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Searched refs:SRSS_CLK_FLL_CONFIG4 (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1459 SRSS_CLK_FLL_CONFIG4 &= ~SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; in Cy_SysClk_FllDisable()
1645 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange… in Cy_SysClk_FllManualConfigure()
1646 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq)… in Cy_SysClk_FllManualConfigure()
1674 tempReg = SRSS_CLK_FLL_CONFIG4; in Cy_SysClk_FllGetConfiguration()
1690 SRSS_CLK_FLL_CONFIG4 |= SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; in Cy_SysClk_FllEnable()
Dcy_sysclk_v2.c2865 SRSS_CLK_FLL_CONFIG4 &= ~SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; in Cy_SysClk_FllDisable()
3067 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange… in Cy_SysClk_FllManualConfigure()
3068 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq)… in Cy_SysClk_FllManualConfigure()
3100 tempReg = SRSS_CLK_FLL_CONFIG4; in Cy_SysClk_FllGetConfiguration()
3120 SRSS_CLK_FLL_CONFIG4 |= SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk; in Cy_SysClk_FllEnable()
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h263 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG4) macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h227 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4) macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h933 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4) macro