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Searched refs:SCB_I2C_CTRL (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_scb_i2c.c102 SCB_I2C_CTRL(base) = _BOOL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, !config->ackGeneralAddr) | in Cy_SCB_I2C_Init()
182 SCB_I2C_CTRL(base) = CY_SCB_I2C_CTRL_DEF_VAL; in Cy_SCB_I2C_DeInit()
553 if (((uint32_t) CY_SCB_I2C_SLAVE) == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, SCB_I2C_CTRL(base))) in Cy_SCB_I2C_SetDataRate()
729 if (((uint32_t) CY_SCB_I2C_SLAVE) == _FLD2VAL(CY_SCB_I2C_CTRL_MODE, SCB_I2C_CTRL(base))) in Cy_SCB_I2C_GetDataRate()
759 dutyCycle = _FLD2VAL(SCB_I2C_CTRL_LOW_PHASE_OVS, SCB_I2C_CTRL(base)) + in Cy_SCB_I2C_GetDataRate()
760 _FLD2VAL(SCB_I2C_CTRL_HIGH_PHASE_OVS, SCB_I2C_CTRL(base)) + in Cy_SCB_I2C_GetDataRate()
1078 SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; in Cy_SCB_I2C_SlaveAbortWrite()
1312 SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_M_READY_DATA_ACK_Msk; in Cy_SCB_I2C_MasterRead()
2439 if (!_FLD2BOOL(SCB_I2C_CTRL_S_GENERAL_IGNORE, SCB_I2C_CTRL(base))) in SlaveHandleAddress()
2512 SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk; in SlaveHandleAddress()
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Dcy_scb_ezi2c.c95 SCB_I2C_CTRL(base) = CY_SCB_EZI2C_I2C_CTRL; in Cy_SCB_EZI2C_Init()
160 SCB_I2C_CTRL(base) = CY_SCB_I2C_CTRL_DEF_VAL; in Cy_SCB_EZI2C_DeInit()
1003 SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk; in UpdateRxFifoLevel()
1121 SCB_I2C_CTRL(base) |= SCB_I2C_CTRL_S_READY_DATA_ACK_Msk; in HandleDataReceive()
1252 SCB_I2C_CTRL(base) &= (uint32_t) ~(SCB_I2C_CTRL_S_READY_DATA_ACK_Msk | in HandleStop()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_scb_i2c.h1284 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_LOW_PHASE_OVS, (clockCycles - 1UL)); in Cy_SCB_I2C_MasterSetLowPhaseDutyCycle()
1313 CY_REG32_CLR_SET(SCB_I2C_CTRL(base), SCB_I2C_CTRL_HIGH_PHASE_OVS, (clockCycles - 1UL)); in Cy_SCB_I2C_MasterSetHighPhaseDutyCycle()
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h1152 #define SCB_I2C_CTRL(base) (((CySCB_V1_Type*) (base))->I2C_CTRL) macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1800 #define SCB_I2C_CTRL(base) (((CySCB_Type*) (base))->I2C_CTRL) macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h481 #define SCB_I2C_CTRL(base) (((CySCB_Type*) (base))->I2C_CTRL) macro