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Searched refs:REG_I2S_TR_CTL (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_i2s.c66 REG_I2S_TR_CTL(base) = 0UL; /* Disable any DMA triggers */ in Cy_I2S_Init()
179 REG_I2S_TR_CTL(base) |= _BOOL2FLD(I2S_TR_CTL_TX_REQ_EN, config->txDmaTrigger); in Cy_I2S_Init()
186 REG_I2S_TR_CTL(base) |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger); in Cy_I2S_Init()
212 REG_I2S_TR_CTL(base) = 0UL; in Cy_I2S_DeInit()
/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_audio_common.c1607 pdl_config->txDmaTrigger = _FLD2BOOL(I2S_TR_CTL_TX_REQ_EN, REG_I2S_TR_CTL(base)); in _cyhal_audioss_reconstruct_pdl_config()
1609 pdl_config->rxDmaTrigger = _FLD2BOOL(I2S_TR_CTL_RX_REQ_EN, REG_I2S_TR_CTL(base));; in _cyhal_audioss_reconstruct_pdl_config()
2678 REG_I2S_TR_CTL(obj->base) |= I2S_TR_CTL_RX_REQ_EN_Msk;
2682 REG_I2S_TR_CTL(obj->base) |= I2S_TR_CTL_TX_REQ_EN_Msk;
2701 REG_I2S_TR_CTL(obj->base) &= ~I2S_TR_CTL_RX_REQ_EN_Msk;
2705 REG_I2S_TR_CTL(obj->base) &= ~I2S_TR_CTL_TX_REQ_EN_Msk;
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h934 #define REG_I2S_TR_CTL(base) (((I2S_V1_Type*)(base))->TR_CTL) macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1609 #define REG_I2S_TR_CTL(base) (((I2S_Type*)(base))->TR_CTL) macro