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Searched refs:PWSR (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dppu_v1.c64 while ((ppu->PWSR & (PPU_V1_PWSR_PWR_STATUS | PPU_V1_PWSR_PWR_DYN_STATUS)) in ppu_v1_set_power_mode()
96 while ((ppu->PWSR & PPU_V1_PWSR_OP_DYN_STATUS) == 0) in ppu_v1_opmode_dynamic_enable()
110 while ((ppu->PWSR & PPU_V1_PWSR_PWR_DYN_STATUS) == 0) in ppu_v1_dynamic_enable()
132 return (enum ppu_v1_mode)(ppu->PWSR & PPU_V1_PWSR_PWR_STATUS); in ppu_v1_get_power_mode()
147 ((ppu->PWSR & PPU_V1_PWSR_OP_STATUS) >> PPU_V1_PWSR_OP_STATUS_POS); in ppu_v1_get_operating_mode()
162 return ((ppu->PWSR & PPU_V1_PWSR_PWR_DYN_STATUS) != 0); in ppu_v1_is_dynamic_enabled()
169 return ((ppu->PWSR & PPU_V1_PWSR_OFF_LOCK_STATUS) != 0); in ppu_v1_is_locked()
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_cpuss_ppu.h44 __IM uint32_t PWSR; /*!< 0x00000008 Power Status Register */ member
Dcyip_pwrmode.h56 __IM uint32_t PWSR; /*!< 0x00000008 Power Status Register */ member
Dcyip_ramc_ppu.h44 __IM uint32_t PWSR; /*!< 0x00000008 Power Status Register */ member
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dppu_v1.h47 __IM uint32_t PWSR; member