Searched refs:PHYREG_00_BMCR (Results 1 – 2 of 2) sorted by relevance
| /hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_ephy.c | 134 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
135 phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig | PHYBMCR_RESET_Msk ) ); in Cy_EPHY_Reset()
139 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
148 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
149 phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig & ( ~PHYBMCR_RESET_Msk ) ) ); in Cy_EPHY_Reset()
186 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Configure()
253 phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, phy->bmcr); in Cy_EPHY_Configure()
281 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &status); in Cy_EPHY_GetLinkStatus()
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| /hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_ephy.h | 114 #define PHYREG_00_BMCR (0x00UL) /**< Basic Mode Control Register. */ macro
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