1 /***************************************************************************//** 2 * \file cyip_peri.h 3 * 4 * \brief 5 * PERI IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PERI_H_ 28 #define _CYIP_PERI_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PERI 34 *******************************************************************************/ 35 36 #define PERI_GR_SECTION_SIZE 0x00000040UL 37 #define PERI_TR_GR_SECTION_SIZE 0x00000200UL 38 #define PERI_PPU_PR_SECTION_SIZE 0x00000040UL 39 #define PERI_PPU_GR_SECTION_SIZE 0x00000040UL 40 #define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL 41 #define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL 42 #define PERI_SECTION_SIZE 0x00010000UL 43 44 /** 45 * \brief Peripheral group structure (PERI_GR) 46 */ 47 typedef struct { 48 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ 49 __IM uint32_t RESERVED[7]; 50 __IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */ 51 __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */ 52 __IM uint32_t RESERVED1[6]; 53 } PERI_GR_V1_Type; /*!< Size = 64 (0x40) */ 54 55 /** 56 * \brief Trigger group (PERI_TR_GR) 57 */ 58 typedef struct { 59 __IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */ 60 } PERI_TR_GR_V1_Type; /*!< Size = 512 (0x200) */ 61 62 /** 63 * \brief PPU structure with programmable address (PERI_PPU_PR) 64 */ 65 typedef struct { 66 __IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 67 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 68 __IM uint32_t RESERVED[6]; 69 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 70 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 71 __IM uint32_t RESERVED1[6]; 72 } PERI_PPU_PR_V1_Type; /*!< Size = 64 (0x40) */ 73 74 /** 75 * \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR) 76 */ 77 typedef struct { 78 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 79 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 80 __IM uint32_t RESERVED[6]; 81 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 82 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 83 __IM uint32_t RESERVED1[6]; 84 } PERI_PPU_GR_V1_Type; /*!< Size = 64 (0x40) */ 85 86 /** 87 * \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL) 88 */ 89 typedef struct { 90 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 91 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 92 __IM uint32_t RESERVED[6]; 93 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 94 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 95 __IM uint32_t RESERVED1[6]; 96 } PERI_GR_PPU_SL_V1_Type; /*!< Size = 64 (0x40) */ 97 98 /** 99 * \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG) 100 */ 101 typedef struct { 102 __IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */ 103 __IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */ 104 __IM uint32_t RESERVED[6]; 105 __IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */ 106 __IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */ 107 __IM uint32_t RESERVED1[6]; 108 } PERI_GR_PPU_RG_V1_Type; /*!< Size = 64 (0x40) */ 109 110 /** 111 * \brief Peripheral interconnect (PERI) 112 */ 113 typedef struct { 114 PERI_GR_V1_Type GR[16]; /*!< 0x00000000 Peripheral group structure */ 115 __IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */ 116 __IM uint32_t RESERVED[255]; 117 __IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */ 118 __IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */ 119 __IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */ 120 __IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */ 121 __IM uint32_t RESERVED1; 122 __IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */ 123 __IM uint32_t RESERVED2[128]; 124 __IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */ 125 __IM uint32_t RESERVED3[1023]; 126 PERI_TR_GR_V1_Type TR_GR[16]; /*!< 0x00002000 Trigger group */ 127 PERI_PPU_PR_V1_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */ 128 __IM uint32_t RESERVED4[512]; 129 PERI_PPU_GR_V1_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral 130 group */ 131 } PERI_V1_Type; /*!< Size = 21504 (0x5400) */ 132 133 134 /* PERI_GR.CLOCK_CTL */ 135 #define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL 136 #define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL 137 /* PERI_GR.SL_CTL */ 138 #define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL 139 #define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL 140 #define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL 141 #define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL 142 #define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL 143 #define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL 144 #define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL 145 #define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL 146 #define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL 147 #define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL 148 #define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL 149 #define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL 150 #define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL 151 #define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL 152 #define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL 153 #define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL 154 #define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL 155 #define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL 156 #define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL 157 #define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL 158 #define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL 159 #define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL 160 #define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL 161 #define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL 162 #define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL 163 #define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL 164 #define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL 165 #define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL 166 #define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL 167 #define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL 168 #define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL 169 #define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL 170 /* PERI_GR.TIMEOUT_CTL */ 171 #define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos 0UL 172 #define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL 173 174 175 /* PERI_TR_GR.TR_OUT_CTL */ 176 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos 0UL 177 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk 0xFFUL 178 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos 8UL 179 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk 0x100UL 180 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos 9UL 181 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk 0x200UL 182 183 184 /* PERI_PPU_PR.ADDR0 */ 185 #define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos 0UL 186 #define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 187 #define PERI_PPU_PR_ADDR0_ADDR24_Pos 8UL 188 #define PERI_PPU_PR_ADDR0_ADDR24_Msk 0xFFFFFF00UL 189 /* PERI_PPU_PR.ATT0 */ 190 #define PERI_PPU_PR_ATT0_UR_Pos 0UL 191 #define PERI_PPU_PR_ATT0_UR_Msk 0x1UL 192 #define PERI_PPU_PR_ATT0_UW_Pos 1UL 193 #define PERI_PPU_PR_ATT0_UW_Msk 0x2UL 194 #define PERI_PPU_PR_ATT0_UX_Pos 2UL 195 #define PERI_PPU_PR_ATT0_UX_Msk 0x4UL 196 #define PERI_PPU_PR_ATT0_PR_Pos 3UL 197 #define PERI_PPU_PR_ATT0_PR_Msk 0x8UL 198 #define PERI_PPU_PR_ATT0_PW_Pos 4UL 199 #define PERI_PPU_PR_ATT0_PW_Msk 0x10UL 200 #define PERI_PPU_PR_ATT0_PX_Pos 5UL 201 #define PERI_PPU_PR_ATT0_PX_Msk 0x20UL 202 #define PERI_PPU_PR_ATT0_NS_Pos 6UL 203 #define PERI_PPU_PR_ATT0_NS_Msk 0x40UL 204 #define PERI_PPU_PR_ATT0_PC_MASK_0_Pos 8UL 205 #define PERI_PPU_PR_ATT0_PC_MASK_0_Msk 0x100UL 206 #define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos 9UL 207 #define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 208 #define PERI_PPU_PR_ATT0_REGION_SIZE_Pos 24UL 209 #define PERI_PPU_PR_ATT0_REGION_SIZE_Msk 0x1F000000UL 210 #define PERI_PPU_PR_ATT0_PC_MATCH_Pos 30UL 211 #define PERI_PPU_PR_ATT0_PC_MATCH_Msk 0x40000000UL 212 #define PERI_PPU_PR_ATT0_ENABLED_Pos 31UL 213 #define PERI_PPU_PR_ATT0_ENABLED_Msk 0x80000000UL 214 /* PERI_PPU_PR.ADDR1 */ 215 #define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos 0UL 216 #define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 217 #define PERI_PPU_PR_ADDR1_ADDR24_Pos 8UL 218 #define PERI_PPU_PR_ADDR1_ADDR24_Msk 0xFFFFFF00UL 219 /* PERI_PPU_PR.ATT1 */ 220 #define PERI_PPU_PR_ATT1_UR_Pos 0UL 221 #define PERI_PPU_PR_ATT1_UR_Msk 0x1UL 222 #define PERI_PPU_PR_ATT1_UW_Pos 1UL 223 #define PERI_PPU_PR_ATT1_UW_Msk 0x2UL 224 #define PERI_PPU_PR_ATT1_UX_Pos 2UL 225 #define PERI_PPU_PR_ATT1_UX_Msk 0x4UL 226 #define PERI_PPU_PR_ATT1_PR_Pos 3UL 227 #define PERI_PPU_PR_ATT1_PR_Msk 0x8UL 228 #define PERI_PPU_PR_ATT1_PW_Pos 4UL 229 #define PERI_PPU_PR_ATT1_PW_Msk 0x10UL 230 #define PERI_PPU_PR_ATT1_PX_Pos 5UL 231 #define PERI_PPU_PR_ATT1_PX_Msk 0x20UL 232 #define PERI_PPU_PR_ATT1_NS_Pos 6UL 233 #define PERI_PPU_PR_ATT1_NS_Msk 0x40UL 234 #define PERI_PPU_PR_ATT1_PC_MASK_0_Pos 8UL 235 #define PERI_PPU_PR_ATT1_PC_MASK_0_Msk 0x100UL 236 #define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos 9UL 237 #define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 238 #define PERI_PPU_PR_ATT1_REGION_SIZE_Pos 24UL 239 #define PERI_PPU_PR_ATT1_REGION_SIZE_Msk 0x1F000000UL 240 #define PERI_PPU_PR_ATT1_PC_MATCH_Pos 30UL 241 #define PERI_PPU_PR_ATT1_PC_MATCH_Msk 0x40000000UL 242 #define PERI_PPU_PR_ATT1_ENABLED_Pos 31UL 243 #define PERI_PPU_PR_ATT1_ENABLED_Msk 0x80000000UL 244 245 246 /* PERI_PPU_GR.ADDR0 */ 247 #define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos 0UL 248 #define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 249 #define PERI_PPU_GR_ADDR0_ADDR24_Pos 8UL 250 #define PERI_PPU_GR_ADDR0_ADDR24_Msk 0xFFFFFF00UL 251 /* PERI_PPU_GR.ATT0 */ 252 #define PERI_PPU_GR_ATT0_UR_Pos 0UL 253 #define PERI_PPU_GR_ATT0_UR_Msk 0x1UL 254 #define PERI_PPU_GR_ATT0_UW_Pos 1UL 255 #define PERI_PPU_GR_ATT0_UW_Msk 0x2UL 256 #define PERI_PPU_GR_ATT0_UX_Pos 2UL 257 #define PERI_PPU_GR_ATT0_UX_Msk 0x4UL 258 #define PERI_PPU_GR_ATT0_PR_Pos 3UL 259 #define PERI_PPU_GR_ATT0_PR_Msk 0x8UL 260 #define PERI_PPU_GR_ATT0_PW_Pos 4UL 261 #define PERI_PPU_GR_ATT0_PW_Msk 0x10UL 262 #define PERI_PPU_GR_ATT0_PX_Pos 5UL 263 #define PERI_PPU_GR_ATT0_PX_Msk 0x20UL 264 #define PERI_PPU_GR_ATT0_NS_Pos 6UL 265 #define PERI_PPU_GR_ATT0_NS_Msk 0x40UL 266 #define PERI_PPU_GR_ATT0_PC_MASK_0_Pos 8UL 267 #define PERI_PPU_GR_ATT0_PC_MASK_0_Msk 0x100UL 268 #define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos 9UL 269 #define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 270 #define PERI_PPU_GR_ATT0_REGION_SIZE_Pos 24UL 271 #define PERI_PPU_GR_ATT0_REGION_SIZE_Msk 0x1F000000UL 272 #define PERI_PPU_GR_ATT0_PC_MATCH_Pos 30UL 273 #define PERI_PPU_GR_ATT0_PC_MATCH_Msk 0x40000000UL 274 #define PERI_PPU_GR_ATT0_ENABLED_Pos 31UL 275 #define PERI_PPU_GR_ATT0_ENABLED_Msk 0x80000000UL 276 /* PERI_PPU_GR.ADDR1 */ 277 #define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos 0UL 278 #define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 279 #define PERI_PPU_GR_ADDR1_ADDR24_Pos 8UL 280 #define PERI_PPU_GR_ADDR1_ADDR24_Msk 0xFFFFFF00UL 281 /* PERI_PPU_GR.ATT1 */ 282 #define PERI_PPU_GR_ATT1_UR_Pos 0UL 283 #define PERI_PPU_GR_ATT1_UR_Msk 0x1UL 284 #define PERI_PPU_GR_ATT1_UW_Pos 1UL 285 #define PERI_PPU_GR_ATT1_UW_Msk 0x2UL 286 #define PERI_PPU_GR_ATT1_UX_Pos 2UL 287 #define PERI_PPU_GR_ATT1_UX_Msk 0x4UL 288 #define PERI_PPU_GR_ATT1_PR_Pos 3UL 289 #define PERI_PPU_GR_ATT1_PR_Msk 0x8UL 290 #define PERI_PPU_GR_ATT1_PW_Pos 4UL 291 #define PERI_PPU_GR_ATT1_PW_Msk 0x10UL 292 #define PERI_PPU_GR_ATT1_PX_Pos 5UL 293 #define PERI_PPU_GR_ATT1_PX_Msk 0x20UL 294 #define PERI_PPU_GR_ATT1_NS_Pos 6UL 295 #define PERI_PPU_GR_ATT1_NS_Msk 0x40UL 296 #define PERI_PPU_GR_ATT1_PC_MASK_0_Pos 8UL 297 #define PERI_PPU_GR_ATT1_PC_MASK_0_Msk 0x100UL 298 #define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos 9UL 299 #define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 300 #define PERI_PPU_GR_ATT1_REGION_SIZE_Pos 24UL 301 #define PERI_PPU_GR_ATT1_REGION_SIZE_Msk 0x1F000000UL 302 #define PERI_PPU_GR_ATT1_PC_MATCH_Pos 30UL 303 #define PERI_PPU_GR_ATT1_PC_MATCH_Msk 0x40000000UL 304 #define PERI_PPU_GR_ATT1_ENABLED_Pos 31UL 305 #define PERI_PPU_GR_ATT1_ENABLED_Msk 0x80000000UL 306 307 308 /* PERI_GR_PPU_SL.ADDR0 */ 309 #define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos 0UL 310 #define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 311 #define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos 8UL 312 #define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk 0xFFFFFF00UL 313 /* PERI_GR_PPU_SL.ATT0 */ 314 #define PERI_GR_PPU_SL_ATT0_UR_Pos 0UL 315 #define PERI_GR_PPU_SL_ATT0_UR_Msk 0x1UL 316 #define PERI_GR_PPU_SL_ATT0_UW_Pos 1UL 317 #define PERI_GR_PPU_SL_ATT0_UW_Msk 0x2UL 318 #define PERI_GR_PPU_SL_ATT0_UX_Pos 2UL 319 #define PERI_GR_PPU_SL_ATT0_UX_Msk 0x4UL 320 #define PERI_GR_PPU_SL_ATT0_PR_Pos 3UL 321 #define PERI_GR_PPU_SL_ATT0_PR_Msk 0x8UL 322 #define PERI_GR_PPU_SL_ATT0_PW_Pos 4UL 323 #define PERI_GR_PPU_SL_ATT0_PW_Msk 0x10UL 324 #define PERI_GR_PPU_SL_ATT0_PX_Pos 5UL 325 #define PERI_GR_PPU_SL_ATT0_PX_Msk 0x20UL 326 #define PERI_GR_PPU_SL_ATT0_NS_Pos 6UL 327 #define PERI_GR_PPU_SL_ATT0_NS_Msk 0x40UL 328 #define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos 8UL 329 #define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk 0x100UL 330 #define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos 9UL 331 #define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 332 #define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos 24UL 333 #define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk 0x1F000000UL 334 #define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos 30UL 335 #define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk 0x40000000UL 336 #define PERI_GR_PPU_SL_ATT0_ENABLED_Pos 31UL 337 #define PERI_GR_PPU_SL_ATT0_ENABLED_Msk 0x80000000UL 338 /* PERI_GR_PPU_SL.ADDR1 */ 339 #define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos 0UL 340 #define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 341 #define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos 8UL 342 #define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk 0xFFFFFF00UL 343 /* PERI_GR_PPU_SL.ATT1 */ 344 #define PERI_GR_PPU_SL_ATT1_UR_Pos 0UL 345 #define PERI_GR_PPU_SL_ATT1_UR_Msk 0x1UL 346 #define PERI_GR_PPU_SL_ATT1_UW_Pos 1UL 347 #define PERI_GR_PPU_SL_ATT1_UW_Msk 0x2UL 348 #define PERI_GR_PPU_SL_ATT1_UX_Pos 2UL 349 #define PERI_GR_PPU_SL_ATT1_UX_Msk 0x4UL 350 #define PERI_GR_PPU_SL_ATT1_PR_Pos 3UL 351 #define PERI_GR_PPU_SL_ATT1_PR_Msk 0x8UL 352 #define PERI_GR_PPU_SL_ATT1_PW_Pos 4UL 353 #define PERI_GR_PPU_SL_ATT1_PW_Msk 0x10UL 354 #define PERI_GR_PPU_SL_ATT1_PX_Pos 5UL 355 #define PERI_GR_PPU_SL_ATT1_PX_Msk 0x20UL 356 #define PERI_GR_PPU_SL_ATT1_NS_Pos 6UL 357 #define PERI_GR_PPU_SL_ATT1_NS_Msk 0x40UL 358 #define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos 8UL 359 #define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk 0x100UL 360 #define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos 9UL 361 #define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 362 #define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos 24UL 363 #define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk 0x1F000000UL 364 #define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos 30UL 365 #define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk 0x40000000UL 366 #define PERI_GR_PPU_SL_ATT1_ENABLED_Pos 31UL 367 #define PERI_GR_PPU_SL_ATT1_ENABLED_Msk 0x80000000UL 368 369 370 /* PERI_GR_PPU_RG.ADDR0 */ 371 #define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos 0UL 372 #define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL 373 #define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos 8UL 374 #define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk 0xFFFFFF00UL 375 /* PERI_GR_PPU_RG.ATT0 */ 376 #define PERI_GR_PPU_RG_ATT0_UR_Pos 0UL 377 #define PERI_GR_PPU_RG_ATT0_UR_Msk 0x1UL 378 #define PERI_GR_PPU_RG_ATT0_UW_Pos 1UL 379 #define PERI_GR_PPU_RG_ATT0_UW_Msk 0x2UL 380 #define PERI_GR_PPU_RG_ATT0_UX_Pos 2UL 381 #define PERI_GR_PPU_RG_ATT0_UX_Msk 0x4UL 382 #define PERI_GR_PPU_RG_ATT0_PR_Pos 3UL 383 #define PERI_GR_PPU_RG_ATT0_PR_Msk 0x8UL 384 #define PERI_GR_PPU_RG_ATT0_PW_Pos 4UL 385 #define PERI_GR_PPU_RG_ATT0_PW_Msk 0x10UL 386 #define PERI_GR_PPU_RG_ATT0_PX_Pos 5UL 387 #define PERI_GR_PPU_RG_ATT0_PX_Msk 0x20UL 388 #define PERI_GR_PPU_RG_ATT0_NS_Pos 6UL 389 #define PERI_GR_PPU_RG_ATT0_NS_Msk 0x40UL 390 #define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos 8UL 391 #define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk 0x100UL 392 #define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos 9UL 393 #define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL 394 #define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos 24UL 395 #define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk 0x1F000000UL 396 #define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos 30UL 397 #define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk 0x40000000UL 398 #define PERI_GR_PPU_RG_ATT0_ENABLED_Pos 31UL 399 #define PERI_GR_PPU_RG_ATT0_ENABLED_Msk 0x80000000UL 400 /* PERI_GR_PPU_RG.ADDR1 */ 401 #define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos 0UL 402 #define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL 403 #define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos 8UL 404 #define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk 0xFFFFFF00UL 405 /* PERI_GR_PPU_RG.ATT1 */ 406 #define PERI_GR_PPU_RG_ATT1_UR_Pos 0UL 407 #define PERI_GR_PPU_RG_ATT1_UR_Msk 0x1UL 408 #define PERI_GR_PPU_RG_ATT1_UW_Pos 1UL 409 #define PERI_GR_PPU_RG_ATT1_UW_Msk 0x2UL 410 #define PERI_GR_PPU_RG_ATT1_UX_Pos 2UL 411 #define PERI_GR_PPU_RG_ATT1_UX_Msk 0x4UL 412 #define PERI_GR_PPU_RG_ATT1_PR_Pos 3UL 413 #define PERI_GR_PPU_RG_ATT1_PR_Msk 0x8UL 414 #define PERI_GR_PPU_RG_ATT1_PW_Pos 4UL 415 #define PERI_GR_PPU_RG_ATT1_PW_Msk 0x10UL 416 #define PERI_GR_PPU_RG_ATT1_PX_Pos 5UL 417 #define PERI_GR_PPU_RG_ATT1_PX_Msk 0x20UL 418 #define PERI_GR_PPU_RG_ATT1_NS_Pos 6UL 419 #define PERI_GR_PPU_RG_ATT1_NS_Msk 0x40UL 420 #define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos 8UL 421 #define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk 0x100UL 422 #define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos 9UL 423 #define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL 424 #define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos 24UL 425 #define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk 0x1F000000UL 426 #define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos 30UL 427 #define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk 0x40000000UL 428 #define PERI_GR_PPU_RG_ATT1_ENABLED_Pos 31UL 429 #define PERI_GR_PPU_RG_ATT1_ENABLED_Msk 0x80000000UL 430 431 432 /* PERI.DIV_CMD */ 433 #define PERI_DIV_CMD_DIV_SEL_Pos 0UL 434 #define PERI_DIV_CMD_DIV_SEL_Msk 0x3FUL 435 #define PERI_DIV_CMD_TYPE_SEL_Pos 6UL 436 #define PERI_DIV_CMD_TYPE_SEL_Msk 0xC0UL 437 #define PERI_DIV_CMD_PA_DIV_SEL_Pos 8UL 438 #define PERI_DIV_CMD_PA_DIV_SEL_Msk 0x3F00UL 439 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos 14UL 440 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk 0xC000UL 441 #define PERI_DIV_CMD_DISABLE_Pos 30UL 442 #define PERI_DIV_CMD_DISABLE_Msk 0x40000000UL 443 #define PERI_DIV_CMD_ENABLE_Pos 31UL 444 #define PERI_DIV_CMD_ENABLE_Msk 0x80000000UL 445 /* PERI.DIV_8_CTL */ 446 #define PERI_DIV_8_CTL_EN_Pos 0UL 447 #define PERI_DIV_8_CTL_EN_Msk 0x1UL 448 #define PERI_DIV_8_CTL_INT8_DIV_Pos 8UL 449 #define PERI_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL 450 /* PERI.DIV_16_CTL */ 451 #define PERI_DIV_16_CTL_EN_Pos 0UL 452 #define PERI_DIV_16_CTL_EN_Msk 0x1UL 453 #define PERI_DIV_16_CTL_INT16_DIV_Pos 8UL 454 #define PERI_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL 455 /* PERI.DIV_16_5_CTL */ 456 #define PERI_DIV_16_5_CTL_EN_Pos 0UL 457 #define PERI_DIV_16_5_CTL_EN_Msk 0x1UL 458 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL 459 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL 460 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos 8UL 461 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL 462 /* PERI.DIV_24_5_CTL */ 463 #define PERI_DIV_24_5_CTL_EN_Pos 0UL 464 #define PERI_DIV_24_5_CTL_EN_Msk 0x1UL 465 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL 466 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL 467 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos 8UL 468 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL 469 /* PERI.CLOCK_CTL */ 470 #define PERI_CLOCK_CTL_DIV_SEL_Pos 0UL 471 #define PERI_CLOCK_CTL_DIV_SEL_Msk 0x3FUL 472 #define PERI_CLOCK_CTL_TYPE_SEL_Pos 6UL 473 #define PERI_CLOCK_CTL_TYPE_SEL_Msk 0xC0UL 474 /* PERI.TR_CMD */ 475 #define PERI_TR_CMD_TR_SEL_Pos 0UL 476 #define PERI_TR_CMD_TR_SEL_Msk 0xFFUL 477 #define PERI_TR_CMD_GROUP_SEL_Pos 8UL 478 #define PERI_TR_CMD_GROUP_SEL_Msk 0xF00UL 479 #define PERI_TR_CMD_COUNT_Pos 16UL 480 #define PERI_TR_CMD_COUNT_Msk 0xFF0000UL 481 #define PERI_TR_CMD_OUT_SEL_Pos 30UL 482 #define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL 483 #define PERI_TR_CMD_ACTIVATE_Pos 31UL 484 #define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL 485 486 487 #endif /* _CYIP_PERI_H_ */ 488 489 490 /* [] END OF FILE */ 491
