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Searched refs:PDR1 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.6.0/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c621 PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; in SystemCoreClockSetup()
626 PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; in SystemCoreClockSetup()
/hal_infineon-3.6.0/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c672 PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; in SystemCoreClockSetup()
677 PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; in SystemCoreClockSetup()
/hal_infineon-3.6.0/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c771 PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk; in SystemCoreClockSetup()
776 PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk; in SystemCoreClockSetup()
/hal_infineon-3.6.0/XMCLib/devices/XMC4700/Include/
DXMC4700.h2204 …__IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Reg… member
2234 …__IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Reg… member
2264 …__IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Reg… member
2294 …__IO uint32_t PDR1; /*!< (@ 0x48028344) Port 3 Pad Driver Mode 1 Reg… member
2350 …__IO uint32_t PDR1; /*!< (@ 0x48028544) Port 5 Pad Driver Mode 1 Reg… member
2406 …__IO uint32_t PDR1; /*!< (@ 0x48028744) Port 7 Pad Driver Mode 1 Reg… member
2435 …__IO uint32_t PDR1; /*!< (@ 0x48028844) Port 8 Pad Driver Mode 1 Reg… member
2464 …__IO uint32_t PDR1; /*!< (@ 0x48028944) Port 9 Pad Driver Mode 1 Reg… member
/hal_infineon-3.6.0/XMCLib/devices/XMC4800/Include/
DXMC4800.h2424 …__IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Reg… member
2454 …__IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Reg… member
2484 …__IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Reg… member
2514 …__IO uint32_t PDR1; /*!< (@ 0x48028344) Port 3 Pad Driver Mode 1 Reg… member
2570 …__IO uint32_t PDR1; /*!< (@ 0x48028544) Port 5 Pad Driver Mode 1 Reg… member
2626 …__IO uint32_t PDR1; /*!< (@ 0x48028744) Port 7 Pad Driver Mode 1 Reg… member
2655 …__IO uint32_t PDR1; /*!< (@ 0x48028844) Port 8 Pad Driver Mode 1 Reg… member
2684 …__IO uint32_t PDR1; /*!< (@ 0x48028944) Port 9 Pad Driver Mode 1 Reg… member
/hal_infineon-3.6.0/XMCLib/devices/XMC4500/Include/
DXMC4500.h2172 …__IO uint32_t PDR1; /*!< (@ 0x48028044) Port 0 Pad Driver Mode 1 Reg… member
2202 …__IO uint32_t PDR1; /*!< (@ 0x48028144) Port 1 Pad Driver Mode 1 Reg… member
2232 …__IO uint32_t PDR1; /*!< (@ 0x48028244) Port 2 Pad Driver Mode 1 Reg… member
2262 …__IO uint32_t PDR1; /*!< (@ 0x48028344) Port 3 Pad Driver Mode 1 Reg… member
2318 …__IO uint32_t PDR1; /*!< (@ 0x48028544) Port 5 Pad Driver Mode 1 Reg… member