1 /***************************************************************************//** 2 * \file cyip_pdm.h 3 * 4 * \brief 5 * PDM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PDM_H_ 28 #define _CYIP_PDM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PDM 34 *******************************************************************************/ 35 36 #define PDM_CH_SECTION_SIZE 0x00000100UL 37 #define PDM_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief PDM RX structure (PDM_CH) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t RESERVED[3]; 45 __IOM uint32_t IF_CTL; /*!< 0x00000010 Interface control */ 46 __IOM uint32_t CIC_CTL; /*!< 0x00000014 CIC control */ 47 __IOM uint32_t FIR0_CTL; /*!< 0x00000018 FIR 0 control */ 48 __IOM uint32_t FIR1_CTL; /*!< 0x0000001C FIR 1 control */ 49 __IOM uint32_t DC_BLOCK_CTL; /*!< 0x00000020 DC block control */ 50 __IM uint32_t RESERVED1[23]; 51 __IOM uint32_t RX_FIFO_CTL; /*!< 0x00000080 RX FIFO control */ 52 __IM uint32_t RX_FIFO_STATUS; /*!< 0x00000084 RX FIFO status */ 53 __IM uint32_t RX_FIFO_RD; /*!< 0x00000088 RX FIFO read */ 54 __IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000008C RX FIFO silent read */ 55 __IM uint32_t RESERVED2[12]; 56 __IOM uint32_t INTR_RX; /*!< 0x000000C0 Interrupt */ 57 __IOM uint32_t INTR_RX_SET; /*!< 0x000000C4 Interrupt set */ 58 __IOM uint32_t INTR_RX_MASK; /*!< 0x000000C8 Interrupt mask */ 59 __IM uint32_t INTR_RX_MASKED; /*!< 0x000000CC Interrupt masked */ 60 __IM uint32_t RESERVED3[12]; 61 } PDM_CH_Type; /*!< Size = 256 (0x100) */ 62 63 /** 64 * \brief PDM (PDM) 65 */ 66 typedef struct { 67 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 68 __IOM uint32_t CTL_CLR; /*!< 0x00000004 Control clear */ 69 __IOM uint32_t CTL_SET; /*!< 0x00000008 Control set */ 70 __IM uint32_t RESERVED; 71 __IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */ 72 __IM uint32_t RESERVED1[3]; 73 __IOM uint32_t ROUTE_CTL; /*!< 0x00000020 Route control */ 74 __IM uint32_t RESERVED2[3]; 75 __IOM uint32_t TEST_CTL; /*!< 0x00000030 Test control */ 76 __IM uint32_t RESERVED3[51]; 77 __IOM uint32_t FIR0_COEFF0; /*!< 0x00000100 FIR 0 coefficients 0 */ 78 __IOM uint32_t FIR0_COEFF1; /*!< 0x00000104 FIR 0 coefficients 1 */ 79 __IOM uint32_t FIR0_COEFF2; /*!< 0x00000108 FIR 0 coefficients 2 */ 80 __IOM uint32_t FIR0_COEFF3; /*!< 0x0000010C FIR 0 coefficients 3 */ 81 __IOM uint32_t FIR0_COEFF4; /*!< 0x00000110 FIR 0 coefficients 4 */ 82 __IOM uint32_t FIR0_COEFF5; /*!< 0x00000114 FIR 0 coefficients 5 */ 83 __IOM uint32_t FIR0_COEFF6; /*!< 0x00000118 FIR 0 coefficients 6 */ 84 __IOM uint32_t FIR0_COEFF7; /*!< 0x0000011C FIR 0 coefficients 7 */ 85 __IM uint32_t RESERVED4[8]; 86 __IOM uint32_t FIR1_COEFF0; /*!< 0x00000140 FIR 1 coefficients 0 */ 87 __IOM uint32_t FIR1_COEFF1; /*!< 0x00000144 FIR 1 coefficients 1 */ 88 __IOM uint32_t FIR1_COEFF2; /*!< 0x00000148 FIR 1 coefficients 2 */ 89 __IOM uint32_t FIR1_COEFF3; /*!< 0x0000014C FIR 1 coefficients 3 */ 90 __IOM uint32_t FIR1_COEFF4; /*!< 0x00000150 FIR 1 coefficients 4 */ 91 __IOM uint32_t FIR1_COEFF5; /*!< 0x00000154 FIR 1 coefficients 5 */ 92 __IOM uint32_t FIR1_COEFF6; /*!< 0x00000158 FIR 1 coefficients 6 */ 93 __IOM uint32_t FIR1_COEFF7; /*!< 0x0000015C FIR 1 coefficients 7 */ 94 __IOM uint32_t FIR1_COEFF8; /*!< 0x00000160 FIR 1 coefficients 8 */ 95 __IOM uint32_t FIR1_COEFF9; /*!< 0x00000164 FIR 1 coefficients 9 */ 96 __IOM uint32_t FIR1_COEFF10; /*!< 0x00000168 FIR 1 coefficients 10 */ 97 __IOM uint32_t FIR1_COEFF11; /*!< 0x0000016C FIR 1 coefficients 11 */ 98 __IOM uint32_t FIR1_COEFF12; /*!< 0x00000170 FIR 1 coefficients 12 */ 99 __IOM uint32_t FIR1_COEFF13; /*!< 0x00000174 FIR 1 coefficients 13 */ 100 __IM uint32_t RESERVED5[8098]; 101 PDM_CH_Type CH[8]; /*!< 0x00008000 PDM RX structure */ 102 } PDM_Type; /*!< Size = 34816 (0x8800) */ 103 104 105 /* PDM_CH.CTL */ 106 #define PDM_CH_CTL_WORD_SIZE_Pos 0UL 107 #define PDM_CH_CTL_WORD_SIZE_Msk 0xFUL 108 #define PDM_CH_CTL_WORD_SIGN_EXTEND_Pos 8UL 109 #define PDM_CH_CTL_WORD_SIGN_EXTEND_Msk 0x100UL 110 #define PDM_CH_CTL_ENABLED_Pos 31UL 111 #define PDM_CH_CTL_ENABLED_Msk 0x80000000UL 112 /* PDM_CH.IF_CTL */ 113 #define PDM_CH_IF_CTL_SAMPLE_DELAY_Pos 0UL 114 #define PDM_CH_IF_CTL_SAMPLE_DELAY_Msk 0xFFUL 115 /* PDM_CH.CIC_CTL */ 116 #define PDM_CH_CIC_CTL_DECIM_CODE_Pos 0UL 117 #define PDM_CH_CIC_CTL_DECIM_CODE_Msk 0x7UL 118 /* PDM_CH.FIR0_CTL */ 119 #define PDM_CH_FIR0_CTL_DECIM3_Pos 0UL 120 #define PDM_CH_FIR0_CTL_DECIM3_Msk 0x7UL 121 #define PDM_CH_FIR0_CTL_SCALE_Pos 8UL 122 #define PDM_CH_FIR0_CTL_SCALE_Msk 0x1F00UL 123 #define PDM_CH_FIR0_CTL_ENABLED_Pos 31UL 124 #define PDM_CH_FIR0_CTL_ENABLED_Msk 0x80000000UL 125 /* PDM_CH.FIR1_CTL */ 126 #define PDM_CH_FIR1_CTL_DECIM2_Pos 0UL 127 #define PDM_CH_FIR1_CTL_DECIM2_Msk 0x3UL 128 #define PDM_CH_FIR1_CTL_SCALE_Pos 8UL 129 #define PDM_CH_FIR1_CTL_SCALE_Msk 0x1F00UL 130 #define PDM_CH_FIR1_CTL_ENABLED_Pos 31UL 131 #define PDM_CH_FIR1_CTL_ENABLED_Msk 0x80000000UL 132 /* PDM_CH.DC_BLOCK_CTL */ 133 #define PDM_CH_DC_BLOCK_CTL_CODE_Pos 0UL 134 #define PDM_CH_DC_BLOCK_CTL_CODE_Msk 0x7UL 135 #define PDM_CH_DC_BLOCK_CTL_ENABLED_Pos 31UL 136 #define PDM_CH_DC_BLOCK_CTL_ENABLED_Msk 0x80000000UL 137 /* PDM_CH.RX_FIFO_CTL */ 138 #define PDM_CH_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 139 #define PDM_CH_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0x3FUL 140 #define PDM_CH_RX_FIFO_CTL_FREEZE_Pos 17UL 141 #define PDM_CH_RX_FIFO_CTL_FREEZE_Msk 0x20000UL 142 /* PDM_CH.RX_FIFO_STATUS */ 143 #define PDM_CH_RX_FIFO_STATUS_USED_Pos 0UL 144 #define PDM_CH_RX_FIFO_STATUS_USED_Msk 0x7FUL 145 #define PDM_CH_RX_FIFO_STATUS_RD_PTR_Pos 16UL 146 #define PDM_CH_RX_FIFO_STATUS_RD_PTR_Msk 0x3F0000UL 147 #define PDM_CH_RX_FIFO_STATUS_WR_PTR_Pos 24UL 148 #define PDM_CH_RX_FIFO_STATUS_WR_PTR_Msk 0x3F000000UL 149 /* PDM_CH.RX_FIFO_RD */ 150 #define PDM_CH_RX_FIFO_RD_DATA_Pos 0UL 151 #define PDM_CH_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL 152 /* PDM_CH.RX_FIFO_RD_SILENT */ 153 #define PDM_CH_RX_FIFO_RD_SILENT_DATA_Pos 0UL 154 #define PDM_CH_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL 155 /* PDM_CH.INTR_RX */ 156 #define PDM_CH_INTR_RX_FIFO_TRIGGER_Pos 0UL 157 #define PDM_CH_INTR_RX_FIFO_TRIGGER_Msk 0x1UL 158 #define PDM_CH_INTR_RX_FIFO_OVERFLOW_Pos 1UL 159 #define PDM_CH_INTR_RX_FIFO_OVERFLOW_Msk 0x2UL 160 #define PDM_CH_INTR_RX_FIFO_UNDERFLOW_Pos 2UL 161 #define PDM_CH_INTR_RX_FIFO_UNDERFLOW_Msk 0x4UL 162 #define PDM_CH_INTR_RX_FIR_OVERFLOW_Pos 4UL 163 #define PDM_CH_INTR_RX_FIR_OVERFLOW_Msk 0x10UL 164 #define PDM_CH_INTR_RX_IF_OVERFLOW_Pos 8UL 165 #define PDM_CH_INTR_RX_IF_OVERFLOW_Msk 0x100UL 166 /* PDM_CH.INTR_RX_SET */ 167 #define PDM_CH_INTR_RX_SET_FIFO_TRIGGER_Pos 0UL 168 #define PDM_CH_INTR_RX_SET_FIFO_TRIGGER_Msk 0x1UL 169 #define PDM_CH_INTR_RX_SET_FIFO_OVERFLOW_Pos 1UL 170 #define PDM_CH_INTR_RX_SET_FIFO_OVERFLOW_Msk 0x2UL 171 #define PDM_CH_INTR_RX_SET_FIFO_UNDERFLOW_Pos 2UL 172 #define PDM_CH_INTR_RX_SET_FIFO_UNDERFLOW_Msk 0x4UL 173 #define PDM_CH_INTR_RX_SET_FIR_OVERFLOW_Pos 4UL 174 #define PDM_CH_INTR_RX_SET_FIR_OVERFLOW_Msk 0x10UL 175 #define PDM_CH_INTR_RX_SET_IF_OVERFLOW_Pos 8UL 176 #define PDM_CH_INTR_RX_SET_IF_OVERFLOW_Msk 0x100UL 177 /* PDM_CH.INTR_RX_MASK */ 178 #define PDM_CH_INTR_RX_MASK_FIFO_TRIGGER_Pos 0UL 179 #define PDM_CH_INTR_RX_MASK_FIFO_TRIGGER_Msk 0x1UL 180 #define PDM_CH_INTR_RX_MASK_FIFO_OVERFLOW_Pos 1UL 181 #define PDM_CH_INTR_RX_MASK_FIFO_OVERFLOW_Msk 0x2UL 182 #define PDM_CH_INTR_RX_MASK_FIFO_UNDERFLOW_Pos 2UL 183 #define PDM_CH_INTR_RX_MASK_FIFO_UNDERFLOW_Msk 0x4UL 184 #define PDM_CH_INTR_RX_MASK_FIR_OVERFLOW_Pos 4UL 185 #define PDM_CH_INTR_RX_MASK_FIR_OVERFLOW_Msk 0x10UL 186 #define PDM_CH_INTR_RX_MASK_IF_OVERFLOW_Pos 8UL 187 #define PDM_CH_INTR_RX_MASK_IF_OVERFLOW_Msk 0x100UL 188 /* PDM_CH.INTR_RX_MASKED */ 189 #define PDM_CH_INTR_RX_MASKED_FIFO_TRIGGER_Pos 0UL 190 #define PDM_CH_INTR_RX_MASKED_FIFO_TRIGGER_Msk 0x1UL 191 #define PDM_CH_INTR_RX_MASKED_FIFO_OVERFLOW_Pos 1UL 192 #define PDM_CH_INTR_RX_MASKED_FIFO_OVERFLOW_Msk 0x2UL 193 #define PDM_CH_INTR_RX_MASKED_FIFO_UNDERFLOW_Pos 2UL 194 #define PDM_CH_INTR_RX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL 195 #define PDM_CH_INTR_RX_MASKED_FIR_OVERFLOW_Pos 4UL 196 #define PDM_CH_INTR_RX_MASKED_FIR_OVERFLOW_Msk 0x10UL 197 #define PDM_CH_INTR_RX_MASKED_IF_OVERFLOW_Pos 8UL 198 #define PDM_CH_INTR_RX_MASKED_IF_OVERFLOW_Msk 0x100UL 199 200 201 /* PDM.CTL */ 202 #define PDM_CTL_ACTIVE_Pos 0UL 203 #define PDM_CTL_ACTIVE_Msk 0xFFUL 204 /* PDM.CTL_CLR */ 205 #define PDM_CTL_CLR_ACTIVE_Pos 0UL 206 #define PDM_CTL_CLR_ACTIVE_Msk 0xFFUL 207 /* PDM.CTL_SET */ 208 #define PDM_CTL_SET_ACTIVE_Pos 0UL 209 #define PDM_CTL_SET_ACTIVE_Msk 0xFFUL 210 /* PDM.CLOCK_CTL */ 211 #define PDM_CLOCK_CTL_CLOCK_DIV_Pos 0UL 212 #define PDM_CLOCK_CTL_CLOCK_DIV_Msk 0xFFUL 213 #define PDM_CLOCK_CTL_CLOCK_SEL_Pos 8UL 214 #define PDM_CLOCK_CTL_CLOCK_SEL_Msk 0x300UL 215 #define PDM_CLOCK_CTL_HALVE_Pos 16UL 216 #define PDM_CLOCK_CTL_HALVE_Msk 0x10000UL 217 /* PDM.ROUTE_CTL */ 218 #define PDM_ROUTE_CTL_DATA_SEL_Pos 0UL 219 #define PDM_ROUTE_CTL_DATA_SEL_Msk 0xFFUL 220 /* PDM.TEST_CTL */ 221 #define PDM_TEST_CTL_DRIVE_DELAY_HI_Pos 0UL 222 #define PDM_TEST_CTL_DRIVE_DELAY_HI_Msk 0xFFUL 223 #define PDM_TEST_CTL_DRIVE_DELAY_LO_Pos 8UL 224 #define PDM_TEST_CTL_DRIVE_DELAY_LO_Msk 0xFF00UL 225 #define PDM_TEST_CTL_MODE_HI_Pos 16UL 226 #define PDM_TEST_CTL_MODE_HI_Msk 0x30000UL 227 #define PDM_TEST_CTL_MODE_LO_Pos 18UL 228 #define PDM_TEST_CTL_MODE_LO_Msk 0xC0000UL 229 #define PDM_TEST_CTL_AUDIO_FREQ_DIV_Pos 20UL 230 #define PDM_TEST_CTL_AUDIO_FREQ_DIV_Msk 0xF00000UL 231 #define PDM_TEST_CTL_CH_ENABLED_Pos 24UL 232 #define PDM_TEST_CTL_CH_ENABLED_Msk 0xFF000000UL 233 /* PDM.FIR0_COEFF0 */ 234 #define PDM_FIR0_COEFF0_DATA0_Pos 0UL 235 #define PDM_FIR0_COEFF0_DATA0_Msk 0x3FFFUL 236 #define PDM_FIR0_COEFF0_DATA1_Pos 16UL 237 #define PDM_FIR0_COEFF0_DATA1_Msk 0x3FFF0000UL 238 /* PDM.FIR0_COEFF1 */ 239 #define PDM_FIR0_COEFF1_DATA0_Pos 0UL 240 #define PDM_FIR0_COEFF1_DATA0_Msk 0x3FFFUL 241 #define PDM_FIR0_COEFF1_DATA1_Pos 16UL 242 #define PDM_FIR0_COEFF1_DATA1_Msk 0x3FFF0000UL 243 /* PDM.FIR0_COEFF2 */ 244 #define PDM_FIR0_COEFF2_DATA0_Pos 0UL 245 #define PDM_FIR0_COEFF2_DATA0_Msk 0x3FFFUL 246 #define PDM_FIR0_COEFF2_DATA1_Pos 16UL 247 #define PDM_FIR0_COEFF2_DATA1_Msk 0x3FFF0000UL 248 /* PDM.FIR0_COEFF3 */ 249 #define PDM_FIR0_COEFF3_DATA0_Pos 0UL 250 #define PDM_FIR0_COEFF3_DATA0_Msk 0x3FFFUL 251 #define PDM_FIR0_COEFF3_DATA1_Pos 16UL 252 #define PDM_FIR0_COEFF3_DATA1_Msk 0x3FFF0000UL 253 /* PDM.FIR0_COEFF4 */ 254 #define PDM_FIR0_COEFF4_DATA0_Pos 0UL 255 #define PDM_FIR0_COEFF4_DATA0_Msk 0x3FFFUL 256 #define PDM_FIR0_COEFF4_DATA1_Pos 16UL 257 #define PDM_FIR0_COEFF4_DATA1_Msk 0x3FFF0000UL 258 /* PDM.FIR0_COEFF5 */ 259 #define PDM_FIR0_COEFF5_DATA0_Pos 0UL 260 #define PDM_FIR0_COEFF5_DATA0_Msk 0x3FFFUL 261 #define PDM_FIR0_COEFF5_DATA1_Pos 16UL 262 #define PDM_FIR0_COEFF5_DATA1_Msk 0x3FFF0000UL 263 /* PDM.FIR0_COEFF6 */ 264 #define PDM_FIR0_COEFF6_DATA0_Pos 0UL 265 #define PDM_FIR0_COEFF6_DATA0_Msk 0x3FFFUL 266 #define PDM_FIR0_COEFF6_DATA1_Pos 16UL 267 #define PDM_FIR0_COEFF6_DATA1_Msk 0x3FFF0000UL 268 /* PDM.FIR0_COEFF7 */ 269 #define PDM_FIR0_COEFF7_DATA0_Pos 0UL 270 #define PDM_FIR0_COEFF7_DATA0_Msk 0x3FFFUL 271 #define PDM_FIR0_COEFF7_DATA1_Pos 16UL 272 #define PDM_FIR0_COEFF7_DATA1_Msk 0x3FFF0000UL 273 /* PDM.FIR1_COEFF0 */ 274 #define PDM_FIR1_COEFF0_DATA0_Pos 0UL 275 #define PDM_FIR1_COEFF0_DATA0_Msk 0x3FFFUL 276 #define PDM_FIR1_COEFF0_DATA1_Pos 16UL 277 #define PDM_FIR1_COEFF0_DATA1_Msk 0x3FFF0000UL 278 /* PDM.FIR1_COEFF1 */ 279 #define PDM_FIR1_COEFF1_DATA0_Pos 0UL 280 #define PDM_FIR1_COEFF1_DATA0_Msk 0x3FFFUL 281 #define PDM_FIR1_COEFF1_DATA1_Pos 16UL 282 #define PDM_FIR1_COEFF1_DATA1_Msk 0x3FFF0000UL 283 /* PDM.FIR1_COEFF2 */ 284 #define PDM_FIR1_COEFF2_DATA0_Pos 0UL 285 #define PDM_FIR1_COEFF2_DATA0_Msk 0x3FFFUL 286 #define PDM_FIR1_COEFF2_DATA1_Pos 16UL 287 #define PDM_FIR1_COEFF2_DATA1_Msk 0x3FFF0000UL 288 /* PDM.FIR1_COEFF3 */ 289 #define PDM_FIR1_COEFF3_DATA0_Pos 0UL 290 #define PDM_FIR1_COEFF3_DATA0_Msk 0x3FFFUL 291 #define PDM_FIR1_COEFF3_DATA1_Pos 16UL 292 #define PDM_FIR1_COEFF3_DATA1_Msk 0x3FFF0000UL 293 /* PDM.FIR1_COEFF4 */ 294 #define PDM_FIR1_COEFF4_DATA0_Pos 0UL 295 #define PDM_FIR1_COEFF4_DATA0_Msk 0x3FFFUL 296 #define PDM_FIR1_COEFF4_DATA1_Pos 16UL 297 #define PDM_FIR1_COEFF4_DATA1_Msk 0x3FFF0000UL 298 /* PDM.FIR1_COEFF5 */ 299 #define PDM_FIR1_COEFF5_DATA0_Pos 0UL 300 #define PDM_FIR1_COEFF5_DATA0_Msk 0x3FFFUL 301 #define PDM_FIR1_COEFF5_DATA1_Pos 16UL 302 #define PDM_FIR1_COEFF5_DATA1_Msk 0x3FFF0000UL 303 /* PDM.FIR1_COEFF6 */ 304 #define PDM_FIR1_COEFF6_DATA0_Pos 0UL 305 #define PDM_FIR1_COEFF6_DATA0_Msk 0x3FFFUL 306 #define PDM_FIR1_COEFF6_DATA1_Pos 16UL 307 #define PDM_FIR1_COEFF6_DATA1_Msk 0x3FFF0000UL 308 /* PDM.FIR1_COEFF7 */ 309 #define PDM_FIR1_COEFF7_DATA0_Pos 0UL 310 #define PDM_FIR1_COEFF7_DATA0_Msk 0x3FFFUL 311 #define PDM_FIR1_COEFF7_DATA1_Pos 16UL 312 #define PDM_FIR1_COEFF7_DATA1_Msk 0x3FFF0000UL 313 /* PDM.FIR1_COEFF8 */ 314 #define PDM_FIR1_COEFF8_DATA0_Pos 0UL 315 #define PDM_FIR1_COEFF8_DATA0_Msk 0x3FFFUL 316 #define PDM_FIR1_COEFF8_DATA1_Pos 16UL 317 #define PDM_FIR1_COEFF8_DATA1_Msk 0x3FFF0000UL 318 /* PDM.FIR1_COEFF9 */ 319 #define PDM_FIR1_COEFF9_DATA0_Pos 0UL 320 #define PDM_FIR1_COEFF9_DATA0_Msk 0x3FFFUL 321 #define PDM_FIR1_COEFF9_DATA1_Pos 16UL 322 #define PDM_FIR1_COEFF9_DATA1_Msk 0x3FFF0000UL 323 /* PDM.FIR1_COEFF10 */ 324 #define PDM_FIR1_COEFF10_DATA0_Pos 0UL 325 #define PDM_FIR1_COEFF10_DATA0_Msk 0x3FFFUL 326 #define PDM_FIR1_COEFF10_DATA1_Pos 16UL 327 #define PDM_FIR1_COEFF10_DATA1_Msk 0x3FFF0000UL 328 /* PDM.FIR1_COEFF11 */ 329 #define PDM_FIR1_COEFF11_DATA0_Pos 0UL 330 #define PDM_FIR1_COEFF11_DATA0_Msk 0x3FFFUL 331 #define PDM_FIR1_COEFF11_DATA1_Pos 16UL 332 #define PDM_FIR1_COEFF11_DATA1_Msk 0x3FFF0000UL 333 /* PDM.FIR1_COEFF12 */ 334 #define PDM_FIR1_COEFF12_DATA0_Pos 0UL 335 #define PDM_FIR1_COEFF12_DATA0_Msk 0x3FFFUL 336 #define PDM_FIR1_COEFF12_DATA1_Pos 16UL 337 #define PDM_FIR1_COEFF12_DATA1_Msk 0x3FFF0000UL 338 /* PDM.FIR1_COEFF13 */ 339 #define PDM_FIR1_COEFF13_DATA0_Pos 0UL 340 #define PDM_FIR1_COEFF13_DATA0_Msk 0x3FFFUL 341 #define PDM_FIR1_COEFF13_DATA1_Pos 16UL 342 #define PDM_FIR1_COEFF13_DATA1_Msk 0x3FFF0000UL 343 344 345 #endif /* _CYIP_PDM_H_ */ 346 347 348 /* [] END OF FILE */ 349
