1 /***************************************************************************//** 2 * \file gpio_xmc7200_320_bga.h 3 * 4 * \brief 5 * XMC7200 device GPIO header for 320-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_XMC7200_320_BGA_H_ 28 #define _GPIO_XMC7200_320_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 320u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_EFUSE, 50 AMUXBUS_MAIN, 51 AMUXBUS_REGHC_ISENSE, 52 AMUXBUS_TEST, 53 AMUXBUS_TESTECT, 54 AMUXBUS_TESTSRSS, 55 }; 56 57 /* AMUX Splitter Controls */ 58 typedef enum 59 { 60 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TESTSRSS; Right = AMUXBUS_TEST */ 61 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTECT */ 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_EFUSE */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_REGHC_ISENSE */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (AUTOLVL) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 72 #define P0_1_PORT GPIO_PRT0 73 #define P0_1_PIN 1u 74 #define P0_1_NUM 1u 75 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 76 #define P0_2_PORT GPIO_PRT0 77 #define P0_2_PIN 2u 78 #define P0_2_NUM 2u 79 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 80 #define P0_3_PORT GPIO_PRT0 81 #define P0_3_PIN 3u 82 #define P0_3_NUM 3u 83 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 84 85 /* PORT 1 (AUTOLVL) */ 86 #define P1_0_PORT GPIO_PRT1 87 #define P1_0_PIN 0u 88 #define P1_0_NUM 0u 89 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 90 #define P1_1_PORT GPIO_PRT1 91 #define P1_1_PIN 1u 92 #define P1_1_NUM 1u 93 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 94 #define P1_2_PORT GPIO_PRT1 95 #define P1_2_PIN 2u 96 #define P1_2_NUM 2u 97 #define P1_2_AMUXSEGMENT AMUXBUS_MAIN 98 #define P1_3_PORT GPIO_PRT1 99 #define P1_3_PIN 3u 100 #define P1_3_NUM 3u 101 #define P1_3_AMUXSEGMENT AMUXBUS_MAIN 102 #define P1_4_PORT GPIO_PRT1 103 #define P1_4_PIN 4u 104 #define P1_4_NUM 4u 105 #define P1_4_AMUXSEGMENT AMUXBUS_MAIN 106 #define P1_5_PORT GPIO_PRT1 107 #define P1_5_PIN 5u 108 #define P1_5_NUM 5u 109 #define P1_5_AMUXSEGMENT AMUXBUS_MAIN 110 #define P1_6_PORT GPIO_PRT1 111 #define P1_6_PIN 6u 112 #define P1_6_NUM 6u 113 #define P1_6_AMUXSEGMENT AMUXBUS_MAIN 114 115 /* PORT 2 (AUTOLVL) */ 116 #define P2_0_PORT GPIO_PRT2 117 #define P2_0_PIN 0u 118 #define P2_0_NUM 0u 119 #define P2_0_AMUXSEGMENT AMUXBUS_MAIN 120 #define P2_1_PORT GPIO_PRT2 121 #define P2_1_PIN 1u 122 #define P2_1_NUM 1u 123 #define P2_1_AMUXSEGMENT AMUXBUS_MAIN 124 #define P2_2_PORT GPIO_PRT2 125 #define P2_2_PIN 2u 126 #define P2_2_NUM 2u 127 #define P2_2_AMUXSEGMENT AMUXBUS_MAIN 128 #define P2_3_PORT GPIO_PRT2 129 #define P2_3_PIN 3u 130 #define P2_3_NUM 3u 131 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 132 #define P2_4_PORT GPIO_PRT2 133 #define P2_4_PIN 4u 134 #define P2_4_NUM 4u 135 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 136 #define P2_5_PORT GPIO_PRT2 137 #define P2_5_PIN 5u 138 #define P2_5_NUM 5u 139 #define P2_5_AMUXSEGMENT AMUXBUS_MAIN 140 #define P2_6_PORT GPIO_PRT2 141 #define P2_6_PIN 6u 142 #define P2_6_NUM 6u 143 #define P2_6_AMUXSEGMENT AMUXBUS_MAIN 144 #define P2_7_PORT GPIO_PRT2 145 #define P2_7_PIN 7u 146 #define P2_7_NUM 7u 147 #define P2_7_AMUXSEGMENT AMUXBUS_MAIN 148 149 /* PORT 3 (AUTOLVL) */ 150 #define P3_0_PORT GPIO_PRT3 151 #define P3_0_PIN 0u 152 #define P3_0_NUM 0u 153 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 154 #define P3_1_PORT GPIO_PRT3 155 #define P3_1_PIN 1u 156 #define P3_1_NUM 1u 157 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 158 #define P3_2_PORT GPIO_PRT3 159 #define P3_2_PIN 2u 160 #define P3_2_NUM 2u 161 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 162 #define P3_3_PORT GPIO_PRT3 163 #define P3_3_PIN 3u 164 #define P3_3_NUM 3u 165 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 166 #define P3_4_PORT GPIO_PRT3 167 #define P3_4_PIN 4u 168 #define P3_4_NUM 4u 169 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 170 #define P3_5_PORT GPIO_PRT3 171 #define P3_5_PIN 5u 172 #define P3_5_NUM 5u 173 #define P3_5_AMUXSEGMENT AMUXBUS_MAIN 174 #define P3_6_PORT GPIO_PRT3 175 #define P3_6_PIN 6u 176 #define P3_6_NUM 6u 177 #define P3_6_AMUXSEGMENT AMUXBUS_MAIN 178 #define P3_7_PORT GPIO_PRT3 179 #define P3_7_PIN 7u 180 #define P3_7_NUM 7u 181 #define P3_7_AMUXSEGMENT AMUXBUS_MAIN 182 183 /* PORT 4 (AUTOLVL) */ 184 #define P4_0_PORT GPIO_PRT4 185 #define P4_0_PIN 0u 186 #define P4_0_NUM 0u 187 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 188 #define P4_1_PORT GPIO_PRT4 189 #define P4_1_PIN 1u 190 #define P4_1_NUM 1u 191 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 192 #define P4_2_PORT GPIO_PRT4 193 #define P4_2_PIN 2u 194 #define P4_2_NUM 2u 195 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 196 #define P4_3_PORT GPIO_PRT4 197 #define P4_3_PIN 3u 198 #define P4_3_NUM 3u 199 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 200 #define P4_4_PORT GPIO_PRT4 201 #define P4_4_PIN 4u 202 #define P4_4_NUM 4u 203 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 204 #define P4_5_PORT GPIO_PRT4 205 #define P4_5_PIN 5u 206 #define P4_5_NUM 5u 207 #define P4_5_AMUXSEGMENT AMUXBUS_MAIN 208 #define P4_6_PORT GPIO_PRT4 209 #define P4_6_PIN 6u 210 #define P4_6_NUM 6u 211 #define P4_6_AMUXSEGMENT AMUXBUS_MAIN 212 213 /* PORT 5 (AUTOLVL) */ 214 #define P5_0_PORT GPIO_PRT5 215 #define P5_0_PIN 0u 216 #define P5_0_NUM 0u 217 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 218 #define P5_1_PORT GPIO_PRT5 219 #define P5_1_PIN 1u 220 #define P5_1_NUM 1u 221 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 222 #define P5_2_PORT GPIO_PRT5 223 #define P5_2_PIN 2u 224 #define P5_2_NUM 2u 225 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 226 #define P5_3_PORT GPIO_PRT5 227 #define P5_3_PIN 3u 228 #define P5_3_NUM 3u 229 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 230 #define P5_4_PORT GPIO_PRT5 231 #define P5_4_PIN 4u 232 #define P5_4_NUM 4u 233 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 234 #define P5_5_PORT GPIO_PRT5 235 #define P5_5_PIN 5u 236 #define P5_5_NUM 5u 237 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 238 239 /* PORT 6 (AUTOLVL) */ 240 #define P6_0_PORT GPIO_PRT6 241 #define P6_0_PIN 0u 242 #define P6_0_NUM 0u 243 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 244 #define P6_1_PORT GPIO_PRT6 245 #define P6_1_PIN 1u 246 #define P6_1_NUM 1u 247 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 248 #define P6_2_PORT GPIO_PRT6 249 #define P6_2_PIN 2u 250 #define P6_2_NUM 2u 251 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 252 #define P6_3_PORT GPIO_PRT6 253 #define P6_3_PIN 3u 254 #define P6_3_NUM 3u 255 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 256 #define P6_4_PORT GPIO_PRT6 257 #define P6_4_PIN 4u 258 #define P6_4_NUM 4u 259 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 260 #define P6_5_PORT GPIO_PRT6 261 #define P6_5_PIN 5u 262 #define P6_5_NUM 5u 263 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 264 #define P6_6_PORT GPIO_PRT6 265 #define P6_6_PIN 6u 266 #define P6_6_NUM 6u 267 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 268 #define P6_7_PORT GPIO_PRT6 269 #define P6_7_PIN 7u 270 #define P6_7_NUM 7u 271 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 272 273 /* PORT 7 (AUTOLVL) */ 274 #define P7_0_PORT GPIO_PRT7 275 #define P7_0_PIN 0u 276 #define P7_0_NUM 0u 277 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 278 #define P7_1_PORT GPIO_PRT7 279 #define P7_1_PIN 1u 280 #define P7_1_NUM 1u 281 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 282 #define P7_2_PORT GPIO_PRT7 283 #define P7_2_PIN 2u 284 #define P7_2_NUM 2u 285 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 286 #define P7_3_PORT GPIO_PRT7 287 #define P7_3_PIN 3u 288 #define P7_3_NUM 3u 289 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 290 #define P7_4_PORT GPIO_PRT7 291 #define P7_4_PIN 4u 292 #define P7_4_NUM 4u 293 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 294 #define P7_5_PORT GPIO_PRT7 295 #define P7_5_PIN 5u 296 #define P7_5_NUM 5u 297 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 298 #define P7_6_PORT GPIO_PRT7 299 #define P7_6_PIN 6u 300 #define P7_6_NUM 6u 301 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 302 #define P7_7_PORT GPIO_PRT7 303 #define P7_7_PIN 7u 304 #define P7_7_NUM 7u 305 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 306 307 /* PORT 8 (AUTOLVL) */ 308 #define P8_0_PORT GPIO_PRT8 309 #define P8_0_PIN 0u 310 #define P8_0_NUM 0u 311 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 312 #define P8_1_PORT GPIO_PRT8 313 #define P8_1_PIN 1u 314 #define P8_1_NUM 1u 315 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 316 #define P8_2_PORT GPIO_PRT8 317 #define P8_2_PIN 2u 318 #define P8_2_NUM 2u 319 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 320 #define P8_3_PORT GPIO_PRT8 321 #define P8_3_PIN 3u 322 #define P8_3_NUM 3u 323 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 324 #define P8_4_PORT GPIO_PRT8 325 #define P8_4_PIN 4u 326 #define P8_4_NUM 4u 327 #define P8_4_AMUXSEGMENT AMUXBUS_MAIN 328 329 /* PORT 9 (AUTOLVL) */ 330 #define P9_0_PORT GPIO_PRT9 331 #define P9_0_PIN 0u 332 #define P9_0_NUM 0u 333 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 334 #define P9_1_PORT GPIO_PRT9 335 #define P9_1_PIN 1u 336 #define P9_1_NUM 1u 337 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 338 #define P9_2_PORT GPIO_PRT9 339 #define P9_2_PIN 2u 340 #define P9_2_NUM 2u 341 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 342 #define P9_3_PORT GPIO_PRT9 343 #define P9_3_PIN 3u 344 #define P9_3_NUM 3u 345 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 346 347 /* PORT 10 (AUTOLVL) */ 348 #define P10_0_PORT GPIO_PRT10 349 #define P10_0_PIN 0u 350 #define P10_0_NUM 0u 351 #define P10_0_AMUXSEGMENT AMUXBUS_MAIN 352 #define P10_1_PORT GPIO_PRT10 353 #define P10_1_PIN 1u 354 #define P10_1_NUM 1u 355 #define P10_1_AMUXSEGMENT AMUXBUS_MAIN 356 #define P10_2_PORT GPIO_PRT10 357 #define P10_2_PIN 2u 358 #define P10_2_NUM 2u 359 #define P10_2_AMUXSEGMENT AMUXBUS_MAIN 360 #define P10_3_PORT GPIO_PRT10 361 #define P10_3_PIN 3u 362 #define P10_3_NUM 3u 363 #define P10_3_AMUXSEGMENT AMUXBUS_MAIN 364 #define P10_4_PORT GPIO_PRT10 365 #define P10_4_PIN 4u 366 #define P10_4_NUM 4u 367 #define P10_4_AMUXSEGMENT AMUXBUS_MAIN 368 #define P10_5_PORT GPIO_PRT10 369 #define P10_5_PIN 5u 370 #define P10_5_NUM 5u 371 #define P10_5_AMUXSEGMENT AMUXBUS_MAIN 372 #define P10_6_PORT GPIO_PRT10 373 #define P10_6_PIN 6u 374 #define P10_6_NUM 6u 375 #define P10_6_AMUXSEGMENT AMUXBUS_MAIN 376 #define P10_7_PORT GPIO_PRT10 377 #define P10_7_PIN 7u 378 #define P10_7_NUM 7u 379 #define P10_7_AMUXSEGMENT AMUXBUS_MAIN 380 381 /* PORT 11 (AUTOLVL) */ 382 #define P11_0_PORT GPIO_PRT11 383 #define P11_0_PIN 0u 384 #define P11_0_NUM 0u 385 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 386 #define P11_1_PORT GPIO_PRT11 387 #define P11_1_PIN 1u 388 #define P11_1_NUM 1u 389 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 390 #define P11_2_PORT GPIO_PRT11 391 #define P11_2_PIN 2u 392 #define P11_2_NUM 2u 393 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 394 395 /* PORT 12 (AUTOLVL) */ 396 #define P12_0_PORT GPIO_PRT12 397 #define P12_0_PIN 0u 398 #define P12_0_NUM 0u 399 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 400 #define P12_1_PORT GPIO_PRT12 401 #define P12_1_PIN 1u 402 #define P12_1_NUM 1u 403 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 404 #define P12_2_PORT GPIO_PRT12 405 #define P12_2_PIN 2u 406 #define P12_2_NUM 2u 407 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 408 #define P12_3_PORT GPIO_PRT12 409 #define P12_3_PIN 3u 410 #define P12_3_NUM 3u 411 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 412 #define P12_4_PORT GPIO_PRT12 413 #define P12_4_PIN 4u 414 #define P12_4_NUM 4u 415 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 416 #define P12_5_PORT GPIO_PRT12 417 #define P12_5_PIN 5u 418 #define P12_5_NUM 5u 419 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 420 #define P12_6_PORT GPIO_PRT12 421 #define P12_6_PIN 6u 422 #define P12_6_NUM 6u 423 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 424 #define P12_7_PORT GPIO_PRT12 425 #define P12_7_PIN 7u 426 #define P12_7_NUM 7u 427 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 428 429 /* PORT 13 (AUTOLVL) */ 430 #define P13_0_PORT GPIO_PRT13 431 #define P13_0_PIN 0u 432 #define P13_0_NUM 0u 433 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 434 #define P13_1_PORT GPIO_PRT13 435 #define P13_1_PIN 1u 436 #define P13_1_NUM 1u 437 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 438 #define P13_2_PORT GPIO_PRT13 439 #define P13_2_PIN 2u 440 #define P13_2_NUM 2u 441 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 442 #define P13_3_PORT GPIO_PRT13 443 #define P13_3_PIN 3u 444 #define P13_3_NUM 3u 445 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 446 #define P13_4_PORT GPIO_PRT13 447 #define P13_4_PIN 4u 448 #define P13_4_NUM 4u 449 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 450 #define P13_5_PORT GPIO_PRT13 451 #define P13_5_PIN 5u 452 #define P13_5_NUM 5u 453 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 454 #define P13_6_PORT GPIO_PRT13 455 #define P13_6_PIN 6u 456 #define P13_6_NUM 6u 457 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 458 #define P13_7_PORT GPIO_PRT13 459 #define P13_7_PIN 7u 460 #define P13_7_NUM 7u 461 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 462 463 /* PORT 14 (AUTOLVL) */ 464 #define P14_0_PORT GPIO_PRT14 465 #define P14_0_PIN 0u 466 #define P14_0_NUM 0u 467 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 468 #define P14_1_PORT GPIO_PRT14 469 #define P14_1_PIN 1u 470 #define P14_1_NUM 1u 471 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 472 #define P14_2_PORT GPIO_PRT14 473 #define P14_2_PIN 2u 474 #define P14_2_NUM 2u 475 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 476 #define P14_3_PORT GPIO_PRT14 477 #define P14_3_PIN 3u 478 #define P14_3_NUM 3u 479 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 480 #define P14_4_PORT GPIO_PRT14 481 #define P14_4_PIN 4u 482 #define P14_4_NUM 4u 483 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 484 #define P14_5_PORT GPIO_PRT14 485 #define P14_5_PIN 5u 486 #define P14_5_NUM 5u 487 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 488 #define P14_6_PORT GPIO_PRT14 489 #define P14_6_PIN 6u 490 #define P14_6_NUM 6u 491 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 492 #define P14_7_PORT GPIO_PRT14 493 #define P14_7_PIN 7u 494 #define P14_7_NUM 7u 495 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 496 497 /* PORT 15 (AUTOLVL) */ 498 #define P15_0_PORT GPIO_PRT15 499 #define P15_0_PIN 0u 500 #define P15_0_NUM 0u 501 #define P15_0_AMUXSEGMENT AMUXBUS_MAIN 502 #define P15_1_PORT GPIO_PRT15 503 #define P15_1_PIN 1u 504 #define P15_1_NUM 1u 505 #define P15_1_AMUXSEGMENT AMUXBUS_MAIN 506 #define P15_2_PORT GPIO_PRT15 507 #define P15_2_PIN 2u 508 #define P15_2_NUM 2u 509 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 510 #define P15_3_PORT GPIO_PRT15 511 #define P15_3_PIN 3u 512 #define P15_3_NUM 3u 513 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 514 515 /* PORT 16 (AUTOLVL) */ 516 #define P16_0_PORT GPIO_PRT16 517 #define P16_0_PIN 0u 518 #define P16_0_NUM 0u 519 #define P16_0_AMUXSEGMENT AMUXBUS_MAIN 520 #define P16_1_PORT GPIO_PRT16 521 #define P16_1_PIN 1u 522 #define P16_1_NUM 1u 523 #define P16_1_AMUXSEGMENT AMUXBUS_MAIN 524 #define P16_2_PORT GPIO_PRT16 525 #define P16_2_PIN 2u 526 #define P16_2_NUM 2u 527 #define P16_2_AMUXSEGMENT AMUXBUS_MAIN 528 #define P16_3_PORT GPIO_PRT16 529 #define P16_3_PIN 3u 530 #define P16_3_NUM 3u 531 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 532 #define P16_4_PORT GPIO_PRT16 533 #define P16_4_PIN 4u 534 #define P16_4_NUM 4u 535 #define P16_4_AMUXSEGMENT AMUXBUS_MAIN 536 #define P16_5_PORT GPIO_PRT16 537 #define P16_5_PIN 5u 538 #define P16_5_NUM 5u 539 #define P16_5_AMUXSEGMENT AMUXBUS_MAIN 540 #define P16_6_PORT GPIO_PRT16 541 #define P16_6_PIN 6u 542 #define P16_6_NUM 6u 543 #define P16_6_AMUXSEGMENT AMUXBUS_MAIN 544 #define P16_7_PORT GPIO_PRT16 545 #define P16_7_PIN 7u 546 #define P16_7_NUM 7u 547 #define P16_7_AMUXSEGMENT AMUXBUS_MAIN 548 549 /* PORT 17 (AUTOLVL) */ 550 #define P17_0_PORT GPIO_PRT17 551 #define P17_0_PIN 0u 552 #define P17_0_NUM 0u 553 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 554 #define P17_1_PORT GPIO_PRT17 555 #define P17_1_PIN 1u 556 #define P17_1_NUM 1u 557 #define P17_1_AMUXSEGMENT AMUXBUS_MAIN 558 #define P17_2_PORT GPIO_PRT17 559 #define P17_2_PIN 2u 560 #define P17_2_NUM 2u 561 #define P17_2_AMUXSEGMENT AMUXBUS_MAIN 562 #define P17_3_PORT GPIO_PRT17 563 #define P17_3_PIN 3u 564 #define P17_3_NUM 3u 565 #define P17_3_AMUXSEGMENT AMUXBUS_MAIN 566 #define P17_4_PORT GPIO_PRT17 567 #define P17_4_PIN 4u 568 #define P17_4_NUM 4u 569 #define P17_4_AMUXSEGMENT AMUXBUS_MAIN 570 #define P17_5_PORT GPIO_PRT17 571 #define P17_5_PIN 5u 572 #define P17_5_NUM 5u 573 #define P17_5_AMUXSEGMENT AMUXBUS_MAIN 574 #define P17_6_PORT GPIO_PRT17 575 #define P17_6_PIN 6u 576 #define P17_6_NUM 6u 577 #define P17_6_AMUXSEGMENT AMUXBUS_MAIN 578 #define P17_7_PORT GPIO_PRT17 579 #define P17_7_PIN 7u 580 #define P17_7_NUM 7u 581 #define P17_7_AMUXSEGMENT AMUXBUS_MAIN 582 583 /* PORT 18 (AUTOLVL) */ 584 #define P18_0_PORT GPIO_PRT18 585 #define P18_0_PIN 0u 586 #define P18_0_NUM 0u 587 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 588 #define P18_1_PORT GPIO_PRT18 589 #define P18_1_PIN 1u 590 #define P18_1_NUM 1u 591 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 592 #define P18_2_PORT GPIO_PRT18 593 #define P18_2_PIN 2u 594 #define P18_2_NUM 2u 595 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 596 #define P18_3_PORT GPIO_PRT18 597 #define P18_3_PIN 3u 598 #define P18_3_NUM 3u 599 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 600 #define P18_4_PORT GPIO_PRT18 601 #define P18_4_PIN 4u 602 #define P18_4_NUM 4u 603 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 604 #define P18_5_PORT GPIO_PRT18 605 #define P18_5_PIN 5u 606 #define P18_5_NUM 5u 607 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 608 #define P18_6_PORT GPIO_PRT18 609 #define P18_6_PIN 6u 610 #define P18_6_NUM 6u 611 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 612 #define P18_7_PORT GPIO_PRT18 613 #define P18_7_PIN 7u 614 #define P18_7_NUM 7u 615 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 616 617 /* PORT 19 (AUTOLVL) */ 618 #define P19_0_PORT GPIO_PRT19 619 #define P19_0_PIN 0u 620 #define P19_0_NUM 0u 621 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 622 #define P19_1_PORT GPIO_PRT19 623 #define P19_1_PIN 1u 624 #define P19_1_NUM 1u 625 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 626 #define P19_2_PORT GPIO_PRT19 627 #define P19_2_PIN 2u 628 #define P19_2_NUM 2u 629 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 630 #define P19_3_PORT GPIO_PRT19 631 #define P19_3_PIN 3u 632 #define P19_3_NUM 3u 633 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 634 #define P19_4_PORT GPIO_PRT19 635 #define P19_4_PIN 4u 636 #define P19_4_NUM 4u 637 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 638 639 /* PORT 20 (AUTOLVL) */ 640 #define P20_0_PORT GPIO_PRT20 641 #define P20_0_PIN 0u 642 #define P20_0_NUM 0u 643 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 644 #define P20_1_PORT GPIO_PRT20 645 #define P20_1_PIN 1u 646 #define P20_1_NUM 1u 647 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 648 #define P20_2_PORT GPIO_PRT20 649 #define P20_2_PIN 2u 650 #define P20_2_NUM 2u 651 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 652 #define P20_3_PORT GPIO_PRT20 653 #define P20_3_PIN 3u 654 #define P20_3_NUM 3u 655 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 656 #define P20_4_PORT GPIO_PRT20 657 #define P20_4_PIN 4u 658 #define P20_4_NUM 4u 659 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 660 #define P20_5_PORT GPIO_PRT20 661 #define P20_5_PIN 5u 662 #define P20_5_NUM 5u 663 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 664 #define P20_6_PORT GPIO_PRT20 665 #define P20_6_PIN 6u 666 #define P20_6_NUM 6u 667 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 668 #define P20_7_PORT GPIO_PRT20 669 #define P20_7_PIN 7u 670 #define P20_7_NUM 7u 671 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 672 673 /* PORT 21 (AUTOLVL) */ 674 #define P21_0_PORT GPIO_PRT21 675 #define P21_0_PIN 0u 676 #define P21_0_NUM 0u 677 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 678 #define P21_1_PORT GPIO_PRT21 679 #define P21_1_PIN 1u 680 #define P21_1_NUM 1u 681 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 682 #define P21_2_PORT GPIO_PRT21 683 #define P21_2_PIN 2u 684 #define P21_2_NUM 2u 685 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 686 #define P21_3_PORT GPIO_PRT21 687 #define P21_3_PIN 3u 688 #define P21_3_NUM 3u 689 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 690 #define P21_4_PORT GPIO_PRT21 691 #define P21_4_PIN 4u 692 #define P21_4_NUM 4u 693 #define P21_4_AMUXSEGMENT AMUXBUS_MAIN 694 #define P21_5_PORT GPIO_PRT21 695 #define P21_5_PIN 5u 696 #define P21_5_NUM 5u 697 #define P21_5_AMUXSEGMENT AMUXBUS_MAIN 698 #define P21_6_PORT GPIO_PRT21 699 #define P21_6_PIN 6u 700 #define P21_6_NUM 6u 701 #define P21_6_AMUXSEGMENT AMUXBUS_MAIN 702 #define P21_7_PORT GPIO_PRT21 703 #define P21_7_PIN 7u 704 #define P21_7_NUM 7u 705 #define P21_7_AMUXSEGMENT AMUXBUS_MAIN 706 707 /* PORT 22 (AUTOLVL) */ 708 #define P22_1_PORT GPIO_PRT22 709 #define P22_1_PIN 1u 710 #define P22_1_NUM 1u 711 #define P22_1_AMUXSEGMENT AMUXBUS_MAIN 712 #define P22_2_PORT GPIO_PRT22 713 #define P22_2_PIN 2u 714 #define P22_2_NUM 2u 715 #define P22_2_AMUXSEGMENT AMUXBUS_MAIN 716 #define P22_3_PORT GPIO_PRT22 717 #define P22_3_PIN 3u 718 #define P22_3_NUM 3u 719 #define P22_3_AMUXSEGMENT AMUXBUS_MAIN 720 #define P22_4_PORT GPIO_PRT22 721 #define P22_4_PIN 4u 722 #define P22_4_NUM 4u 723 #define P22_4_AMUXSEGMENT AMUXBUS_MAIN 724 #define P22_5_PORT GPIO_PRT22 725 #define P22_5_PIN 5u 726 #define P22_5_NUM 5u 727 #define P22_5_AMUXSEGMENT AMUXBUS_MAIN 728 #define P22_6_PORT GPIO_PRT22 729 #define P22_6_PIN 6u 730 #define P22_6_NUM 6u 731 #define P22_6_AMUXSEGMENT AMUXBUS_MAIN 732 #define P22_7_PORT GPIO_PRT22 733 #define P22_7_PIN 7u 734 #define P22_7_NUM 7u 735 #define P22_7_AMUXSEGMENT AMUXBUS_MAIN 736 737 /* PORT 23 (AUTOLVL) */ 738 #define P23_0_PORT GPIO_PRT23 739 #define P23_0_PIN 0u 740 #define P23_0_NUM 0u 741 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 742 #define P23_1_PORT GPIO_PRT23 743 #define P23_1_PIN 1u 744 #define P23_1_NUM 1u 745 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 746 #define P23_2_PORT GPIO_PRT23 747 #define P23_2_PIN 2u 748 #define P23_2_NUM 2u 749 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 750 #define P23_3_PORT GPIO_PRT23 751 #define P23_3_PIN 3u 752 #define P23_3_NUM 3u 753 #define P23_3_AMUXSEGMENT AMUXBUS_TEST 754 #define P23_4_PORT GPIO_PRT23 755 #define P23_4_PIN 4u 756 #define P23_4_NUM 4u 757 #define P23_4_AMUXSEGMENT AMUXBUS_TEST 758 #define P23_5_PORT GPIO_PRT23 759 #define P23_5_PIN 5u 760 #define P23_5_NUM 5u 761 #define P23_5_AMUXSEGMENT AMUXBUS_MAIN 762 #define P23_6_PORT GPIO_PRT23 763 #define P23_6_PIN 6u 764 #define P23_6_NUM 6u 765 #define P23_6_AMUXSEGMENT AMUXBUS_MAIN 766 #define P23_7_PORT GPIO_PRT23 767 #define P23_7_PIN 7u 768 #define P23_7_NUM 7u 769 #define P23_7_AMUXSEGMENT AMUXBUS_MAIN 770 771 /* PORT 24 (HSIO, AUTOLVL) */ 772 #define P24_0_PORT GPIO_PRT24 773 #define P24_0_PIN 0u 774 #define P24_0_NUM 0u 775 #define P24_0_AMUXSEGMENT AMUXBUS_MAIN 776 #define P24_1_PORT GPIO_PRT24 777 #define P24_1_PIN 1u 778 #define P24_1_NUM 1u 779 #define P24_1_AMUXSEGMENT AMUXBUS_MAIN 780 #define P24_2_PORT GPIO_PRT24 781 #define P24_2_PIN 2u 782 #define P24_2_NUM 2u 783 #define P24_2_AMUXSEGMENT AMUXBUS_MAIN 784 #define P24_3_PORT GPIO_PRT24 785 #define P24_3_PIN 3u 786 #define P24_3_NUM 3u 787 #define P24_3_AMUXSEGMENT AMUXBUS_MAIN 788 #define P24_4_PORT GPIO_PRT24 789 #define P24_4_PIN 4u 790 #define P24_4_NUM 4u 791 #define P24_4_AMUXSEGMENT AMUXBUS_MAIN 792 793 /* PORT 25 (HSIO, AUTOLVL) */ 794 #define P25_0_PORT GPIO_PRT25 795 #define P25_0_PIN 0u 796 #define P25_0_NUM 0u 797 #define P25_0_AMUXSEGMENT AMUXBUS_MAIN 798 #define P25_1_PORT GPIO_PRT25 799 #define P25_1_PIN 1u 800 #define P25_1_NUM 1u 801 #define P25_1_AMUXSEGMENT AMUXBUS_MAIN 802 #define P25_2_PORT GPIO_PRT25 803 #define P25_2_PIN 2u 804 #define P25_2_NUM 2u 805 #define P25_2_AMUXSEGMENT AMUXBUS_MAIN 806 #define P25_3_PORT GPIO_PRT25 807 #define P25_3_PIN 3u 808 #define P25_3_NUM 3u 809 #define P25_3_AMUXSEGMENT AMUXBUS_MAIN 810 #define P25_4_PORT GPIO_PRT25 811 #define P25_4_PIN 4u 812 #define P25_4_NUM 4u 813 #define P25_4_AMUXSEGMENT AMUXBUS_MAIN 814 #define P25_5_PORT GPIO_PRT25 815 #define P25_5_PIN 5u 816 #define P25_5_NUM 5u 817 #define P25_5_AMUXSEGMENT AMUXBUS_MAIN 818 #define P25_6_PORT GPIO_PRT25 819 #define P25_6_PIN 6u 820 #define P25_6_NUM 6u 821 #define P25_6_AMUXSEGMENT AMUXBUS_MAIN 822 #define P25_7_PORT GPIO_PRT25 823 #define P25_7_PIN 7u 824 #define P25_7_NUM 7u 825 #define P25_7_AMUXSEGMENT AMUXBUS_MAIN 826 827 /* PORT 26 (HSIO, AUTOLVL) */ 828 #define P26_0_PORT GPIO_PRT26 829 #define P26_0_PIN 0u 830 #define P26_0_NUM 0u 831 #define P26_0_AMUXSEGMENT AMUXBUS_MAIN 832 #define P26_1_PORT GPIO_PRT26 833 #define P26_1_PIN 1u 834 #define P26_1_NUM 1u 835 #define P26_1_AMUXSEGMENT AMUXBUS_MAIN 836 #define P26_2_PORT GPIO_PRT26 837 #define P26_2_PIN 2u 838 #define P26_2_NUM 2u 839 #define P26_2_AMUXSEGMENT AMUXBUS_MAIN 840 #define P26_3_PORT GPIO_PRT26 841 #define P26_3_PIN 3u 842 #define P26_3_NUM 3u 843 #define P26_3_AMUXSEGMENT AMUXBUS_MAIN 844 #define P26_4_PORT GPIO_PRT26 845 #define P26_4_PIN 4u 846 #define P26_4_NUM 4u 847 #define P26_4_AMUXSEGMENT AMUXBUS_MAIN 848 #define P26_5_PORT GPIO_PRT26 849 #define P26_5_PIN 5u 850 #define P26_5_NUM 5u 851 #define P26_5_AMUXSEGMENT AMUXBUS_MAIN 852 #define P26_6_PORT GPIO_PRT26 853 #define P26_6_PIN 6u 854 #define P26_6_NUM 6u 855 #define P26_6_AMUXSEGMENT AMUXBUS_MAIN 856 #define P26_7_PORT GPIO_PRT26 857 #define P26_7_PIN 7u 858 #define P26_7_NUM 7u 859 #define P26_7_AMUXSEGMENT AMUXBUS_MAIN 860 861 /* PORT 27 (HSIO, AUTOLVL) */ 862 #define P27_0_PORT GPIO_PRT27 863 #define P27_0_PIN 0u 864 #define P27_0_NUM 0u 865 #define P27_0_AMUXSEGMENT AMUXBUS_MAIN 866 #define P27_1_PORT GPIO_PRT27 867 #define P27_1_PIN 1u 868 #define P27_1_NUM 1u 869 #define P27_1_AMUXSEGMENT AMUXBUS_MAIN 870 #define P27_2_PORT GPIO_PRT27 871 #define P27_2_PIN 2u 872 #define P27_2_NUM 2u 873 #define P27_2_AMUXSEGMENT AMUXBUS_MAIN 874 #define P27_3_PORT GPIO_PRT27 875 #define P27_3_PIN 3u 876 #define P27_3_NUM 3u 877 #define P27_3_AMUXSEGMENT AMUXBUS_MAIN 878 #define P27_4_PORT GPIO_PRT27 879 #define P27_4_PIN 4u 880 #define P27_4_NUM 4u 881 #define P27_4_AMUXSEGMENT AMUXBUS_MAIN 882 #define P27_5_PORT GPIO_PRT27 883 #define P27_5_PIN 5u 884 #define P27_5_NUM 5u 885 #define P27_5_AMUXSEGMENT AMUXBUS_MAIN 886 #define P27_6_PORT GPIO_PRT27 887 #define P27_6_PIN 6u 888 #define P27_6_NUM 6u 889 #define P27_6_AMUXSEGMENT AMUXBUS_MAIN 890 #define P27_7_PORT GPIO_PRT27 891 #define P27_7_PIN 7u 892 #define P27_7_NUM 7u 893 #define P27_7_AMUXSEGMENT AMUXBUS_MAIN 894 895 /* PORT 28 (AUTOLVL) */ 896 #define P28_0_PORT GPIO_PRT28 897 #define P28_0_PIN 0u 898 #define P28_0_NUM 0u 899 #define P28_0_AMUXSEGMENT AMUXBUS_MAIN 900 #define P28_1_PORT GPIO_PRT28 901 #define P28_1_PIN 1u 902 #define P28_1_NUM 1u 903 #define P28_1_AMUXSEGMENT AMUXBUS_MAIN 904 #define P28_2_PORT GPIO_PRT28 905 #define P28_2_PIN 2u 906 #define P28_2_NUM 2u 907 #define P28_2_AMUXSEGMENT AMUXBUS_MAIN 908 #define P28_3_PORT GPIO_PRT28 909 #define P28_3_PIN 3u 910 #define P28_3_NUM 3u 911 #define P28_3_AMUXSEGMENT AMUXBUS_MAIN 912 #define P28_4_PORT GPIO_PRT28 913 #define P28_4_PIN 4u 914 #define P28_4_NUM 4u 915 #define P28_4_AMUXSEGMENT AMUXBUS_MAIN 916 #define P28_5_PORT GPIO_PRT28 917 #define P28_5_PIN 5u 918 #define P28_5_NUM 5u 919 #define P28_5_AMUXSEGMENT AMUXBUS_MAIN 920 #define P28_6_PORT GPIO_PRT28 921 #define P28_6_PIN 6u 922 #define P28_6_NUM 6u 923 #define P28_6_AMUXSEGMENT AMUXBUS_MAIN 924 #define P28_7_PORT GPIO_PRT28 925 #define P28_7_PIN 7u 926 #define P28_7_NUM 7u 927 #define P28_7_AMUXSEGMENT AMUXBUS_MAIN 928 929 /* PORT 29 (AUTOLVL) */ 930 #define P29_0_PORT GPIO_PRT29 931 #define P29_0_PIN 0u 932 #define P29_0_NUM 0u 933 #define P29_0_AMUXSEGMENT AMUXBUS_MAIN 934 #define P29_1_PORT GPIO_PRT29 935 #define P29_1_PIN 1u 936 #define P29_1_NUM 1u 937 #define P29_1_AMUXSEGMENT AMUXBUS_MAIN 938 #define P29_2_PORT GPIO_PRT29 939 #define P29_2_PIN 2u 940 #define P29_2_NUM 2u 941 #define P29_2_AMUXSEGMENT AMUXBUS_MAIN 942 #define P29_3_PORT GPIO_PRT29 943 #define P29_3_PIN 3u 944 #define P29_3_NUM 3u 945 #define P29_3_AMUXSEGMENT AMUXBUS_MAIN 946 #define P29_4_PORT GPIO_PRT29 947 #define P29_4_PIN 4u 948 #define P29_4_NUM 4u 949 #define P29_4_AMUXSEGMENT AMUXBUS_MAIN 950 #define P29_5_PORT GPIO_PRT29 951 #define P29_5_PIN 5u 952 #define P29_5_NUM 5u 953 #define P29_5_AMUXSEGMENT AMUXBUS_MAIN 954 #define P29_6_PORT GPIO_PRT29 955 #define P29_6_PIN 6u 956 #define P29_6_NUM 6u 957 #define P29_6_AMUXSEGMENT AMUXBUS_MAIN 958 #define P29_7_PORT GPIO_PRT29 959 #define P29_7_PIN 7u 960 #define P29_7_NUM 7u 961 #define P29_7_AMUXSEGMENT AMUXBUS_MAIN 962 963 /* PORT 30 (AUTOLVL) */ 964 #define P30_0_PORT GPIO_PRT30 965 #define P30_0_PIN 0u 966 #define P30_0_NUM 0u 967 #define P30_0_AMUXSEGMENT AMUXBUS_MAIN 968 #define P30_1_PORT GPIO_PRT30 969 #define P30_1_PIN 1u 970 #define P30_1_NUM 1u 971 #define P30_1_AMUXSEGMENT AMUXBUS_MAIN 972 #define P30_2_PORT GPIO_PRT30 973 #define P30_2_PIN 2u 974 #define P30_2_NUM 2u 975 #define P30_2_AMUXSEGMENT AMUXBUS_MAIN 976 #define P30_3_PORT GPIO_PRT30 977 #define P30_3_PIN 3u 978 #define P30_3_NUM 3u 979 #define P30_3_AMUXSEGMENT AMUXBUS_MAIN 980 981 /* PORT 31 (AUTOLVL) */ 982 #define P31_0_PORT GPIO_PRT31 983 #define P31_0_PIN 0u 984 #define P31_0_NUM 0u 985 #define P31_0_AMUXSEGMENT AMUXBUS_MAIN 986 #define P31_1_PORT GPIO_PRT31 987 #define P31_1_PIN 1u 988 #define P31_1_NUM 1u 989 #define P31_1_AMUXSEGMENT AMUXBUS_MAIN 990 #define P31_2_PORT GPIO_PRT31 991 #define P31_2_PIN 2u 992 #define P31_2_NUM 2u 993 #define P31_2_AMUXSEGMENT AMUXBUS_MAIN 994 995 /* PORT 32 (AUTOLVL) */ 996 #define P32_0_PORT GPIO_PRT32 997 #define P32_0_PIN 0u 998 #define P32_0_NUM 0u 999 #define P32_0_AMUXSEGMENT AMUXBUS_MAIN 1000 #define P32_1_PORT GPIO_PRT32 1001 #define P32_1_PIN 1u 1002 #define P32_1_NUM 1u 1003 #define P32_1_AMUXSEGMENT AMUXBUS_MAIN 1004 #define P32_2_PORT GPIO_PRT32 1005 #define P32_2_PIN 2u 1006 #define P32_2_NUM 2u 1007 #define P32_2_AMUXSEGMENT AMUXBUS_MAIN 1008 #define P32_3_PORT GPIO_PRT32 1009 #define P32_3_PIN 3u 1010 #define P32_3_NUM 3u 1011 #define P32_3_AMUXSEGMENT AMUXBUS_MAIN 1012 #define P32_4_PORT GPIO_PRT32 1013 #define P32_4_PIN 4u 1014 #define P32_4_NUM 4u 1015 #define P32_4_AMUXSEGMENT AMUXBUS_MAIN 1016 #define P32_5_PORT GPIO_PRT32 1017 #define P32_5_PIN 5u 1018 #define P32_5_NUM 5u 1019 #define P32_5_AMUXSEGMENT AMUXBUS_MAIN 1020 #define P32_6_PORT GPIO_PRT32 1021 #define P32_6_PIN 6u 1022 #define P32_6_NUM 6u 1023 #define P32_6_AMUXSEGMENT AMUXBUS_MAIN 1024 #define P32_7_PORT GPIO_PRT32 1025 #define P32_7_PIN 7u 1026 #define P32_7_NUM 7u 1027 #define P32_7_AMUXSEGMENT AMUXBUS_MAIN 1028 1029 /* PORT 33 (HSIO, AUTOLVL) */ 1030 #define P33_0_PORT GPIO_PRT33 1031 #define P33_0_PIN 0u 1032 #define P33_0_NUM 0u 1033 #define P33_0_AMUXSEGMENT AMUXBUS_MAIN 1034 #define P33_1_PORT GPIO_PRT33 1035 #define P33_1_PIN 1u 1036 #define P33_1_NUM 1u 1037 #define P33_1_AMUXSEGMENT AMUXBUS_MAIN 1038 #define P33_2_PORT GPIO_PRT33 1039 #define P33_2_PIN 2u 1040 #define P33_2_NUM 2u 1041 #define P33_2_AMUXSEGMENT AMUXBUS_MAIN 1042 #define P33_3_PORT GPIO_PRT33 1043 #define P33_3_PIN 3u 1044 #define P33_3_NUM 3u 1045 #define P33_3_AMUXSEGMENT AMUXBUS_MAIN 1046 #define P33_4_PORT GPIO_PRT33 1047 #define P33_4_PIN 4u 1048 #define P33_4_NUM 4u 1049 #define P33_4_AMUXSEGMENT AMUXBUS_MAIN 1050 #define P33_5_PORT GPIO_PRT33 1051 #define P33_5_PIN 5u 1052 #define P33_5_NUM 5u 1053 #define P33_5_AMUXSEGMENT AMUXBUS_MAIN 1054 #define P33_6_PORT GPIO_PRT33 1055 #define P33_6_PIN 6u 1056 #define P33_6_NUM 6u 1057 #define P33_6_AMUXSEGMENT AMUXBUS_MAIN 1058 #define P33_7_PORT GPIO_PRT33 1059 #define P33_7_PIN 7u 1060 #define P33_7_NUM 7u 1061 #define P33_7_AMUXSEGMENT AMUXBUS_MAIN 1062 1063 /* PORT 34 (HSIO, AUTOLVL) */ 1064 #define P34_0_PORT GPIO_PRT34 1065 #define P34_0_PIN 0u 1066 #define P34_0_NUM 0u 1067 #define P34_0_AMUXSEGMENT AMUXBUS_MAIN 1068 #define P34_1_PORT GPIO_PRT34 1069 #define P34_1_PIN 1u 1070 #define P34_1_NUM 1u 1071 #define P34_1_AMUXSEGMENT AMUXBUS_MAIN 1072 #define P34_2_PORT GPIO_PRT34 1073 #define P34_2_PIN 2u 1074 #define P34_2_NUM 2u 1075 #define P34_2_AMUXSEGMENT AMUXBUS_MAIN 1076 #define P34_3_PORT GPIO_PRT34 1077 #define P34_3_PIN 3u 1078 #define P34_3_NUM 3u 1079 #define P34_3_AMUXSEGMENT AMUXBUS_MAIN 1080 #define P34_4_PORT GPIO_PRT34 1081 #define P34_4_PIN 4u 1082 #define P34_4_NUM 4u 1083 #define P34_4_AMUXSEGMENT AMUXBUS_MAIN 1084 #define P34_5_PORT GPIO_PRT34 1085 #define P34_5_PIN 5u 1086 #define P34_5_NUM 5u 1087 #define P34_5_AMUXSEGMENT AMUXBUS_MAIN 1088 #define P34_6_PORT GPIO_PRT34 1089 #define P34_6_PIN 6u 1090 #define P34_6_NUM 6u 1091 #define P34_6_AMUXSEGMENT AMUXBUS_MAIN 1092 #define P34_7_PORT GPIO_PRT34 1093 #define P34_7_PIN 7u 1094 #define P34_7_NUM 7u 1095 #define P34_7_AMUXSEGMENT AMUXBUS_MAIN 1096 1097 /* Analog Connections */ 1098 #define PASS0_I_TEMP_KELVIN_PORT 21u 1099 #define PASS0_I_TEMP_KELVIN_PIN 2u 1100 #define PASS0_SARMUX_MOTOR0_PORT 11u 1101 #define PASS0_SARMUX_MOTOR0_PIN 0u 1102 #define PASS0_SARMUX_MOTOR1_PORT 11u 1103 #define PASS0_SARMUX_MOTOR1_PIN 1u 1104 #define PASS0_SARMUX_MOTOR2_PORT 11u 1105 #define PASS0_SARMUX_MOTOR2_PIN 2u 1106 #define PASS0_SARMUX_PADS0_PORT 6u 1107 #define PASS0_SARMUX_PADS0_PIN 0u 1108 #define PASS0_SARMUX_PADS1_PORT 6u 1109 #define PASS0_SARMUX_PADS1_PIN 1u 1110 #define PASS0_SARMUX_PADS10_PORT 32u 1111 #define PASS0_SARMUX_PADS10_PIN 2u 1112 #define PASS0_SARMUX_PADS11_PORT 32u 1113 #define PASS0_SARMUX_PADS11_PIN 3u 1114 #define PASS0_SARMUX_PADS12_PORT 32u 1115 #define PASS0_SARMUX_PADS12_PIN 4u 1116 #define PASS0_SARMUX_PADS13_PORT 32u 1117 #define PASS0_SARMUX_PADS13_PIN 5u 1118 #define PASS0_SARMUX_PADS14_PORT 32u 1119 #define PASS0_SARMUX_PADS14_PIN 6u 1120 #define PASS0_SARMUX_PADS15_PORT 32u 1121 #define PASS0_SARMUX_PADS15_PIN 7u 1122 #define PASS0_SARMUX_PADS16_PORT 7u 1123 #define PASS0_SARMUX_PADS16_PIN 0u 1124 #define PASS0_SARMUX_PADS17_PORT 7u 1125 #define PASS0_SARMUX_PADS17_PIN 1u 1126 #define PASS0_SARMUX_PADS18_PORT 7u 1127 #define PASS0_SARMUX_PADS18_PIN 2u 1128 #define PASS0_SARMUX_PADS19_PORT 7u 1129 #define PASS0_SARMUX_PADS19_PIN 3u 1130 #define PASS0_SARMUX_PADS2_PORT 6u 1131 #define PASS0_SARMUX_PADS2_PIN 2u 1132 #define PASS0_SARMUX_PADS20_PORT 7u 1133 #define PASS0_SARMUX_PADS20_PIN 4u 1134 #define PASS0_SARMUX_PADS21_PORT 7u 1135 #define PASS0_SARMUX_PADS21_PIN 5u 1136 #define PASS0_SARMUX_PADS22_PORT 7u 1137 #define PASS0_SARMUX_PADS22_PIN 6u 1138 #define PASS0_SARMUX_PADS23_PORT 7u 1139 #define PASS0_SARMUX_PADS23_PIN 7u 1140 #define PASS0_SARMUX_PADS24_PORT 8u 1141 #define PASS0_SARMUX_PADS24_PIN 1u 1142 #define PASS0_SARMUX_PADS25_PORT 8u 1143 #define PASS0_SARMUX_PADS25_PIN 2u 1144 #define PASS0_SARMUX_PADS26_PORT 8u 1145 #define PASS0_SARMUX_PADS26_PIN 3u 1146 #define PASS0_SARMUX_PADS27_PORT 8u 1147 #define PASS0_SARMUX_PADS27_PIN 4u 1148 #define PASS0_SARMUX_PADS28_PORT 9u 1149 #define PASS0_SARMUX_PADS28_PIN 0u 1150 #define PASS0_SARMUX_PADS29_PORT 9u 1151 #define PASS0_SARMUX_PADS29_PIN 1u 1152 #define PASS0_SARMUX_PADS3_PORT 6u 1153 #define PASS0_SARMUX_PADS3_PIN 3u 1154 #define PASS0_SARMUX_PADS30_PORT 9u 1155 #define PASS0_SARMUX_PADS30_PIN 2u 1156 #define PASS0_SARMUX_PADS31_PORT 9u 1157 #define PASS0_SARMUX_PADS31_PIN 3u 1158 #define PASS0_SARMUX_PADS32_PORT 10u 1159 #define PASS0_SARMUX_PADS32_PIN 4u 1160 #define PASS0_SARMUX_PADS33_PORT 10u 1161 #define PASS0_SARMUX_PADS33_PIN 5u 1162 #define PASS0_SARMUX_PADS34_PORT 10u 1163 #define PASS0_SARMUX_PADS34_PIN 6u 1164 #define PASS0_SARMUX_PADS35_PORT 10u 1165 #define PASS0_SARMUX_PADS35_PIN 7u 1166 #define PASS0_SARMUX_PADS36_PORT 12u 1167 #define PASS0_SARMUX_PADS36_PIN 0u 1168 #define PASS0_SARMUX_PADS37_PORT 12u 1169 #define PASS0_SARMUX_PADS37_PIN 1u 1170 #define PASS0_SARMUX_PADS38_PORT 12u 1171 #define PASS0_SARMUX_PADS38_PIN 2u 1172 #define PASS0_SARMUX_PADS39_PORT 12u 1173 #define PASS0_SARMUX_PADS39_PIN 3u 1174 #define PASS0_SARMUX_PADS4_PORT 6u 1175 #define PASS0_SARMUX_PADS4_PIN 4u 1176 #define PASS0_SARMUX_PADS40_PORT 12u 1177 #define PASS0_SARMUX_PADS40_PIN 4u 1178 #define PASS0_SARMUX_PADS41_PORT 12u 1179 #define PASS0_SARMUX_PADS41_PIN 5u 1180 #define PASS0_SARMUX_PADS42_PORT 12u 1181 #define PASS0_SARMUX_PADS42_PIN 6u 1182 #define PASS0_SARMUX_PADS43_PORT 12u 1183 #define PASS0_SARMUX_PADS43_PIN 7u 1184 #define PASS0_SARMUX_PADS44_PORT 13u 1185 #define PASS0_SARMUX_PADS44_PIN 0u 1186 #define PASS0_SARMUX_PADS45_PORT 13u 1187 #define PASS0_SARMUX_PADS45_PIN 1u 1188 #define PASS0_SARMUX_PADS46_PORT 13u 1189 #define PASS0_SARMUX_PADS46_PIN 2u 1190 #define PASS0_SARMUX_PADS47_PORT 13u 1191 #define PASS0_SARMUX_PADS47_PIN 3u 1192 #define PASS0_SARMUX_PADS48_PORT 13u 1193 #define PASS0_SARMUX_PADS48_PIN 4u 1194 #define PASS0_SARMUX_PADS49_PORT 13u 1195 #define PASS0_SARMUX_PADS49_PIN 5u 1196 #define PASS0_SARMUX_PADS5_PORT 6u 1197 #define PASS0_SARMUX_PADS5_PIN 5u 1198 #define PASS0_SARMUX_PADS50_PORT 13u 1199 #define PASS0_SARMUX_PADS50_PIN 6u 1200 #define PASS0_SARMUX_PADS51_PORT 13u 1201 #define PASS0_SARMUX_PADS51_PIN 7u 1202 #define PASS0_SARMUX_PADS52_PORT 14u 1203 #define PASS0_SARMUX_PADS52_PIN 0u 1204 #define PASS0_SARMUX_PADS53_PORT 14u 1205 #define PASS0_SARMUX_PADS53_PIN 1u 1206 #define PASS0_SARMUX_PADS54_PORT 14u 1207 #define PASS0_SARMUX_PADS54_PIN 2u 1208 #define PASS0_SARMUX_PADS55_PORT 14u 1209 #define PASS0_SARMUX_PADS55_PIN 3u 1210 #define PASS0_SARMUX_PADS56_PORT 14u 1211 #define PASS0_SARMUX_PADS56_PIN 4u 1212 #define PASS0_SARMUX_PADS57_PORT 14u 1213 #define PASS0_SARMUX_PADS57_PIN 5u 1214 #define PASS0_SARMUX_PADS58_PORT 14u 1215 #define PASS0_SARMUX_PADS58_PIN 6u 1216 #define PASS0_SARMUX_PADS59_PORT 14u 1217 #define PASS0_SARMUX_PADS59_PIN 7u 1218 #define PASS0_SARMUX_PADS6_PORT 6u 1219 #define PASS0_SARMUX_PADS6_PIN 6u 1220 #define PASS0_SARMUX_PADS60_PORT 15u 1221 #define PASS0_SARMUX_PADS60_PIN 0u 1222 #define PASS0_SARMUX_PADS61_PORT 15u 1223 #define PASS0_SARMUX_PADS61_PIN 1u 1224 #define PASS0_SARMUX_PADS62_PORT 15u 1225 #define PASS0_SARMUX_PADS62_PIN 2u 1226 #define PASS0_SARMUX_PADS63_PORT 15u 1227 #define PASS0_SARMUX_PADS63_PIN 3u 1228 #define PASS0_SARMUX_PADS64_PORT 16u 1229 #define PASS0_SARMUX_PADS64_PIN 0u 1230 #define PASS0_SARMUX_PADS65_PORT 16u 1231 #define PASS0_SARMUX_PADS65_PIN 1u 1232 #define PASS0_SARMUX_PADS66_PORT 16u 1233 #define PASS0_SARMUX_PADS66_PIN 2u 1234 #define PASS0_SARMUX_PADS67_PORT 16u 1235 #define PASS0_SARMUX_PADS67_PIN 3u 1236 #define PASS0_SARMUX_PADS68_PORT 16u 1237 #define PASS0_SARMUX_PADS68_PIN 4u 1238 #define PASS0_SARMUX_PADS69_PORT 16u 1239 #define PASS0_SARMUX_PADS69_PIN 5u 1240 #define PASS0_SARMUX_PADS7_PORT 6u 1241 #define PASS0_SARMUX_PADS7_PIN 7u 1242 #define PASS0_SARMUX_PADS70_PORT 16u 1243 #define PASS0_SARMUX_PADS70_PIN 6u 1244 #define PASS0_SARMUX_PADS71_PORT 16u 1245 #define PASS0_SARMUX_PADS71_PIN 7u 1246 #define PASS0_SARMUX_PADS72_PORT 17u 1247 #define PASS0_SARMUX_PADS72_PIN 0u 1248 #define PASS0_SARMUX_PADS73_PORT 17u 1249 #define PASS0_SARMUX_PADS73_PIN 1u 1250 #define PASS0_SARMUX_PADS74_PORT 17u 1251 #define PASS0_SARMUX_PADS74_PIN 2u 1252 #define PASS0_SARMUX_PADS75_PORT 17u 1253 #define PASS0_SARMUX_PADS75_PIN 3u 1254 #define PASS0_SARMUX_PADS76_PORT 17u 1255 #define PASS0_SARMUX_PADS76_PIN 4u 1256 #define PASS0_SARMUX_PADS77_PORT 17u 1257 #define PASS0_SARMUX_PADS77_PIN 5u 1258 #define PASS0_SARMUX_PADS78_PORT 17u 1259 #define PASS0_SARMUX_PADS78_PIN 6u 1260 #define PASS0_SARMUX_PADS79_PORT 17u 1261 #define PASS0_SARMUX_PADS79_PIN 7u 1262 #define PASS0_SARMUX_PADS8_PORT 32u 1263 #define PASS0_SARMUX_PADS8_PIN 0u 1264 #define PASS0_SARMUX_PADS80_PORT 18u 1265 #define PASS0_SARMUX_PADS80_PIN 0u 1266 #define PASS0_SARMUX_PADS81_PORT 18u 1267 #define PASS0_SARMUX_PADS81_PIN 1u 1268 #define PASS0_SARMUX_PADS82_PORT 18u 1269 #define PASS0_SARMUX_PADS82_PIN 2u 1270 #define PASS0_SARMUX_PADS83_PORT 18u 1271 #define PASS0_SARMUX_PADS83_PIN 3u 1272 #define PASS0_SARMUX_PADS84_PORT 18u 1273 #define PASS0_SARMUX_PADS84_PIN 4u 1274 #define PASS0_SARMUX_PADS85_PORT 18u 1275 #define PASS0_SARMUX_PADS85_PIN 5u 1276 #define PASS0_SARMUX_PADS86_PORT 18u 1277 #define PASS0_SARMUX_PADS86_PIN 6u 1278 #define PASS0_SARMUX_PADS87_PORT 18u 1279 #define PASS0_SARMUX_PADS87_PIN 7u 1280 #define PASS0_SARMUX_PADS88_PORT 19u 1281 #define PASS0_SARMUX_PADS88_PIN 0u 1282 #define PASS0_SARMUX_PADS89_PORT 19u 1283 #define PASS0_SARMUX_PADS89_PIN 1u 1284 #define PASS0_SARMUX_PADS9_PORT 32u 1285 #define PASS0_SARMUX_PADS9_PIN 1u 1286 #define PASS0_SARMUX_PADS90_PORT 19u 1287 #define PASS0_SARMUX_PADS90_PIN 2u 1288 #define PASS0_SARMUX_PADS91_PORT 19u 1289 #define PASS0_SARMUX_PADS91_PIN 3u 1290 #define PASS0_SARMUX_PADS92_PORT 19u 1291 #define PASS0_SARMUX_PADS92_PIN 4u 1292 #define PASS0_SARMUX_PADS93_PORT 20u 1293 #define PASS0_SARMUX_PADS93_PIN 0u 1294 #define PASS0_SARMUX_PADS94_PORT 20u 1295 #define PASS0_SARMUX_PADS94_PIN 1u 1296 #define PASS0_SARMUX_PADS95_PORT 20u 1297 #define PASS0_SARMUX_PADS95_PIN 2u 1298 #define PASS0_VB_TEMP_KELVIN_PORT 10u 1299 #define PASS0_VB_TEMP_KELVIN_PIN 4u 1300 #define PASS0_VE_TEMP_KELVIN_PORT 23u 1301 #define PASS0_VE_TEMP_KELVIN_PIN 4u 1302 #define SRSS_ADFT_PIN0_PORT 23u 1303 #define SRSS_ADFT_PIN0_PIN 4u 1304 #define SRSS_ADFT_PIN1_PORT 23u 1305 #define SRSS_ADFT_PIN1_PIN 3u 1306 #define SRSS_ADFT_POR_PAD_HV_PORT 21u 1307 #define SRSS_ADFT_POR_PAD_HV_PIN 4u 1308 #define SRSS_ECO_IN_PORT 21u 1309 #define SRSS_ECO_IN_PIN 2u 1310 #define SRSS_ECO_OUT_PORT 21u 1311 #define SRSS_ECO_OUT_PIN 3u 1312 #define SRSS_REGHC_ISENSE_INM_PORT 22u 1313 #define SRSS_REGHC_ISENSE_INM_PIN 2u 1314 #define SRSS_REGHC_ISENSE_INP_PORT 22u 1315 #define SRSS_REGHC_ISENSE_INP_PIN 1u 1316 #define SRSS_REGHC_RST_VOUT_PORT 22u 1317 #define SRSS_REGHC_RST_VOUT_PIN 3u 1318 #define SRSS_VEXT_REF_REG_PORT 21u 1319 #define SRSS_VEXT_REF_REG_PIN 3u 1320 #define SRSS_WCO_IN_PORT 21u 1321 #define SRSS_WCO_IN_PIN 0u 1322 #define SRSS_WCO_OUT_PORT 21u 1323 #define SRSS_WCO_OUT_PIN 1u 1324 1325 /* HSIOM Connections */ 1326 typedef enum 1327 { 1328 /* Generic HSIOM connections */ 1329 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 1330 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1331 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1332 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1333 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 1334 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 1335 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1336 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1337 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 1338 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 1339 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 1340 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 1341 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 1342 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 1343 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 1344 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 1345 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 1346 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 1347 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 1348 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 1349 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 1350 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 1351 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 1352 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 1353 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 1354 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 1355 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 1356 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 1357 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 1358 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 1359 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 1360 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 1361 1362 /* P0.0 */ 1363 P0_0_GPIO = 0, /* GPIO controls 'out' */ 1364 P0_0_AMUXA = 4, /* Analog mux bus A */ 1365 P0_0_AMUXB = 5, /* Analog mux bus B */ 1366 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1367 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1368 P0_0_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:1 */ 1369 P0_0_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 1370 P0_0_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:1 */ 1371 P0_0_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:1 */ 1372 P0_0_SCB0_UART_RX = 17, /* Digital Active - scb[0].uart_rx:0 */ 1373 P0_0_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:2 */ 1374 P0_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:0 */ 1375 P0_0_TCPWM0_LINE512 = 22, /* Digital Active - tcpwm[0].line[512] */ 1376 P0_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 1377 1378 /* P0.1 */ 1379 P0_1_GPIO = 0, /* GPIO controls 'out' */ 1380 P0_1_AMUXA = 4, /* Analog mux bus A */ 1381 P0_1_AMUXB = 5, /* Analog mux bus B */ 1382 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1383 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1384 P0_1_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:1 */ 1385 P0_1_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 1386 P0_1_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:1 */ 1387 P0_1_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:1 */ 1388 P0_1_SCB0_UART_TX = 17, /* Digital Active - scb[0].uart_tx:0 */ 1389 P0_1_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:2 */ 1390 P0_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:0 */ 1391 P0_1_TCPWM0_LINE_COMPL512 = 22, /* Digital Active - tcpwm[0].line_compl[512] */ 1392 P0_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 1393 1394 /* P0.2 */ 1395 P0_2_GPIO = 0, /* GPIO controls 'out' */ 1396 P0_2_AMUXA = 4, /* Analog mux bus A */ 1397 P0_2_AMUXB = 5, /* Analog mux bus B */ 1398 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1399 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1400 P0_2_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:1 */ 1401 P0_2_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 1402 P0_2_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:1 */ 1403 P0_2_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:1 */ 1404 P0_2_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 1405 P0_2_SCB0_UART_RTS = 17, /* Digital Active - scb[0].uart_rts:0 */ 1406 P0_2_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:2 */ 1407 P0_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:0 */ 1408 P0_2_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 1409 P0_2_TCPWM0_TR_ONE_CNT_IN1536 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1536] */ 1410 P0_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 1411 1412 /* P0.3 */ 1413 P0_3_GPIO = 0, /* GPIO controls 'out' */ 1414 P0_3_AMUXA = 4, /* Analog mux bus A */ 1415 P0_3_AMUXB = 5, /* Analog mux bus B */ 1416 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1417 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1418 P0_3_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:1 */ 1419 P0_3_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 1420 P0_3_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:1 */ 1421 P0_3_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:1 */ 1422 P0_3_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 1423 P0_3_SCB0_UART_CTS = 17, /* Digital Active - scb[0].uart_cts:0 */ 1424 P0_3_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:2 */ 1425 P0_3_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 1426 P0_3_TCPWM0_TR_ONE_CNT_IN1537 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1537] */ 1427 P0_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 1428 1429 /* P1.0 */ 1430 P1_0_GPIO = 0, /* GPIO controls 'out' */ 1431 P1_0_AMUXA = 4, /* Analog mux bus A */ 1432 P1_0_AMUXB = 5, /* Analog mux bus B */ 1433 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1434 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1435 P1_0_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:1 */ 1436 P1_0_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:1 */ 1437 P1_0_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:1 */ 1438 P1_0_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:1 */ 1439 P1_0_SCB0_I2C_SCL = 14, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 1440 P1_0_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:0 */ 1441 P1_0_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:2 */ 1442 P1_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 1443 1444 /* P1.1 */ 1445 P1_1_GPIO = 0, /* GPIO controls 'out' */ 1446 P1_1_AMUXA = 4, /* Analog mux bus A */ 1447 P1_1_AMUXB = 5, /* Analog mux bus B */ 1448 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1449 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1450 P1_1_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:1 */ 1451 P1_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 1452 P1_1_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:1 */ 1453 P1_1_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:1 */ 1454 P1_1_SCB0_I2C_SDA = 14, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 1455 P1_1_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:0 */ 1456 P1_1_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:2 */ 1457 P1_1_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 1458 1459 /* P1.2 */ 1460 P1_2_GPIO = 0, /* GPIO controls 'out' */ 1461 P1_2_AMUXA = 4, /* Analog mux bus A */ 1462 P1_2_AMUXB = 5, /* Analog mux bus B */ 1463 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1464 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1465 P1_2_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:1 */ 1466 P1_2_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 1467 P1_2_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:1 */ 1468 P1_2_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:1 */ 1469 P1_2_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:0 */ 1470 P1_2_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:2 */ 1471 P1_2_PERI_TR_IO_INPUT0 = 26, /* Digital Active - peri.tr_io_input[0]:0 */ 1472 P1_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1473 1474 /* P1.3 */ 1475 P1_3_GPIO = 0, /* GPIO controls 'out' */ 1476 P1_3_AMUXA = 4, /* Analog mux bus A */ 1477 P1_3_AMUXB = 5, /* Analog mux bus B */ 1478 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1479 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1480 P1_3_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:1 */ 1481 P1_3_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 1482 P1_3_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:1 */ 1483 P1_3_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:1 */ 1484 P1_3_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:0 */ 1485 P1_3_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:2 */ 1486 P1_3_PERI_TR_IO_INPUT1 = 26, /* Digital Active - peri.tr_io_input[1]:0 */ 1487 P1_3_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1488 1489 /* P1.4 */ 1490 P1_4_GPIO = 0, /* GPIO controls 'out' */ 1491 P1_4_AMUXA = 4, /* Analog mux bus A */ 1492 P1_4_AMUXB = 5, /* Analog mux bus B */ 1493 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1494 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1495 P1_4_TCPWM1_LINE71 = 8, /* Digital Active - tcpwm[1].line[71]:0 */ 1496 P1_4_TCPWM1_LINE_COMPL70 = 9, /* Digital Active - tcpwm[1].line_compl[70]:0 */ 1497 P1_4_TCPWM1_TR_ONE_CNT_IN213 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[213]:0 */ 1498 P1_4_TCPWM1_TR_ONE_CNT_IN211 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[211]:0 */ 1499 P1_4_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:1 */ 1500 P1_4_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:1 */ 1501 P1_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:2 */ 1502 1503 /* P1.5 */ 1504 P1_5_GPIO = 0, /* GPIO controls 'out' */ 1505 P1_5_AMUXA = 4, /* Analog mux bus A */ 1506 P1_5_AMUXB = 5, /* Analog mux bus B */ 1507 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1508 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1509 P1_5_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:1 */ 1510 P1_5_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:1 */ 1511 P1_5_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:1 */ 1512 P1_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:2 */ 1513 1514 /* P1.6 */ 1515 P1_6_GPIO = 0, /* GPIO controls 'out' */ 1516 P1_6_AMUXA = 4, /* Analog mux bus A */ 1517 P1_6_AMUXB = 5, /* Analog mux bus B */ 1518 P1_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1519 P1_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1520 P1_6_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:1 */ 1521 P1_6_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:1 */ 1522 P1_6_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:1 */ 1523 P1_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:2 */ 1524 1525 /* P2.0 */ 1526 P2_0_GPIO = 0, /* GPIO controls 'out' */ 1527 P2_0_AMUXA = 4, /* Analog mux bus A */ 1528 P2_0_AMUXB = 5, /* Analog mux bus B */ 1529 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1530 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1531 P2_0_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:1 */ 1532 P2_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 1533 P2_0_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:1 */ 1534 P2_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:1 */ 1535 P2_0_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:0 */ 1536 P2_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:0 */ 1537 P2_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:0 */ 1538 P2_0_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:0 */ 1539 P2_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1540 P2_0_PERI_TR_IO_INPUT2 = 26, /* Digital Active - peri.tr_io_input[2]:0 */ 1541 P2_0_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1542 P2_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1543 1544 /* P2.1 */ 1545 P2_1_GPIO = 0, /* GPIO controls 'out' */ 1546 P2_1_AMUXA = 4, /* Analog mux bus A */ 1547 P2_1_AMUXB = 5, /* Analog mux bus B */ 1548 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1549 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1550 P2_1_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:1 */ 1551 P2_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1552 P2_1_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:1 */ 1553 P2_1_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:1 */ 1554 P2_1_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:0 */ 1555 P2_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:0 */ 1556 P2_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:0 */ 1557 P2_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:0 */ 1558 P2_1_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:0 */ 1559 P2_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1560 P2_1_PERI_TR_IO_INPUT3 = 26, /* Digital Active - peri.tr_io_input[3]:0 */ 1561 P2_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1562 1563 /* P2.2 */ 1564 P2_2_GPIO = 0, /* GPIO controls 'out' */ 1565 P2_2_AMUXA = 4, /* Analog mux bus A */ 1566 P2_2_AMUXB = 5, /* Analog mux bus B */ 1567 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1568 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1569 P2_2_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:1 */ 1570 P2_2_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1571 P2_2_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:1 */ 1572 P2_2_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:1 */ 1573 P2_2_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:0 */ 1574 P2_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:0 */ 1575 P2_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:0 */ 1576 P2_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:0 */ 1577 P2_2_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:0 */ 1578 P2_2_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er:0 */ 1579 P2_2_PERI_TR_IO_INPUT4 = 26, /* Digital Active - peri.tr_io_input[4]:0 */ 1580 P2_2_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1581 1582 /* P2.3 */ 1583 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1584 P2_3_AMUXA = 4, /* Analog mux bus A */ 1585 P2_3_AMUXB = 5, /* Analog mux bus B */ 1586 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1587 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1588 P2_3_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:1 */ 1589 P2_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1590 P2_3_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:1 */ 1591 P2_3_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:1 */ 1592 P2_3_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:0 */ 1593 P2_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:0 */ 1594 P2_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:0 */ 1595 P2_3_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:1 */ 1596 P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:0 */ 1597 P2_3_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:2 */ 1598 P2_3_PERI_TR_IO_INPUT5 = 26, /* Digital Active - peri.tr_io_input[5]:0 */ 1599 1600 /* P2.4 */ 1601 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1602 P2_4_AMUXA = 4, /* Analog mux bus A */ 1603 P2_4_AMUXB = 5, /* Analog mux bus B */ 1604 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1605 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1606 P2_4_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:1 */ 1607 P2_4_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1608 P2_4_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:1 */ 1609 P2_4_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:1 */ 1610 P2_4_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:0 */ 1611 P2_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:0 */ 1612 P2_4_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:1 */ 1613 P2_4_PERI_TR_IO_INPUT6 = 26, /* Digital Active - peri.tr_io_input[6]:0 */ 1614 1615 /* P2.5 */ 1616 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1617 P2_5_AMUXA = 4, /* Analog mux bus A */ 1618 P2_5_AMUXB = 5, /* Analog mux bus B */ 1619 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1620 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1621 P2_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:1 */ 1622 P2_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1623 P2_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:1 */ 1624 P2_5_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:1 */ 1625 P2_5_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:0 */ 1626 P2_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:0 */ 1627 P2_5_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:1 */ 1628 P2_5_PERI_TR_IO_INPUT7 = 26, /* Digital Active - peri.tr_io_input[7]:0 */ 1629 1630 /* P2.6 */ 1631 P2_6_GPIO = 0, /* GPIO controls 'out' */ 1632 P2_6_AMUXA = 4, /* Analog mux bus A */ 1633 P2_6_AMUXB = 5, /* Analog mux bus B */ 1634 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1635 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1636 P2_6_TCPWM1_LINE72 = 8, /* Digital Active - tcpwm[1].line[72]:0 */ 1637 P2_6_TCPWM1_LINE_COMPL71 = 9, /* Digital Active - tcpwm[1].line_compl[71]:0 */ 1638 P2_6_TCPWM1_TR_ONE_CNT_IN216 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[216]:0 */ 1639 P2_6_TCPWM1_TR_ONE_CNT_IN214 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[214]:0 */ 1640 P2_6_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:1 */ 1641 P2_6_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:1 */ 1642 1643 /* P2.7 */ 1644 P2_7_GPIO = 0, /* GPIO controls 'out' */ 1645 P2_7_AMUXA = 4, /* Analog mux bus A */ 1646 P2_7_AMUXB = 5, /* Analog mux bus B */ 1647 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1648 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1649 P2_7_TCPWM1_LINE73 = 8, /* Digital Active - tcpwm[1].line[73]:0 */ 1650 P2_7_TCPWM1_LINE_COMPL72 = 9, /* Digital Active - tcpwm[1].line_compl[72]:0 */ 1651 P2_7_TCPWM1_TR_ONE_CNT_IN219 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[219]:0 */ 1652 P2_7_TCPWM1_TR_ONE_CNT_IN217 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[217]:0 */ 1653 P2_7_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:1 */ 1654 P2_7_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:1 */ 1655 1656 /* P3.0 */ 1657 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1658 P3_0_AMUXA = 4, /* Analog mux bus A */ 1659 P3_0_AMUXB = 5, /* Analog mux bus B */ 1660 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1661 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1662 P3_0_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:1 */ 1663 P3_0_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1664 P3_0_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:1 */ 1665 P3_0_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:1 */ 1666 P3_0_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:0 */ 1667 P3_0_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:0 */ 1668 P3_0_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:0 */ 1669 P3_0_CANFD0_TTCAN_TX3 = 21, /* Digital Active - canfd[0].ttcan_tx[3]:0 */ 1670 P3_0_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:0 */ 1671 P3_0_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 1672 1673 /* P3.1 */ 1674 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1675 P3_1_AMUXA = 4, /* Analog mux bus A */ 1676 P3_1_AMUXB = 5, /* Analog mux bus B */ 1677 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1678 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1679 P3_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:1 */ 1680 P3_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1681 P3_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:1 */ 1682 P3_1_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:1 */ 1683 P3_1_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:0 */ 1684 P3_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:0 */ 1685 P3_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:0 */ 1686 P3_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:0 */ 1687 P3_1_CANFD0_TTCAN_RX3 = 21, /* Digital Active - canfd[0].ttcan_rx[3]:0 */ 1688 P3_1_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:0 */ 1689 P3_1_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 1690 1691 /* P3.2 */ 1692 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1693 P3_2_AMUXA = 4, /* Analog mux bus A */ 1694 P3_2_AMUXB = 5, /* Analog mux bus B */ 1695 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1696 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1697 P3_2_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:1 */ 1698 P3_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1699 P3_2_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:1 */ 1700 P3_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:1 */ 1701 P3_2_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:0 */ 1702 P3_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:0 */ 1703 P3_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:0 */ 1704 P3_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:0 */ 1705 1706 /* P3.3 */ 1707 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1708 P3_3_AMUXA = 4, /* Analog mux bus A */ 1709 P3_3_AMUXB = 5, /* Analog mux bus B */ 1710 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1711 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1712 P3_3_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:1 */ 1713 P3_3_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:1 */ 1714 P3_3_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:1 */ 1715 P3_3_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:1 */ 1716 P3_3_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:0 */ 1717 P3_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:0 */ 1718 P3_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:0 */ 1719 1720 /* P3.4 */ 1721 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1722 P3_4_AMUXA = 4, /* Analog mux bus A */ 1723 P3_4_AMUXB = 5, /* Analog mux bus B */ 1724 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1725 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1726 P3_4_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:1 */ 1727 P3_4_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:1 */ 1728 P3_4_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:1 */ 1729 P3_4_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:1 */ 1730 P3_4_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:0 */ 1731 P3_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:0 */ 1732 P3_4_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:2 */ 1733 1734 /* P3.5 */ 1735 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1736 P3_5_AMUXA = 4, /* Analog mux bus A */ 1737 P3_5_AMUXB = 5, /* Analog mux bus B */ 1738 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1739 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1740 P3_5_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:1 */ 1741 P3_5_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:1 */ 1742 P3_5_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:1 */ 1743 P3_5_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:1 */ 1744 P3_5_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:0 */ 1745 P3_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:0 */ 1746 P3_5_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:2 */ 1747 1748 /* P3.6 */ 1749 P3_6_GPIO = 0, /* GPIO controls 'out' */ 1750 P3_6_AMUXA = 4, /* Analog mux bus A */ 1751 P3_6_AMUXB = 5, /* Analog mux bus B */ 1752 P3_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1753 P3_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1754 P3_6_TCPWM1_LINE74 = 8, /* Digital Active - tcpwm[1].line[74]:0 */ 1755 P3_6_TCPWM1_LINE_COMPL73 = 9, /* Digital Active - tcpwm[1].line_compl[73]:0 */ 1756 P3_6_TCPWM1_TR_ONE_CNT_IN222 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[222]:0 */ 1757 P3_6_TCPWM1_TR_ONE_CNT_IN220 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[220]:0 */ 1758 P3_6_SCB8_SPI_SELECT2 = 19, /* Digital Active - scb[8].spi_select2:0 */ 1759 P3_6_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:1 */ 1760 P3_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:2 */ 1761 1762 /* P3.7 */ 1763 P3_7_GPIO = 0, /* GPIO controls 'out' */ 1764 P3_7_AMUXA = 4, /* Analog mux bus A */ 1765 P3_7_AMUXB = 5, /* Analog mux bus B */ 1766 P3_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1767 P3_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1768 P3_7_TCPWM1_LINE75 = 8, /* Digital Active - tcpwm[1].line[75]:0 */ 1769 P3_7_TCPWM1_LINE_COMPL74 = 9, /* Digital Active - tcpwm[1].line_compl[74]:0 */ 1770 P3_7_TCPWM1_TR_ONE_CNT_IN225 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[225]:0 */ 1771 P3_7_TCPWM1_TR_ONE_CNT_IN223 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[223]:0 */ 1772 P3_7_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:1 */ 1773 P3_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:2 */ 1774 1775 /* P4.0 */ 1776 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1777 P4_0_AMUXA = 4, /* Analog mux bus A */ 1778 P4_0_AMUXB = 5, /* Analog mux bus B */ 1779 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1780 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1781 P4_0_TCPWM1_LINE4 = 8, /* Digital Active - tcpwm[1].line[4]:0 */ 1782 P4_0_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:1 */ 1783 P4_0_TCPWM1_TR_ONE_CNT_IN12 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[12]:0 */ 1784 P4_0_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:1 */ 1785 P4_0_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1786 P4_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:0 */ 1787 P4_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:0 */ 1788 P4_0_LIN0_LIN_RX1 = 20, /* Digital Active - lin[0].lin_rx[1]:1 */ 1789 P4_0_PERI_TR_IO_INPUT10 = 26, /* Digital Active - peri.tr_io_input[10]:0 */ 1790 1791 /* P4.1 */ 1792 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1793 P4_1_AMUXA = 4, /* Analog mux bus A */ 1794 P4_1_AMUXB = 5, /* Analog mux bus B */ 1795 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1796 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1797 P4_1_TCPWM1_LINE5 = 8, /* Digital Active - tcpwm[1].line[5]:0 */ 1798 P4_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1799 P4_1_TCPWM1_TR_ONE_CNT_IN15 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[15]:0 */ 1800 P4_1_TCPWM1_TR_ONE_CNT_IN13 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[13]:0 */ 1801 P4_1_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1802 P4_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:0 */ 1803 P4_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:0 */ 1804 P4_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:0 */ 1805 P4_1_LIN0_LIN_TX1 = 20, /* Digital Active - lin[0].lin_tx[1]:1 */ 1806 P4_1_PERI_TR_IO_INPUT11 = 26, /* Digital Active - peri.tr_io_input[11]:0 */ 1807 1808 /* P4.2 */ 1809 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1810 P4_2_AMUXA = 4, /* Analog mux bus A */ 1811 P4_2_AMUXB = 5, /* Analog mux bus B */ 1812 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1813 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1814 P4_2_TCPWM1_LINE6 = 8, /* Digital Active - tcpwm[1].line[6]:0 */ 1815 P4_2_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1816 P4_2_TCPWM1_TR_ONE_CNT_IN18 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[18]:0 */ 1817 P4_2_TCPWM1_TR_ONE_CNT_IN16 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[16]:0 */ 1818 P4_2_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 1819 P4_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:0 */ 1820 P4_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:0 */ 1821 P4_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:0 */ 1822 P4_2_LIN0_LIN_EN1 = 20, /* Digital Active - lin[0].lin_en[1]:1 */ 1823 P4_2_PERI_TR_IO_INPUT12 = 26, /* Digital Active - peri.tr_io_input[12]:0 */ 1824 1825 /* P4.3 */ 1826 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1827 P4_3_AMUXA = 4, /* Analog mux bus A */ 1828 P4_3_AMUXB = 5, /* Analog mux bus B */ 1829 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1830 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1831 P4_3_TCPWM1_LINE7 = 8, /* Digital Active - tcpwm[1].line[7]:0 */ 1832 P4_3_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1833 P4_3_TCPWM1_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[21]:0 */ 1834 P4_3_TCPWM1_TR_ONE_CNT_IN19 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[19]:0 */ 1835 P4_3_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 1836 P4_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:0 */ 1837 P4_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:0 */ 1838 P4_3_CANFD0_TTCAN_TX1 = 21, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1839 P4_3_PERI_TR_IO_INPUT13 = 26, /* Digital Active - peri.tr_io_input[13]:0 */ 1840 1841 /* P4.4 */ 1842 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1843 P4_4_AMUXA = 4, /* Analog mux bus A */ 1844 P4_4_AMUXB = 5, /* Analog mux bus B */ 1845 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1846 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1847 P4_4_TCPWM1_LINE8 = 8, /* Digital Active - tcpwm[1].line[8]:0 */ 1848 P4_4_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1849 P4_4_TCPWM1_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[24]:0 */ 1850 P4_4_TCPWM1_TR_ONE_CNT_IN22 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[22]:0 */ 1851 P4_4_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:1 */ 1852 P4_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:0 */ 1853 P4_4_CANFD0_TTCAN_RX1 = 21, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1854 1855 /* P4.5 */ 1856 P4_5_GPIO = 0, /* GPIO controls 'out' */ 1857 P4_5_AMUXA = 4, /* Analog mux bus A */ 1858 P4_5_AMUXB = 5, /* Analog mux bus B */ 1859 P4_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1860 P4_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1861 P4_5_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:1 */ 1862 P4_5_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:1 */ 1863 P4_5_PERI_TR_IO_INPUT32 = 26, /* Digital Active - peri.tr_io_input[32]:0 */ 1864 1865 /* P4.6 */ 1866 P4_6_GPIO = 0, /* GPIO controls 'out' */ 1867 P4_6_AMUXA = 4, /* Analog mux bus A */ 1868 P4_6_AMUXB = 5, /* Analog mux bus B */ 1869 P4_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1870 P4_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1871 P4_6_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:1 */ 1872 P4_6_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:1 */ 1873 P4_6_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:1 */ 1874 P4_6_PERI_TR_IO_INPUT33 = 26, /* Digital Active - peri.tr_io_input[33]:0 */ 1875 1876 /* P5.0 */ 1877 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1878 P5_0_AMUXA = 4, /* Analog mux bus A */ 1879 P5_0_AMUXB = 5, /* Analog mux bus B */ 1880 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1881 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1882 P5_0_TCPWM1_LINE9 = 8, /* Digital Active - tcpwm[1].line[9]:0 */ 1883 P5_0_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1884 P5_0_TCPWM1_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[27]:0 */ 1885 P5_0_TCPWM1_TR_ONE_CNT_IN25 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[25]:0 */ 1886 P5_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:0 */ 1887 P5_0_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:1 */ 1888 P5_0_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:0 */ 1889 P5_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:0 */ 1890 P5_0_TCPWM0_LINE256 = 22, /* Digital Active - tcpwm[0].line[256] */ 1891 P5_0_PERI_TR_IO_INPUT38 = 26, /* Digital Active - peri.tr_io_input[38]:0 */ 1892 1893 /* P5.1 */ 1894 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1895 P5_1_AMUXA = 4, /* Analog mux bus A */ 1896 P5_1_AMUXB = 5, /* Analog mux bus B */ 1897 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1898 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1899 P5_1_TCPWM1_LINE10 = 8, /* Digital Active - tcpwm[1].line[10]:0 */ 1900 P5_1_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1901 P5_1_TCPWM1_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[30]:0 */ 1902 P5_1_TCPWM1_TR_ONE_CNT_IN28 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[28]:0 */ 1903 P5_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:0 */ 1904 P5_1_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:1 */ 1905 P5_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:0 */ 1906 P5_1_TCPWM0_LINE_COMPL256 = 22, /* Digital Active - tcpwm[0].line_compl[256] */ 1907 P5_1_PERI_TR_IO_INPUT39 = 26, /* Digital Active - peri.tr_io_input[39]:0 */ 1908 1909 /* P5.2 */ 1910 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1911 P5_2_AMUXA = 4, /* Analog mux bus A */ 1912 P5_2_AMUXB = 5, /* Analog mux bus B */ 1913 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1914 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1915 P5_2_TCPWM1_LINE11 = 8, /* Digital Active - tcpwm[1].line[11]:0 */ 1916 P5_2_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1917 P5_2_TCPWM1_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[33]:0 */ 1918 P5_2_TCPWM1_TR_ONE_CNT_IN31 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[31]:0 */ 1919 P5_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:0 */ 1920 P5_2_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:2 */ 1921 P5_2_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:0 */ 1922 P5_2_TCPWM0_TR_ONE_CNT_IN768 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[768] */ 1923 1924 /* P5.3 */ 1925 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1926 P5_3_AMUXA = 4, /* Analog mux bus A */ 1927 P5_3_AMUXB = 5, /* Analog mux bus B */ 1928 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1929 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1930 P5_3_TCPWM1_LINE12 = 8, /* Digital Active - tcpwm[1].line[12]:0 */ 1931 P5_3_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1932 P5_3_TCPWM1_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[36]:0 */ 1933 P5_3_TCPWM1_TR_ONE_CNT_IN34 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[34]:0 */ 1934 P5_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:0 */ 1935 P5_3_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:2 */ 1936 P5_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:0 */ 1937 P5_3_TCPWM0_TR_ONE_CNT_IN769 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[769] */ 1938 1939 /* P5.4 */ 1940 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1941 P5_4_AMUXA = 4, /* Analog mux bus A */ 1942 P5_4_AMUXB = 5, /* Analog mux bus B */ 1943 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1944 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1945 P5_4_TCPWM1_LINE13 = 8, /* Digital Active - tcpwm[1].line[13]:0 */ 1946 P5_4_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1947 P5_4_TCPWM1_TR_ONE_CNT_IN39 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[39]:0 */ 1948 P5_4_TCPWM1_TR_ONE_CNT_IN37 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[37]:0 */ 1949 P5_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:0 */ 1950 P5_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:0 */ 1951 P5_4_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:1 */ 1952 1953 /* P5.5 */ 1954 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1955 P5_5_AMUXA = 4, /* Analog mux bus A */ 1956 P5_5_AMUXB = 5, /* Analog mux bus B */ 1957 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1958 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1959 P5_5_TCPWM1_LINE14 = 8, /* Digital Active - tcpwm[1].line[14]:0 */ 1960 P5_5_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1961 P5_5_TCPWM1_TR_ONE_CNT_IN42 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[42]:0 */ 1962 P5_5_TCPWM1_TR_ONE_CNT_IN40 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[40]:0 */ 1963 P5_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:0 */ 1964 P5_5_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:0 */ 1965 P5_5_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:1 */ 1966 1967 /* P6.0 */ 1968 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1969 P6_0_AMUXA = 4, /* Analog mux bus A */ 1970 P6_0_AMUXB = 5, /* Analog mux bus B */ 1971 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1972 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1973 P6_0_TCPWM1_LINE256 = 8, /* Digital Active - tcpwm[1].line[256]:0 */ 1974 P6_0_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1975 P6_0_TCPWM1_TR_ONE_CNT_IN768 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[768]:0 */ 1976 P6_0_TCPWM1_TR_ONE_CNT_IN43 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[43]:0 */ 1977 P6_0_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:0 */ 1978 P6_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:0 */ 1979 P6_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:0 */ 1980 P6_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:0 */ 1981 P6_0_TCPWM0_LINE0 = 22, /* Digital Active - tcpwm[0].line[0] */ 1982 P6_0_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:1 */ 1983 1984 /* P6.1 */ 1985 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1986 P6_1_AMUXA = 4, /* Analog mux bus A */ 1987 P6_1_AMUXB = 5, /* Analog mux bus B */ 1988 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1989 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1990 P6_1_TCPWM1_LINE0 = 8, /* Digital Active - tcpwm[1].line[0]:0 */ 1991 P6_1_TCPWM1_LINE_COMPL256 = 9, /* Digital Active - tcpwm[1].line_compl[256]:0 */ 1992 P6_1_TCPWM1_TR_ONE_CNT_IN0 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[0]:0 */ 1993 P6_1_TCPWM1_TR_ONE_CNT_IN769 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[769]:0 */ 1994 P6_1_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:0 */ 1995 P6_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:0 */ 1996 P6_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:0 */ 1997 P6_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:0 */ 1998 P6_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:0 */ 1999 2000 /* P6.2 */ 2001 P6_2_GPIO = 0, /* GPIO controls 'out' */ 2002 P6_2_AMUXA = 4, /* Analog mux bus A */ 2003 P6_2_AMUXB = 5, /* Analog mux bus B */ 2004 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2005 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2006 P6_2_TCPWM1_LINE257 = 8, /* Digital Active - tcpwm[1].line[257]:0 */ 2007 P6_2_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 2008 P6_2_TCPWM1_TR_ONE_CNT_IN771 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[771]:0 */ 2009 P6_2_TCPWM1_TR_ONE_CNT_IN1 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[1]:0 */ 2010 P6_2_TCPWM1_LINE524 = 16, /* Digital Active - tcpwm[1].line[524]:0 */ 2011 P6_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:0 */ 2012 P6_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:0 */ 2013 P6_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:0 */ 2014 P6_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:0 */ 2015 P6_2_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:0 */ 2016 P6_2_TCPWM0_LINE_COMPL0 = 22, /* Digital Active - tcpwm[0].line_compl[0] */ 2017 P6_2_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:0 */ 2018 2019 /* P6.3 */ 2020 P6_3_GPIO = 0, /* GPIO controls 'out' */ 2021 P6_3_AMUXA = 4, /* Analog mux bus A */ 2022 P6_3_AMUXB = 5, /* Analog mux bus B */ 2023 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2024 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2025 P6_3_TCPWM1_LINE1 = 8, /* Digital Active - tcpwm[1].line[1]:0 */ 2026 P6_3_TCPWM1_LINE_COMPL257 = 9, /* Digital Active - tcpwm[1].line_compl[257]:0 */ 2027 P6_3_TCPWM1_TR_ONE_CNT_IN3 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[3]:0 */ 2028 P6_3_TCPWM1_TR_ONE_CNT_IN772 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[772]:0 */ 2029 P6_3_TCPWM1_LINE_COMPL524 = 16, /* Digital Active - tcpwm[1].line_compl[524]:0 */ 2030 P6_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:0 */ 2031 P6_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:0 */ 2032 P6_3_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:0 */ 2033 P6_3_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:0 */ 2034 P6_3_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:0 */ 2035 P6_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:0 */ 2036 P6_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 2037 2038 /* P6.4 */ 2039 P6_4_GPIO = 0, /* GPIO controls 'out' */ 2040 P6_4_AMUXA = 4, /* Analog mux bus A */ 2041 P6_4_AMUXB = 5, /* Analog mux bus B */ 2042 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2043 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2044 P6_4_TCPWM1_LINE258 = 8, /* Digital Active - tcpwm[1].line[258]:0 */ 2045 P6_4_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 2046 P6_4_TCPWM1_TR_ONE_CNT_IN774 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[774]:0 */ 2047 P6_4_TCPWM1_TR_ONE_CNT_IN4 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[4]:0 */ 2048 P6_4_TCPWM1_TR_ONE_CNT_IN1572 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1572]:0 */ 2049 P6_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:0 */ 2050 P6_4_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:0 */ 2051 P6_4_TCPWM0_TR_ONE_CNT_IN0 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[0] */ 2052 P6_4_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:0 */ 2053 P6_4_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:0 */ 2054 2055 /* P6.5 */ 2056 P6_5_GPIO = 0, /* GPIO controls 'out' */ 2057 P6_5_AMUXA = 4, /* Analog mux bus A */ 2058 P6_5_AMUXB = 5, /* Analog mux bus B */ 2059 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2060 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2061 P6_5_TCPWM1_LINE2 = 8, /* Digital Active - tcpwm[1].line[2]:0 */ 2062 P6_5_TCPWM1_LINE_COMPL258 = 9, /* Digital Active - tcpwm[1].line_compl[258]:0 */ 2063 P6_5_TCPWM1_TR_ONE_CNT_IN6 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[6]:0 */ 2064 P6_5_TCPWM1_TR_ONE_CNT_IN775 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[775]:0 */ 2065 P6_5_TCPWM1_TR_ONE_CNT_IN1573 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1573]:0 */ 2066 P6_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:0 */ 2067 P6_5_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:0 */ 2068 P6_5_TCPWM0_TR_ONE_CNT_IN1 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1] */ 2069 P6_5_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:0 */ 2070 P6_5_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:0 */ 2071 2072 /* P6.6 */ 2073 P6_6_GPIO = 0, /* GPIO controls 'out' */ 2074 P6_6_AMUXA = 4, /* Analog mux bus A */ 2075 P6_6_AMUXB = 5, /* Analog mux bus B */ 2076 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2077 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2078 P6_6_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:0 */ 2079 P6_6_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 2080 P6_6_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:0 */ 2081 P6_6_TCPWM1_TR_ONE_CNT_IN7 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[7]:0 */ 2082 P6_6_SCB4_SPI_SELECT3 = 19, /* Digital Active - scb[4].spi_select3:0 */ 2083 P6_6_PERI_TR_IO_INPUT8 = 26, /* Digital Active - peri.tr_io_input[8]:0 */ 2084 2085 /* P6.7 */ 2086 P6_7_GPIO = 0, /* GPIO controls 'out' */ 2087 P6_7_AMUXA = 4, /* Analog mux bus A */ 2088 P6_7_AMUXB = 5, /* Analog mux bus B */ 2089 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2090 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2091 P6_7_TCPWM1_LINE3 = 8, /* Digital Active - tcpwm[1].line[3]:0 */ 2092 P6_7_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:0 */ 2093 P6_7_TCPWM1_TR_ONE_CNT_IN9 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[9]:0 */ 2094 P6_7_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:0 */ 2095 P6_7_PERI_TR_IO_INPUT9 = 26, /* Digital Active - peri.tr_io_input[9]:0 */ 2096 2097 /* P7.0 */ 2098 P7_0_GPIO = 0, /* GPIO controls 'out' */ 2099 P7_0_AMUXA = 4, /* Analog mux bus A */ 2100 P7_0_AMUXB = 5, /* Analog mux bus B */ 2101 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2102 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2103 P7_0_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:0 */ 2104 P7_0_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 2105 P7_0_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:0 */ 2106 P7_0_TCPWM1_TR_ONE_CNT_IN10 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[10]:0 */ 2107 P7_0_SCB5_UART_RX = 17, /* Digital Active - scb[5].uart_rx:1 */ 2108 P7_0_SCB5_SPI_MISO = 19, /* Digital Active - scb[5].spi_miso:1 */ 2109 P7_0_LIN0_LIN_RX4 = 20, /* Digital Active - lin[0].lin_rx[4]:1 */ 2110 P7_0_TCPWM0_LINE1 = 22, /* Digital Active - tcpwm[0].line[1] */ 2111 P7_0_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:0 */ 2112 P7_0_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:0 */ 2113 2114 /* P7.1 */ 2115 P7_1_GPIO = 0, /* GPIO controls 'out' */ 2116 P7_1_AMUXA = 4, /* Analog mux bus A */ 2117 P7_1_AMUXB = 5, /* Analog mux bus B */ 2118 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2119 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2120 P7_1_TCPWM1_LINE15 = 8, /* Digital Active - tcpwm[1].line[15]:0 */ 2121 P7_1_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:0 */ 2122 P7_1_TCPWM1_TR_ONE_CNT_IN45 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[45]:0 */ 2123 P7_1_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:0 */ 2124 P7_1_SCB5_UART_TX = 17, /* Digital Active - scb[5].uart_tx:1 */ 2125 P7_1_SCB5_I2C_SDA = 18, /* Digital Active - scb[5].i2c_sda:1 */ 2126 P7_1_SCB5_SPI_MOSI = 19, /* Digital Active - scb[5].spi_mosi:1 */ 2127 P7_1_LIN0_LIN_TX4 = 20, /* Digital Active - lin[0].lin_tx[4]:1 */ 2128 P7_1_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:0 */ 2129 P7_1_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:0 */ 2130 2131 /* P7.2 */ 2132 P7_2_GPIO = 0, /* GPIO controls 'out' */ 2133 P7_2_AMUXA = 4, /* Analog mux bus A */ 2134 P7_2_AMUXB = 5, /* Analog mux bus B */ 2135 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2136 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2137 P7_2_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:0 */ 2138 P7_2_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 2139 P7_2_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:0 */ 2140 P7_2_TCPWM1_TR_ONE_CNT_IN46 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[46]:0 */ 2141 P7_2_SCB5_UART_RTS = 17, /* Digital Active - scb[5].uart_rts:1 */ 2142 P7_2_SCB5_I2C_SCL = 18, /* Digital Active - scb[5].i2c_scl:1 */ 2143 P7_2_SCB5_SPI_CLK = 19, /* Digital Active - scb[5].spi_clk:1 */ 2144 P7_2_LIN0_LIN_EN4 = 20, /* Digital Active - lin[0].lin_en[4]:1 */ 2145 P7_2_TCPWM0_LINE_COMPL1 = 22, /* Digital Active - tcpwm[0].line_compl[1] */ 2146 P7_2_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:0 */ 2147 P7_2_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:0 */ 2148 2149 /* P7.3 */ 2150 P7_3_GPIO = 0, /* GPIO controls 'out' */ 2151 P7_3_AMUXA = 4, /* Analog mux bus A */ 2152 P7_3_AMUXB = 5, /* Analog mux bus B */ 2153 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2154 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2155 P7_3_TCPWM1_LINE16 = 8, /* Digital Active - tcpwm[1].line[16]:0 */ 2156 P7_3_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:0 */ 2157 P7_3_TCPWM1_TR_ONE_CNT_IN48 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[48]:0 */ 2158 P7_3_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:0 */ 2159 P7_3_SCB5_UART_CTS = 17, /* Digital Active - scb[5].uart_cts:1 */ 2160 P7_3_SCB5_SPI_SELECT0 = 19, /* Digital Active - scb[5].spi_select0:1 */ 2161 P7_3_CANFD0_TTCAN_TX4 = 21, /* Digital Active - canfd[0].ttcan_tx[4]:0 */ 2162 P7_3_TCPWM0_TR_ONE_CNT_IN3 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[3] */ 2163 P7_3_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:0 */ 2164 P7_3_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:0 */ 2165 2166 /* P7.4 */ 2167 P7_4_GPIO = 0, /* GPIO controls 'out' */ 2168 P7_4_AMUXA = 4, /* Analog mux bus A */ 2169 P7_4_AMUXB = 5, /* Analog mux bus B */ 2170 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2171 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2172 P7_4_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:0 */ 2173 P7_4_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 2174 P7_4_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:0 */ 2175 P7_4_TCPWM1_TR_ONE_CNT_IN49 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[49]:0 */ 2176 P7_4_SCB5_SPI_SELECT1 = 19, /* Digital Active - scb[5].spi_select1:1 */ 2177 P7_4_CANFD0_TTCAN_RX4 = 21, /* Digital Active - canfd[0].ttcan_rx[4]:0 */ 2178 P7_4_TCPWM0_TR_ONE_CNT_IN4 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[4] */ 2179 P7_4_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:0 */ 2180 P7_4_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:0 */ 2181 2182 /* P7.5 */ 2183 P7_5_GPIO = 0, /* GPIO controls 'out' */ 2184 P7_5_AMUXA = 4, /* Analog mux bus A */ 2185 P7_5_AMUXB = 5, /* Analog mux bus B */ 2186 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2187 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2188 P7_5_TCPWM1_LINE17 = 8, /* Digital Active - tcpwm[1].line[17]:0 */ 2189 P7_5_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:0 */ 2190 P7_5_TCPWM1_TR_ONE_CNT_IN51 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[51]:0 */ 2191 P7_5_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:0 */ 2192 P7_5_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:0 */ 2193 P7_5_SCB5_SPI_SELECT2 = 19, /* Digital Active - scb[5].spi_select2:1 */ 2194 P7_5_TCPWM0_LINE514 = 22, /* Digital Active - tcpwm[0].line[514] */ 2195 P7_5_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:0 */ 2196 P7_5_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:0 */ 2197 2198 /* P7.6 */ 2199 P7_6_GPIO = 0, /* GPIO controls 'out' */ 2200 P7_6_AMUXA = 4, /* Analog mux bus A */ 2201 P7_6_AMUXB = 5, /* Analog mux bus B */ 2202 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2203 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2204 P7_6_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:0 */ 2205 P7_6_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 2206 P7_6_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:0 */ 2207 P7_6_TCPWM1_TR_ONE_CNT_IN52 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[52]:0 */ 2208 P7_6_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:0 */ 2209 P7_6_PERI_TR_IO_INPUT16 = 26, /* Digital Active - peri.tr_io_input[16]:0 */ 2210 2211 /* P7.7 */ 2212 P7_7_GPIO = 0, /* GPIO controls 'out' */ 2213 P7_7_AMUXA = 4, /* Analog mux bus A */ 2214 P7_7_AMUXB = 5, /* Analog mux bus B */ 2215 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2216 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2217 P7_7_TCPWM1_LINE18 = 8, /* Digital Active - tcpwm[1].line[18]:0 */ 2218 P7_7_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:0 */ 2219 P7_7_TCPWM1_TR_ONE_CNT_IN54 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[54]:0 */ 2220 P7_7_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:0 */ 2221 P7_7_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:0 */ 2222 P7_7_PERI_TR_IO_INPUT17 = 26, /* Digital Active - peri.tr_io_input[17]:0 */ 2223 2224 /* P8.0 */ 2225 P8_0_GPIO = 0, /* GPIO controls 'out' */ 2226 P8_0_AMUXA = 4, /* Analog mux bus A */ 2227 P8_0_AMUXB = 5, /* Analog mux bus B */ 2228 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2229 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2230 P8_0_TCPWM1_LINE19 = 8, /* Digital Active - tcpwm[1].line[19]:0 */ 2231 P8_0_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 2232 P8_0_TCPWM1_TR_ONE_CNT_IN57 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[57]:0 */ 2233 P8_0_TCPWM1_TR_ONE_CNT_IN55 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[55]:0 */ 2234 P8_0_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:1 */ 2235 P8_0_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:1 */ 2236 P8_0_CANFD0_TTCAN_TX0 = 21, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 2237 P8_0_TCPWM0_LINE_COMPL514 = 22, /* Digital Active - tcpwm[0].line_compl[514] */ 2238 P8_0_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:0 */ 2239 P8_0_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:0 */ 2240 2241 /* P8.1 */ 2242 P8_1_GPIO = 0, /* GPIO controls 'out' */ 2243 P8_1_AMUXA = 4, /* Analog mux bus A */ 2244 P8_1_AMUXB = 5, /* Analog mux bus B */ 2245 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2246 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2247 P8_1_TCPWM1_LINE20 = 8, /* Digital Active - tcpwm[1].line[20]:0 */ 2248 P8_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 2249 P8_1_TCPWM1_TR_ONE_CNT_IN60 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[60]:0 */ 2250 P8_1_TCPWM1_TR_ONE_CNT_IN58 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[58]:0 */ 2251 P8_1_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:1 */ 2252 P8_1_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:1 */ 2253 P8_1_CANFD0_TTCAN_RX0 = 21, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 2254 P8_1_TCPWM0_TR_ONE_CNT_IN1542 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1542] */ 2255 P8_1_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:0 */ 2256 P8_1_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:0 */ 2257 P8_1_PERI_TR_IO_INPUT14 = 26, /* Digital Active - peri.tr_io_input[14]:0 */ 2258 2259 /* P8.2 */ 2260 P8_2_GPIO = 0, /* GPIO controls 'out' */ 2261 P8_2_AMUXA = 4, /* Analog mux bus A */ 2262 P8_2_AMUXB = 5, /* Analog mux bus B */ 2263 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2264 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2265 P8_2_TCPWM1_LINE21 = 8, /* Digital Active - tcpwm[1].line[21]:0 */ 2266 P8_2_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 2267 P8_2_TCPWM1_TR_ONE_CNT_IN63 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[63]:0 */ 2268 P8_2_TCPWM1_TR_ONE_CNT_IN61 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[61]:0 */ 2269 P8_2_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:1 */ 2270 P8_2_LIN0_LIN_EN2 = 20, /* Digital Active - lin[0].lin_en[2]:1 */ 2271 P8_2_TCPWM0_TR_ONE_CNT_IN1543 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1543] */ 2272 P8_2_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:0 */ 2273 P8_2_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:0 */ 2274 P8_2_PERI_TR_IO_INPUT15 = 26, /* Digital Active - peri.tr_io_input[15]:0 */ 2275 2276 /* P8.3 */ 2277 P8_3_GPIO = 0, /* GPIO controls 'out' */ 2278 P8_3_AMUXA = 4, /* Analog mux bus A */ 2279 P8_3_AMUXB = 5, /* Analog mux bus B */ 2280 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2281 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2282 P8_3_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:0 */ 2283 P8_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 2284 P8_3_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:0 */ 2285 P8_3_TCPWM1_TR_ONE_CNT_IN64 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[64]:0 */ 2286 P8_3_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:1 */ 2287 P8_3_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:1 */ 2288 P8_3_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:1 */ 2289 2290 /* P8.4 */ 2291 P8_4_GPIO = 0, /* GPIO controls 'out' */ 2292 P8_4_AMUXA = 4, /* Analog mux bus A */ 2293 P8_4_AMUXB = 5, /* Analog mux bus B */ 2294 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2295 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2296 P8_4_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:0 */ 2297 P8_4_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 2298 P8_4_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:0 */ 2299 P8_4_TCPWM1_TR_ONE_CNT_IN67 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[67]:0 */ 2300 P8_4_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:1 */ 2301 P8_4_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:1 */ 2302 2303 /* P9.0 */ 2304 P9_0_GPIO = 0, /* GPIO controls 'out' */ 2305 P9_0_AMUXA = 4, /* Analog mux bus A */ 2306 P9_0_AMUXB = 5, /* Analog mux bus B */ 2307 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2308 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2309 P9_0_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:0 */ 2310 P9_0_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 2311 P9_0_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:0 */ 2312 P9_0_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:0 */ 2313 P9_0_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:1 */ 2314 P9_0_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:1 */ 2315 2316 /* P9.1 */ 2317 P9_1_GPIO = 0, /* GPIO controls 'out' */ 2318 P9_1_AMUXA = 4, /* Analog mux bus A */ 2319 P9_1_AMUXB = 5, /* Analog mux bus B */ 2320 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2321 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2322 P9_1_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:0 */ 2323 P9_1_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:0 */ 2324 P9_1_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:0 */ 2325 P9_1_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:0 */ 2326 P9_1_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:1 */ 2327 P9_1_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:0 */ 2328 2329 /* P9.2 */ 2330 P9_2_GPIO = 0, /* GPIO controls 'out' */ 2331 P9_2_AMUXA = 4, /* Analog mux bus A */ 2332 P9_2_AMUXB = 5, /* Analog mux bus B */ 2333 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2334 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2335 P9_2_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:0 */ 2336 P9_2_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:0 */ 2337 P9_2_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:0 */ 2338 P9_2_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:0 */ 2339 P9_2_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:1 */ 2340 P9_2_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:0 */ 2341 2342 /* P9.3 */ 2343 P9_3_GPIO = 0, /* GPIO controls 'out' */ 2344 P9_3_AMUXA = 4, /* Analog mux bus A */ 2345 P9_3_AMUXB = 5, /* Analog mux bus B */ 2346 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2347 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2348 P9_3_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:0 */ 2349 P9_3_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:0 */ 2350 P9_3_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:0 */ 2351 P9_3_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:0 */ 2352 P9_3_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:1 */ 2353 P9_3_LIN0_LIN_EN12 = 21, /* Digital Active - lin[0].lin_en[12]:0 */ 2354 2355 /* P10.0 */ 2356 P10_0_GPIO = 0, /* GPIO controls 'out' */ 2357 P10_0_AMUXA = 4, /* Analog mux bus A */ 2358 P10_0_AMUXB = 5, /* Analog mux bus B */ 2359 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2360 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2361 P10_0_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:0 */ 2362 P10_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:0 */ 2363 P10_0_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:0 */ 2364 P10_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:0 */ 2365 P10_0_TCPWM1_LINE522 = 16, /* Digital Active - tcpwm[1].line[522]:1 */ 2366 P10_0_SCB4_UART_RX = 17, /* Digital Active - scb[4].uart_rx:1 */ 2367 P10_0_SCB4_SPI_MISO = 19, /* Digital Active - scb[4].spi_miso:1 */ 2368 P10_0_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:2 */ 2369 P10_0_PERI_TR_IO_INPUT18 = 26, /* Digital Active - peri.tr_io_input[18]:0 */ 2370 2371 /* P10.1 */ 2372 P10_1_GPIO = 0, /* GPIO controls 'out' */ 2373 P10_1_AMUXA = 4, /* Analog mux bus A */ 2374 P10_1_AMUXB = 5, /* Analog mux bus B */ 2375 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2376 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2377 P10_1_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:0 */ 2378 P10_1_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:0 */ 2379 P10_1_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:0 */ 2380 P10_1_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:0 */ 2381 P10_1_TCPWM1_LINE_COMPL522 = 16, /* Digital Active - tcpwm[1].line_compl[522]:1 */ 2382 P10_1_SCB4_UART_TX = 17, /* Digital Active - scb[4].uart_tx:1 */ 2383 P10_1_SCB4_I2C_SDA = 18, /* Digital Active - scb[4].i2c_sda:1 */ 2384 P10_1_SCB4_SPI_MOSI = 19, /* Digital Active - scb[4].spi_mosi:1 */ 2385 P10_1_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:2 */ 2386 P10_1_PERI_TR_IO_INPUT19 = 26, /* Digital Active - peri.tr_io_input[19]:0 */ 2387 2388 /* P10.2 */ 2389 P10_2_GPIO = 0, /* GPIO controls 'out' */ 2390 P10_2_AMUXA = 4, /* Analog mux bus A */ 2391 P10_2_AMUXB = 5, /* Analog mux bus B */ 2392 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2393 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2394 P10_2_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:0 */ 2395 P10_2_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:0 */ 2396 P10_2_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:0 */ 2397 P10_2_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:0 */ 2398 P10_2_TCPWM1_TR_ONE_CNT_IN1566 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1566]:1 */ 2399 P10_2_SCB4_UART_RTS = 17, /* Digital Active - scb[4].uart_rts:1 */ 2400 P10_2_SCB4_I2C_SCL = 18, /* Digital Active - scb[4].i2c_scl:1 */ 2401 P10_2_SCB4_SPI_CLK = 19, /* Digital Active - scb[4].spi_clk:1 */ 2402 P10_2_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:1 */ 2403 P10_2_FLEXRAY0_RXDA = 26, /* Digital Active - flexray[0].rxda:0 */ 2404 2405 /* P10.3 */ 2406 P10_3_GPIO = 0, /* GPIO controls 'out' */ 2407 P10_3_AMUXA = 4, /* Analog mux bus A */ 2408 P10_3_AMUXB = 5, /* Analog mux bus B */ 2409 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2410 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2411 P10_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:0 */ 2412 P10_3_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:0 */ 2413 P10_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:0 */ 2414 P10_3_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:0 */ 2415 P10_3_TCPWM1_TR_ONE_CNT_IN1567 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1567]:1 */ 2416 P10_3_SCB4_UART_CTS = 17, /* Digital Active - scb[4].uart_cts:1 */ 2417 P10_3_SCB4_SPI_SELECT0 = 19, /* Digital Active - scb[4].spi_select0:1 */ 2418 P10_3_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:1 */ 2419 P10_3_FLEXRAY0_TXDA = 26, /* Digital Active - flexray[0].txda:0 */ 2420 2421 /* P10.4 */ 2422 P10_4_GPIO = 0, /* GPIO controls 'out' */ 2423 P10_4_AMUXA = 4, /* Analog mux bus A */ 2424 P10_4_AMUXB = 5, /* Analog mux bus B */ 2425 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2426 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2427 P10_4_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:0 */ 2428 P10_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:0 */ 2429 P10_4_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:0 */ 2430 P10_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:0 */ 2431 P10_4_TCPWM1_LINE523 = 16, /* Digital Active - tcpwm[1].line[523]:1 */ 2432 P10_4_SCB4_SPI_SELECT1 = 19, /* Digital Active - scb[4].spi_select1:1 */ 2433 P10_4_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:1 */ 2434 P10_4_FLEXRAY0_TXENA_N = 26, /* Digital Active - flexray[0].txena_n:0 */ 2435 2436 /* P10.5 */ 2437 P10_5_GPIO = 0, /* GPIO controls 'out' */ 2438 P10_5_AMUXA = 4, /* Analog mux bus A */ 2439 P10_5_AMUXB = 5, /* Analog mux bus B */ 2440 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2441 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2442 P10_5_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:0 */ 2443 P10_5_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:0 */ 2444 P10_5_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:0 */ 2445 P10_5_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:0 */ 2446 P10_5_TCPWM1_LINE_COMPL523 = 16, /* Digital Active - tcpwm[1].line_compl[523]:1 */ 2447 P10_5_SCB4_SPI_SELECT2 = 19, /* Digital Active - scb[4].spi_select2:1 */ 2448 P10_5_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:0 */ 2449 P10_5_FLEXRAY0_RXDB = 26, /* Digital Active - flexray[0].rxdb:0 */ 2450 2451 /* P10.6 */ 2452 P10_6_GPIO = 0, /* GPIO controls 'out' */ 2453 P10_6_AMUXA = 4, /* Analog mux bus A */ 2454 P10_6_AMUXB = 5, /* Analog mux bus B */ 2455 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2456 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2457 P10_6_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:0 */ 2458 P10_6_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:0 */ 2459 P10_6_TCPWM1_TR_ONE_CNT_IN1569 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1569]:1 */ 2460 P10_6_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:0 */ 2461 P10_6_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:0 */ 2462 P10_6_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:0 */ 2463 P10_6_FLEXRAY0_TXDB = 26, /* Digital Active - flexray[0].txdb:0 */ 2464 2465 /* P10.7 */ 2466 P10_7_GPIO = 0, /* GPIO controls 'out' */ 2467 P10_7_AMUXA = 4, /* Analog mux bus A */ 2468 P10_7_AMUXB = 5, /* Analog mux bus B */ 2469 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2470 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2471 P10_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:0 */ 2472 P10_7_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:0 */ 2473 P10_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:0 */ 2474 P10_7_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:0 */ 2475 P10_7_TCPWM1_TR_ONE_CNT_IN1570 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1570]:1 */ 2476 P10_7_LIN0_LIN_EN13 = 21, /* Digital Active - lin[0].lin_en[13]:0 */ 2477 P10_7_FLEXRAY0_TXENB_N = 26, /* Digital Active - flexray[0].txenb_n:0 */ 2478 2479 /* P11.0 */ 2480 P11_0_GPIO = 0, /* GPIO controls 'out' */ 2481 P11_0_AMUXA = 4, /* Analog mux bus A */ 2482 P11_0_AMUXB = 5, /* Analog mux bus B */ 2483 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2484 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2485 P11_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:2 */ 2486 P11_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:2 */ 2487 P11_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:2 */ 2488 P11_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:2 */ 2489 P11_0_AUDIOSS0_MCLK = 25, /* Digital Active - audioss[0].mclk:0 */ 2490 2491 /* P11.1 */ 2492 P11_1_GPIO = 0, /* GPIO controls 'out' */ 2493 P11_1_AMUXA = 4, /* Analog mux bus A */ 2494 P11_1_AMUXB = 5, /* Analog mux bus B */ 2495 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2496 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2497 P11_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:2 */ 2498 P11_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:2 */ 2499 P11_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:2 */ 2500 P11_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:2 */ 2501 P11_1_AUDIOSS0_TX_SCK = 25, /* Digital Active - audioss[0].tx_sck:0 */ 2502 2503 /* P11.2 */ 2504 P11_2_GPIO = 0, /* GPIO controls 'out' */ 2505 P11_2_AMUXA = 4, /* Analog mux bus A */ 2506 P11_2_AMUXB = 5, /* Analog mux bus B */ 2507 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2508 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2509 P11_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:2 */ 2510 P11_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:2 */ 2511 P11_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:2 */ 2512 P11_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:2 */ 2513 P11_2_AUDIOSS0_TX_WS = 25, /* Digital Active - audioss[0].tx_ws:0 */ 2514 2515 /* P12.0 */ 2516 P12_0_GPIO = 0, /* GPIO controls 'out' */ 2517 P12_0_AMUXA = 4, /* Analog mux bus A */ 2518 P12_0_AMUXB = 5, /* Analog mux bus B */ 2519 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2520 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2521 P12_0_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:0 */ 2522 P12_0_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:0 */ 2523 P12_0_SCB8_UART_RX = 17, /* Digital Active - scb[8].uart_rx:0 */ 2524 P12_0_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:0 */ 2525 P12_0_SCB8_SPI_MISO = 19, /* Digital Active - scb[8].spi_miso:0 */ 2526 P12_0_CANFD0_TTCAN_TX2 = 21, /* Digital Active - canfd[0].ttcan_tx[2]:1 */ 2527 P12_0_TCPWM0_LINE513 = 22, /* Digital Active - tcpwm[0].line[513] */ 2528 P12_0_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:0 */ 2529 P12_0_AUDIOSS0_TX_SDO = 25, /* Digital Active - audioss[0].tx_sdo:0 */ 2530 P12_0_PERI_TR_IO_INPUT20 = 26, /* Digital Active - peri.tr_io_input[20]:0 */ 2531 2532 /* P12.1 */ 2533 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2534 P12_1_AMUXA = 4, /* Analog mux bus A */ 2535 P12_1_AMUXB = 5, /* Analog mux bus B */ 2536 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2537 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2538 P12_1_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:0 */ 2539 P12_1_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:0 */ 2540 P12_1_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:0 */ 2541 P12_1_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:0 */ 2542 P12_1_SCB8_UART_TX = 17, /* Digital Active - scb[8].uart_tx:0 */ 2543 P12_1_SCB8_I2C_SDA = 18, /* Digital Active - scb[8].i2c_sda:0 */ 2544 P12_1_SCB8_SPI_MOSI = 19, /* Digital Active - scb[8].spi_mosi:0 */ 2545 P12_1_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:0 */ 2546 P12_1_CANFD0_TTCAN_RX2 = 21, /* Digital Active - canfd[0].ttcan_rx[2]:1 */ 2547 P12_1_TCPWM0_LINE_COMPL513 = 22, /* Digital Active - tcpwm[0].line_compl[513] */ 2548 P12_1_AUDIOSS0_CLK_I2S_IF = 25, /* Digital Active - audioss[0].clk_i2s_if:0 */ 2549 P12_1_PERI_TR_IO_INPUT21 = 26, /* Digital Active - peri.tr_io_input[21]:0 */ 2550 2551 /* P12.2 */ 2552 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2553 P12_2_AMUXA = 4, /* Analog mux bus A */ 2554 P12_2_AMUXB = 5, /* Analog mux bus B */ 2555 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2556 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2557 P12_2_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:0 */ 2558 P12_2_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:0 */ 2559 P12_2_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:0 */ 2560 P12_2_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:0 */ 2561 P12_2_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 2562 P12_2_SCB8_UART_RTS = 17, /* Digital Active - scb[8].uart_rts:0 */ 2563 P12_2_SCB8_I2C_SCL = 18, /* Digital Active - scb[8].i2c_scl:0 */ 2564 P12_2_SCB8_SPI_CLK = 19, /* Digital Active - scb[8].spi_clk:0 */ 2565 P12_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:0 */ 2566 P12_2_TCPWM0_TR_ONE_CNT_IN1539 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1539] */ 2567 P12_2_AUDIOSS0_RX_SCK = 25, /* Digital Active - audioss[0].rx_sck:0 */ 2568 2569 /* P12.3 */ 2570 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2571 P12_3_AMUXA = 4, /* Analog mux bus A */ 2572 P12_3_AMUXB = 5, /* Analog mux bus B */ 2573 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2574 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2575 P12_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:0 */ 2576 P12_3_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:0 */ 2577 P12_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:0 */ 2578 P12_3_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:0 */ 2579 P12_3_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 2580 P12_3_SCB8_UART_CTS = 17, /* Digital Active - scb[8].uart_cts:0 */ 2581 P12_3_SCB8_SPI_SELECT0 = 19, /* Digital Active - scb[8].spi_select0:0 */ 2582 P12_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:0 */ 2583 P12_3_TCPWM0_TR_ONE_CNT_IN1540 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[1540] */ 2584 P12_3_AUDIOSS0_RX_WS = 25, /* Digital Active - audioss[0].rx_ws:0 */ 2585 2586 /* P12.4 */ 2587 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2588 P12_4_AMUXA = 4, /* Analog mux bus A */ 2589 P12_4_AMUXB = 5, /* Analog mux bus B */ 2590 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2591 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2592 P12_4_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:0 */ 2593 P12_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:0 */ 2594 P12_4_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:0 */ 2595 P12_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:0 */ 2596 P12_4_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 2597 P12_4_SCB8_SPI_SELECT1 = 19, /* Digital Active - scb[8].spi_select1:0 */ 2598 P12_4_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:2 */ 2599 P12_4_TCPWM0_TR_ONE_CNT_IN7 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[7] */ 2600 P12_4_AUDIOSS0_RX_SDI = 25, /* Digital Active - audioss[0].rx_sdi:0 */ 2601 2602 /* P12.5 */ 2603 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2604 P12_5_AMUXA = 4, /* Analog mux bus A */ 2605 P12_5_AMUXB = 5, /* Analog mux bus B */ 2606 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2607 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2608 P12_5_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:0 */ 2609 P12_5_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:0 */ 2610 P12_5_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:0 */ 2611 P12_5_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:0 */ 2612 P12_5_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 2613 P12_5_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:2 */ 2614 2615 /* P12.6 */ 2616 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2617 P12_6_AMUXA = 4, /* Analog mux bus A */ 2618 P12_6_AMUXB = 5, /* Analog mux bus B */ 2619 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2620 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2621 P12_6_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:0 */ 2622 P12_6_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:0 */ 2623 P12_6_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:0 */ 2624 P12_6_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:0 */ 2625 2626 /* P12.7 */ 2627 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2628 P12_7_AMUXA = 4, /* Analog mux bus A */ 2629 P12_7_AMUXB = 5, /* Analog mux bus B */ 2630 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2631 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2632 P12_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:0 */ 2633 P12_7_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:0 */ 2634 P12_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:0 */ 2635 P12_7_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:0 */ 2636 2637 /* P13.0 */ 2638 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2639 P13_0_AMUXA = 4, /* Analog mux bus A */ 2640 P13_0_AMUXB = 5, /* Analog mux bus B */ 2641 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2642 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2643 P13_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:0 */ 2644 P13_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:0 */ 2645 P13_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:0 */ 2646 P13_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:0 */ 2647 P13_0_PASS0_SAR_EXT_MUX_SEL6 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[6] */ 2648 P13_0_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:0 */ 2649 P13_0_LIN0_LIN_RX3 = 20, /* Digital Active - lin[0].lin_rx[3]:1 */ 2650 P13_0_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:0 */ 2651 P13_0_TCPWM0_TR_ONE_CNT_IN6 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[6] */ 2652 P13_0_AUDIOSS1_MCLK = 25, /* Digital Active - audioss[1].mclk:0 */ 2653 2654 /* P13.1 */ 2655 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2656 P13_1_AMUXA = 4, /* Analog mux bus A */ 2657 P13_1_AMUXB = 5, /* Analog mux bus B */ 2658 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2659 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2660 P13_1_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:0 */ 2661 P13_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:0 */ 2662 P13_1_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:0 */ 2663 P13_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:0 */ 2664 P13_1_PASS0_SAR_EXT_MUX_SEL7 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[7] */ 2665 P13_1_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:0 */ 2666 P13_1_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:0 */ 2667 P13_1_LIN0_LIN_TX3 = 20, /* Digital Active - lin[0].lin_tx[3]:1 */ 2668 P13_1_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:0 */ 2669 P13_1_TCPWM0_LINE_COMPL2 = 22, /* Digital Active - tcpwm[0].line_compl[2] */ 2670 P13_1_AUDIOSS1_TX_SCK = 25, /* Digital Active - audioss[1].tx_sck:0 */ 2671 2672 /* P13.2 */ 2673 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2674 P13_2_AMUXA = 4, /* Analog mux bus A */ 2675 P13_2_AMUXB = 5, /* Analog mux bus B */ 2676 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2677 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2678 P13_2_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:0 */ 2679 P13_2_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:0 */ 2680 P13_2_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:0 */ 2681 P13_2_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:0 */ 2682 P13_2_PASS0_SAR_EXT_MUX_SEL8 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[8] */ 2683 P13_2_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:0 */ 2684 P13_2_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:0 */ 2685 P13_2_LIN0_LIN_EN3 = 20, /* Digital Active - lin[0].lin_en[3]:1 */ 2686 P13_2_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:0 */ 2687 P13_2_TCPWM0_LINE2 = 22, /* Digital Active - tcpwm[0].line[2] */ 2688 P13_2_AUDIOSS1_TX_WS = 25, /* Digital Active - audioss[1].tx_ws:0 */ 2689 2690 /* P13.3 */ 2691 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2692 P13_3_AMUXA = 4, /* Analog mux bus A */ 2693 P13_3_AMUXB = 5, /* Analog mux bus B */ 2694 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2695 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2696 P13_3_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:0 */ 2697 P13_3_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:0 */ 2698 P13_3_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:0 */ 2699 P13_3_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:0 */ 2700 P13_3_PASS0_SAR_EXT_MUX_EN2 = 16, /* Digital Active - pass[0].sar_ext_mux_en[2] */ 2701 P13_3_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:0 */ 2702 P13_3_LIN0_LIN_RX2 = 20, /* Digital Active - lin[0].lin_rx[2]:2 */ 2703 P13_3_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:0 */ 2704 P13_3_AUDIOSS1_TX_SDO = 25, /* Digital Active - audioss[1].tx_sdo:0 */ 2705 2706 /* P13.4 */ 2707 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2708 P13_4_AMUXA = 4, /* Analog mux bus A */ 2709 P13_4_AMUXB = 5, /* Analog mux bus B */ 2710 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2711 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2712 P13_4_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:0 */ 2713 P13_4_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:0 */ 2714 P13_4_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:0 */ 2715 P13_4_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:0 */ 2716 P13_4_TCPWM1_LINE516 = 16, /* Digital Active - tcpwm[1].line[516]:1 */ 2717 P13_4_LIN0_LIN_TX2 = 20, /* Digital Active - lin[0].lin_tx[2]:2 */ 2718 P13_4_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:0 */ 2719 P13_4_LIN0_LIN_RX8 = 22, /* Digital Active - lin[0].lin_rx[8]:0 */ 2720 P13_4_AUDIOSS1_CLK_I2S_IF = 25, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2721 2722 /* P13.5 */ 2723 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2724 P13_5_AMUXA = 4, /* Analog mux bus A */ 2725 P13_5_AMUXB = 5, /* Analog mux bus B */ 2726 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2727 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2728 P13_5_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:0 */ 2729 P13_5_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:0 */ 2730 P13_5_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:0 */ 2731 P13_5_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:0 */ 2732 P13_5_TCPWM1_LINE_COMPL516 = 16, /* Digital Active - tcpwm[1].line_compl[516]:1 */ 2733 P13_5_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:0 */ 2734 P13_5_LIN0_LIN_TX8 = 22, /* Digital Active - lin[0].lin_tx[8]:0 */ 2735 P13_5_AUDIOSS1_RX_SCK = 25, /* Digital Active - audioss[1].rx_sck:0 */ 2736 2737 /* P13.6 */ 2738 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2739 P13_6_AMUXA = 4, /* Analog mux bus A */ 2740 P13_6_AMUXB = 5, /* Analog mux bus B */ 2741 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2742 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2743 P13_6_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:0 */ 2744 P13_6_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:0 */ 2745 P13_6_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:0 */ 2746 P13_6_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:0 */ 2747 P13_6_TCPWM1_LINE517 = 16, /* Digital Active - tcpwm[1].line[517]:1 */ 2748 P13_6_SCB3_SPI_SELECT3 = 21, /* Digital Active - scb[3].spi_select3:0 */ 2749 P13_6_LIN0_LIN_EN8 = 22, /* Digital Active - lin[0].lin_en[8]:0 */ 2750 P13_6_AUDIOSS1_RX_WS = 25, /* Digital Active - audioss[1].rx_ws:0 */ 2751 P13_6_PERI_TR_IO_INPUT22 = 26, /* Digital Active - peri.tr_io_input[22]:0 */ 2752 2753 /* P13.7 */ 2754 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2755 P13_7_AMUXA = 4, /* Analog mux bus A */ 2756 P13_7_AMUXB = 5, /* Analog mux bus B */ 2757 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2758 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2759 P13_7_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:0 */ 2760 P13_7_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:0 */ 2761 P13_7_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:0 */ 2762 P13_7_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:0 */ 2763 P13_7_TCPWM1_LINE_COMPL517 = 16, /* Digital Active - tcpwm[1].line_compl[517]:1 */ 2764 P13_7_AUDIOSS1_RX_SDI = 25, /* Digital Active - audioss[1].rx_sdi:0 */ 2765 P13_7_PERI_TR_IO_INPUT23 = 26, /* Digital Active - peri.tr_io_input[23]:0 */ 2766 2767 /* P14.0 */ 2768 P14_0_GPIO = 0, /* GPIO controls 'out' */ 2769 P14_0_AMUXA = 4, /* Analog mux bus A */ 2770 P14_0_AMUXB = 5, /* Analog mux bus B */ 2771 P14_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2772 P14_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2773 P14_0_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:0 */ 2774 P14_0_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:0 */ 2775 P14_0_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:0 */ 2776 P14_0_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:0 */ 2777 P14_0_TCPWM1_LINE518 = 16, /* Digital Active - tcpwm[1].line[518]:1 */ 2778 P14_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:0 */ 2779 P14_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:0 */ 2780 P14_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2781 P14_0_TCPWM0_LINE257 = 22, /* Digital Active - tcpwm[0].line[257] */ 2782 P14_0_AUDIOSS2_MCLK = 25, /* Digital Active - audioss[2].mclk:0 */ 2783 2784 /* P14.1 */ 2785 P14_1_GPIO = 0, /* GPIO controls 'out' */ 2786 P14_1_AMUXA = 4, /* Analog mux bus A */ 2787 P14_1_AMUXB = 5, /* Analog mux bus B */ 2788 P14_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2789 P14_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2790 P14_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:0 */ 2791 P14_1_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:0 */ 2792 P14_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:0 */ 2793 P14_1_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:0 */ 2794 P14_1_TCPWM1_LINE_COMPL518 = 16, /* Digital Active - tcpwm[1].line_compl[518]:1 */ 2795 P14_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:0 */ 2796 P14_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:0 */ 2797 P14_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:0 */ 2798 P14_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2799 P14_1_TCPWM0_LINE_COMPL257 = 22, /* Digital Active - tcpwm[0].line_compl[257] */ 2800 P14_1_AUDIOSS2_TX_SCK = 25, /* Digital Active - audioss[2].tx_sck:0 */ 2801 2802 /* P14.2 */ 2803 P14_2_GPIO = 0, /* GPIO controls 'out' */ 2804 P14_2_AMUXA = 4, /* Analog mux bus A */ 2805 P14_2_AMUXB = 5, /* Analog mux bus B */ 2806 P14_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2807 P14_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2808 P14_2_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:0 */ 2809 P14_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:0 */ 2810 P14_2_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:0 */ 2811 P14_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:0 */ 2812 P14_2_TCPWM1_LINE519 = 16, /* Digital Active - tcpwm[1].line[519]:1 */ 2813 P14_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:0 */ 2814 P14_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:0 */ 2815 P14_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:0 */ 2816 P14_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:1 */ 2817 P14_2_TCPWM0_TR_ONE_CNT_IN771 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[771] */ 2818 2819 /* P14.3 */ 2820 P14_3_GPIO = 0, /* GPIO controls 'out' */ 2821 P14_3_AMUXA = 4, /* Analog mux bus A */ 2822 P14_3_AMUXB = 5, /* Analog mux bus B */ 2823 P14_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2824 P14_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2825 P14_3_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:0 */ 2826 P14_3_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:0 */ 2827 P14_3_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:0 */ 2828 P14_3_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:0 */ 2829 P14_3_TCPWM1_LINE_COMPL519 = 16, /* Digital Active - tcpwm[1].line_compl[519]:1 */ 2830 P14_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:0 */ 2831 P14_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:0 */ 2832 P14_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:1 */ 2833 P14_3_TCPWM0_TR_ONE_CNT_IN772 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[772] */ 2834 2835 /* P14.4 */ 2836 P14_4_GPIO = 0, /* GPIO controls 'out' */ 2837 P14_4_AMUXA = 4, /* Analog mux bus A */ 2838 P14_4_AMUXB = 5, /* Analog mux bus B */ 2839 P14_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2840 P14_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2841 P14_4_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:0 */ 2842 P14_4_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:0 */ 2843 P14_4_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:0 */ 2844 P14_4_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:0 */ 2845 P14_4_TCPWM1_TR_ONE_CNT_IN1548 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1548]:1 */ 2846 P14_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:0 */ 2847 P14_4_LIN0_LIN_EN6 = 20, /* Digital Active - lin[0].lin_en[6]:1 */ 2848 P14_4_AUDIOSS2_TX_WS = 25, /* Digital Active - audioss[2].tx_ws:0 */ 2849 2850 /* P14.5 */ 2851 P14_5_GPIO = 0, /* GPIO controls 'out' */ 2852 P14_5_AMUXA = 4, /* Analog mux bus A */ 2853 P14_5_AMUXB = 5, /* Analog mux bus B */ 2854 P14_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2855 P14_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2856 P14_5_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:0 */ 2857 P14_5_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:0 */ 2858 P14_5_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:0 */ 2859 P14_5_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:0 */ 2860 P14_5_TCPWM1_TR_ONE_CNT_IN1549 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1549]:1 */ 2861 P14_5_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:0 */ 2862 P14_5_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:0 */ 2863 P14_5_AUDIOSS2_TX_SDO = 25, /* Digital Active - audioss[2].tx_sdo:0 */ 2864 2865 /* P14.6 */ 2866 P14_6_GPIO = 0, /* GPIO controls 'out' */ 2867 P14_6_AMUXA = 4, /* Analog mux bus A */ 2868 P14_6_AMUXB = 5, /* Analog mux bus B */ 2869 P14_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2870 P14_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2871 P14_6_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:0 */ 2872 P14_6_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:0 */ 2873 P14_6_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:0 */ 2874 P14_6_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:0 */ 2875 P14_6_TCPWM1_TR_ONE_CNT_IN1551 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1551]:1 */ 2876 P14_6_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:0 */ 2877 P14_6_PERI_TR_IO_INPUT24 = 26, /* Digital Active - peri.tr_io_input[24]:0 */ 2878 2879 /* P14.7 */ 2880 P14_7_GPIO = 0, /* GPIO controls 'out' */ 2881 P14_7_AMUXA = 4, /* Analog mux bus A */ 2882 P14_7_AMUXB = 5, /* Analog mux bus B */ 2883 P14_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2884 P14_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2885 P14_7_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:0 */ 2886 P14_7_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:0 */ 2887 P14_7_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:0 */ 2888 P14_7_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:0 */ 2889 P14_7_TCPWM1_TR_ONE_CNT_IN1552 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1552]:1 */ 2890 P14_7_LIN0_LIN_EN14 = 18, /* Digital Active - lin[0].lin_en[14]:0 */ 2891 P14_7_PERI_TR_IO_INPUT25 = 26, /* Digital Active - peri.tr_io_input[25]:0 */ 2892 2893 /* P15.0 */ 2894 P15_0_GPIO = 0, /* GPIO controls 'out' */ 2895 P15_0_AMUXA = 4, /* Analog mux bus A */ 2896 P15_0_AMUXB = 5, /* Analog mux bus B */ 2897 P15_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2898 P15_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2899 P15_0_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:0 */ 2900 P15_0_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:0 */ 2901 P15_0_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:0 */ 2902 P15_0_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:0 */ 2903 P15_0_TCPWM1_TR_ONE_CNT_IN1554 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1554]:1 */ 2904 P15_0_SCB9_UART_RX = 17, /* Digital Active - scb[9].uart_rx:0 */ 2905 P15_0_SCB9_SPI_MISO = 19, /* Digital Active - scb[9].spi_miso:0 */ 2906 P15_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:1 */ 2907 P15_0_AUDIOSS2_CLK_I2S_IF = 25, /* Digital Active - audioss[2].clk_i2s_if:0 */ 2908 2909 /* P15.1 */ 2910 P15_1_GPIO = 0, /* GPIO controls 'out' */ 2911 P15_1_AMUXA = 4, /* Analog mux bus A */ 2912 P15_1_AMUXB = 5, /* Analog mux bus B */ 2913 P15_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2914 P15_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2915 P15_1_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:0 */ 2916 P15_1_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:0 */ 2917 P15_1_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:0 */ 2918 P15_1_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:0 */ 2919 P15_1_TCPWM1_TR_ONE_CNT_IN1555 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1555]:1 */ 2920 P15_1_SCB9_UART_TX = 17, /* Digital Active - scb[9].uart_tx:0 */ 2921 P15_1_SCB9_I2C_SDA = 18, /* Digital Active - scb[9].i2c_sda:0 */ 2922 P15_1_SCB9_SPI_MOSI = 19, /* Digital Active - scb[9].spi_mosi:0 */ 2923 P15_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:1 */ 2924 P15_1_AUDIOSS2_RX_SCK = 25, /* Digital Active - audioss[2].rx_sck:0 */ 2925 2926 /* P15.2 */ 2927 P15_2_GPIO = 0, /* GPIO controls 'out' */ 2928 P15_2_AMUXA = 4, /* Analog mux bus A */ 2929 P15_2_AMUXB = 5, /* Analog mux bus B */ 2930 P15_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2931 P15_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2932 P15_2_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:0 */ 2933 P15_2_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:0 */ 2934 P15_2_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:0 */ 2935 P15_2_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:0 */ 2936 P15_2_TCPWM1_TR_ONE_CNT_IN1557 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1557]:1 */ 2937 P15_2_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:0 */ 2938 P15_2_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:0 */ 2939 P15_2_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:0 */ 2940 P15_2_AUDIOSS2_RX_WS = 25, /* Digital Active - audioss[2].rx_ws:0 */ 2941 2942 /* P15.3 */ 2943 P15_3_GPIO = 0, /* GPIO controls 'out' */ 2944 P15_3_AMUXA = 4, /* Analog mux bus A */ 2945 P15_3_AMUXB = 5, /* Analog mux bus B */ 2946 P15_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2947 P15_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2948 P15_3_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:0 */ 2949 P15_3_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:0 */ 2950 P15_3_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:0 */ 2951 P15_3_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:0 */ 2952 P15_3_TCPWM1_TR_ONE_CNT_IN1558 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1558]:1 */ 2953 P15_3_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:0 */ 2954 P15_3_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:0 */ 2955 P15_3_AUDIOSS2_RX_SDI = 25, /* Digital Active - audioss[2].rx_sdi:0 */ 2956 2957 /* P16.0 */ 2958 P16_0_GPIO = 0, /* GPIO controls 'out' */ 2959 P16_0_AMUXA = 4, /* Analog mux bus A */ 2960 P16_0_AMUXB = 5, /* Analog mux bus B */ 2961 P16_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2962 P16_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2963 P16_0_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:0 */ 2964 P16_0_TCPWM1_LINE_COMPL59 = 9, /* Digital Active - tcpwm[1].line_compl[59]:0 */ 2965 P16_0_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:0 */ 2966 P16_0_TCPWM1_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[178]:0 */ 2967 P16_0_TCPWM1_LINE512 = 16, /* Digital Active - tcpwm[1].line[512]:1 */ 2968 P16_0_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:0 */ 2969 P16_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:0 */ 2970 2971 /* P16.1 */ 2972 P16_1_GPIO = 0, /* GPIO controls 'out' */ 2973 P16_1_AMUXA = 4, /* Analog mux bus A */ 2974 P16_1_AMUXB = 5, /* Analog mux bus B */ 2975 P16_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2976 P16_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2977 P16_1_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:0 */ 2978 P16_1_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:0 */ 2979 P16_1_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:0 */ 2980 P16_1_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:0 */ 2981 P16_1_TCPWM1_LINE_COMPL512 = 16, /* Digital Active - tcpwm[1].line_compl[512]:1 */ 2982 P16_1_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:0 */ 2983 P16_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:0 */ 2984 2985 /* P16.2 */ 2986 P16_2_GPIO = 0, /* GPIO controls 'out' */ 2987 P16_2_AMUXA = 4, /* Analog mux bus A */ 2988 P16_2_AMUXB = 5, /* Analog mux bus B */ 2989 P16_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2990 P16_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2991 P16_2_TCPWM1_LINE62 = 8, /* Digital Active - tcpwm[1].line[62]:0 */ 2992 P16_2_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:0 */ 2993 P16_2_TCPWM1_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[186]:0 */ 2994 P16_2_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:0 */ 2995 P16_2_TCPWM1_LINE513 = 16, /* Digital Active - tcpwm[1].line[513]:1 */ 2996 P16_2_SCB9_SPI_SELECT3 = 19, /* Digital Active - scb[9].spi_select3:0 */ 2997 P16_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:0 */ 2998 2999 /* P16.3 */ 3000 P16_3_GPIO = 0, /* GPIO controls 'out' */ 3001 P16_3_AMUXA = 4, /* Analog mux bus A */ 3002 P16_3_AMUXB = 5, /* Analog mux bus B */ 3003 P16_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3004 P16_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3005 P16_3_TCPWM1_LINE62 = 8, /* Digital Active - tcpwm[1].line[62]:1 */ 3006 P16_3_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:0 */ 3007 P16_3_TCPWM1_TR_ONE_CNT_IN186 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[186]:1 */ 3008 P16_3_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:0 */ 3009 P16_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:1 */ 3010 3011 /* P16.4 */ 3012 P16_4_GPIO = 0, /* GPIO controls 'out' */ 3013 P16_4_AMUXA = 4, /* Analog mux bus A */ 3014 P16_4_AMUXB = 5, /* Analog mux bus B */ 3015 P16_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3016 P16_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3017 P16_4_TCPWM1_LINE68 = 8, /* Digital Active - tcpwm[1].line[68]:1 */ 3018 P16_4_TCPWM1_LINE_COMPL69 = 9, /* Digital Active - tcpwm[1].line_compl[69]:1 */ 3019 P16_4_TCPWM1_TR_ONE_CNT_IN204 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[204]:1 */ 3020 P16_4_TCPWM1_TR_ONE_CNT_IN208 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[208]:1 */ 3021 3022 /* P16.5 */ 3023 P16_5_GPIO = 0, /* GPIO controls 'out' */ 3024 P16_5_AMUXA = 4, /* Analog mux bus A */ 3025 P16_5_AMUXB = 5, /* Analog mux bus B */ 3026 P16_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3027 P16_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3028 P16_5_TCPWM1_LINE67 = 8, /* Digital Active - tcpwm[1].line[67]:1 */ 3029 P16_5_TCPWM1_LINE_COMPL68 = 9, /* Digital Active - tcpwm[1].line_compl[68]:1 */ 3030 P16_5_TCPWM1_TR_ONE_CNT_IN201 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[201]:1 */ 3031 P16_5_TCPWM1_TR_ONE_CNT_IN205 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[205]:1 */ 3032 3033 /* P16.6 */ 3034 P16_6_GPIO = 0, /* GPIO controls 'out' */ 3035 P16_6_AMUXA = 4, /* Analog mux bus A */ 3036 P16_6_AMUXB = 5, /* Analog mux bus B */ 3037 P16_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3038 P16_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3039 P16_6_TCPWM1_LINE66 = 8, /* Digital Active - tcpwm[1].line[66]:1 */ 3040 P16_6_TCPWM1_LINE_COMPL67 = 9, /* Digital Active - tcpwm[1].line_compl[67]:1 */ 3041 P16_6_TCPWM1_TR_ONE_CNT_IN198 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[198]:1 */ 3042 P16_6_TCPWM1_TR_ONE_CNT_IN202 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[202]:1 */ 3043 3044 /* P16.7 */ 3045 P16_7_GPIO = 0, /* GPIO controls 'out' */ 3046 P16_7_AMUXA = 4, /* Analog mux bus A */ 3047 P16_7_AMUXB = 5, /* Analog mux bus B */ 3048 P16_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3049 P16_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3050 P16_7_TCPWM1_LINE65 = 8, /* Digital Active - tcpwm[1].line[65]:1 */ 3051 P16_7_TCPWM1_LINE_COMPL66 = 9, /* Digital Active - tcpwm[1].line_compl[66]:1 */ 3052 P16_7_TCPWM1_TR_ONE_CNT_IN195 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[195]:1 */ 3053 P16_7_TCPWM1_TR_ONE_CNT_IN199 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[199]:1 */ 3054 3055 /* P17.0 */ 3056 P17_0_GPIO = 0, /* GPIO controls 'out' */ 3057 P17_0_AMUXA = 4, /* Analog mux bus A */ 3058 P17_0_AMUXB = 5, /* Analog mux bus B */ 3059 P17_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3060 P17_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3061 P17_0_TCPWM1_LINE61 = 8, /* Digital Active - tcpwm[1].line[61]:1 */ 3062 P17_0_TCPWM1_LINE_COMPL62 = 9, /* Digital Active - tcpwm[1].line_compl[62]:1 */ 3063 P17_0_TCPWM1_TR_ONE_CNT_IN183 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[183]:1 */ 3064 P17_0_TCPWM1_TR_ONE_CNT_IN187 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[187]:1 */ 3065 P17_0_LIN0_LIN_RX11 = 20, /* Digital Active - lin[0].lin_rx[11]:2 */ 3066 P17_0_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:0 */ 3067 3068 /* P17.1 */ 3069 P17_1_GPIO = 0, /* GPIO controls 'out' */ 3070 P17_1_AMUXA = 4, /* Analog mux bus A */ 3071 P17_1_AMUXB = 5, /* Analog mux bus B */ 3072 P17_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3073 P17_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3074 P17_1_TCPWM1_LINE60 = 8, /* Digital Active - tcpwm[1].line[60]:1 */ 3075 P17_1_TCPWM1_LINE_COMPL61 = 9, /* Digital Active - tcpwm[1].line_compl[61]:1 */ 3076 P17_1_TCPWM1_TR_ONE_CNT_IN180 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[180]:1 */ 3077 P17_1_TCPWM1_TR_ONE_CNT_IN184 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[184]:1 */ 3078 P17_1_SCB3_UART_RX = 17, /* Digital Active - scb[3].uart_rx:1 */ 3079 P17_1_LIN0_LIN_TX11 = 20, /* Digital Active - lin[0].lin_tx[11]:2 */ 3080 P17_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:0 */ 3081 3082 /* P17.2 */ 3083 P17_2_GPIO = 0, /* GPIO controls 'out' */ 3084 P17_2_AMUXA = 4, /* Analog mux bus A */ 3085 P17_2_AMUXB = 5, /* Analog mux bus B */ 3086 P17_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3087 P17_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3088 P17_2_TCPWM1_LINE59 = 8, /* Digital Active - tcpwm[1].line[59]:1 */ 3089 P17_2_TCPWM1_LINE_COMPL60 = 9, /* Digital Active - tcpwm[1].line_compl[60]:1 */ 3090 P17_2_TCPWM1_TR_ONE_CNT_IN177 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[177]:1 */ 3091 P17_2_TCPWM1_TR_ONE_CNT_IN181 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[181]:1 */ 3092 P17_2_SCB3_UART_TX = 17, /* Digital Active - scb[3].uart_tx:1 */ 3093 P17_2_SCB3_I2C_SDA = 18, /* Digital Active - scb[3].i2c_sda:1 */ 3094 P17_2_LIN0_LIN_EN11 = 20, /* Digital Active - lin[0].lin_en[11]:2 */ 3095 3096 /* P17.3 */ 3097 P17_3_GPIO = 0, /* GPIO controls 'out' */ 3098 P17_3_AMUXA = 4, /* Analog mux bus A */ 3099 P17_3_AMUXB = 5, /* Analog mux bus B */ 3100 P17_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3101 P17_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3102 P17_3_TCPWM1_LINE58 = 8, /* Digital Active - tcpwm[1].line[58]:1 */ 3103 P17_3_TCPWM1_LINE_COMPL59 = 9, /* Digital Active - tcpwm[1].line_compl[59]:1 */ 3104 P17_3_TCPWM1_TR_ONE_CNT_IN174 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[174]:1 */ 3105 P17_3_TCPWM1_TR_ONE_CNT_IN178 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[178]:1 */ 3106 P17_3_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:1 */ 3107 P17_3_SCB3_UART_RTS = 17, /* Digital Active - scb[3].uart_rts:1 */ 3108 P17_3_SCB3_I2C_SCL = 18, /* Digital Active - scb[3].i2c_scl:1 */ 3109 P17_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:1 */ 3110 P17_3_PERI_TR_IO_INPUT26 = 26, /* Digital Active - peri.tr_io_input[26]:0 */ 3111 3112 /* P17.4 */ 3113 P17_4_GPIO = 0, /* GPIO controls 'out' */ 3114 P17_4_AMUXA = 4, /* Analog mux bus A */ 3115 P17_4_AMUXB = 5, /* Analog mux bus B */ 3116 P17_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3117 P17_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3118 P17_4_TCPWM1_LINE57 = 8, /* Digital Active - tcpwm[1].line[57]:1 */ 3119 P17_4_TCPWM1_LINE_COMPL58 = 9, /* Digital Active - tcpwm[1].line_compl[58]:1 */ 3120 P17_4_TCPWM1_TR_ONE_CNT_IN171 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[171]:1 */ 3121 P17_4_TCPWM1_TR_ONE_CNT_IN175 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[175]:1 */ 3122 P17_4_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:1 */ 3123 P17_4_SCB3_UART_CTS = 17, /* Digital Active - scb[3].uart_cts:1 */ 3124 P17_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:1 */ 3125 P17_4_PERI_TR_IO_INPUT27 = 26, /* Digital Active - peri.tr_io_input[27]:0 */ 3126 3127 /* P17.5 */ 3128 P17_5_GPIO = 0, /* GPIO controls 'out' */ 3129 P17_5_AMUXA = 4, /* Analog mux bus A */ 3130 P17_5_AMUXB = 5, /* Analog mux bus B */ 3131 P17_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3132 P17_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3133 P17_5_TCPWM1_LINE56 = 8, /* Digital Active - tcpwm[1].line[56]:1 */ 3134 P17_5_TCPWM1_LINE_COMPL57 = 9, /* Digital Active - tcpwm[1].line_compl[57]:1 */ 3135 P17_5_TCPWM1_TR_ONE_CNT_IN168 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[168]:1 */ 3136 P17_5_TCPWM1_TR_ONE_CNT_IN172 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[172]:1 */ 3137 P17_5_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:1 */ 3138 P17_5_LIN0_LIN_RX15 = 18, /* Digital Active - lin[0].lin_rx[15]:0 */ 3139 P17_5_SCB3_SPI_SELECT1 = 21, /* Digital Active - scb[3].spi_select1:1 */ 3140 3141 /* P17.6 */ 3142 P17_6_GPIO = 0, /* GPIO controls 'out' */ 3143 P17_6_AMUXA = 4, /* Analog mux bus A */ 3144 P17_6_AMUXB = 5, /* Analog mux bus B */ 3145 P17_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3146 P17_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3147 P17_6_TCPWM1_LINE260 = 8, /* Digital Active - tcpwm[1].line[260]:1 */ 3148 P17_6_TCPWM1_LINE_COMPL56 = 9, /* Digital Active - tcpwm[1].line_compl[56]:1 */ 3149 P17_6_TCPWM1_TR_ONE_CNT_IN780 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[780]:1 */ 3150 P17_6_TCPWM1_TR_ONE_CNT_IN169 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[169]:1 */ 3151 P17_6_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:1 */ 3152 P17_6_LIN0_LIN_TX15 = 18, /* Digital Active - lin[0].lin_tx[15]:0 */ 3153 P17_6_SCB3_SPI_SELECT2 = 21, /* Digital Active - scb[3].spi_select2:1 */ 3154 3155 /* P17.7 */ 3156 P17_7_GPIO = 0, /* GPIO controls 'out' */ 3157 P17_7_AMUXA = 4, /* Analog mux bus A */ 3158 P17_7_AMUXB = 5, /* Analog mux bus B */ 3159 P17_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3160 P17_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3161 P17_7_TCPWM1_LINE261 = 8, /* Digital Active - tcpwm[1].line[261]:1 */ 3162 P17_7_TCPWM1_LINE_COMPL260 = 9, /* Digital Active - tcpwm[1].line_compl[260]:1 */ 3163 P17_7_TCPWM1_TR_ONE_CNT_IN783 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[783]:1 */ 3164 P17_7_TCPWM1_TR_ONE_CNT_IN781 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[781]:1 */ 3165 P17_7_LIN0_LIN_EN15 = 18, /* Digital Active - lin[0].lin_en[15]:0 */ 3166 P17_7_LIN0_LIN_RX12 = 21, /* Digital Active - lin[0].lin_rx[12]:1 */ 3167 3168 /* P18.0 */ 3169 P18_0_GPIO = 0, /* GPIO controls 'out' */ 3170 P18_0_AMUXA = 4, /* Analog mux bus A */ 3171 P18_0_AMUXB = 5, /* Analog mux bus B */ 3172 P18_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3173 P18_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3174 P18_0_TCPWM1_LINE262 = 8, /* Digital Active - tcpwm[1].line[262]:1 */ 3175 P18_0_TCPWM1_LINE_COMPL261 = 9, /* Digital Active - tcpwm[1].line_compl[261]:1 */ 3176 P18_0_TCPWM1_TR_ONE_CNT_IN786 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[786]:1 */ 3177 P18_0_TCPWM1_TR_ONE_CNT_IN784 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[784]:1 */ 3178 P18_0_TCPWM1_LINE512 = 16, /* Digital Active - tcpwm[1].line[512]:0 */ 3179 P18_0_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:0 */ 3180 P18_0_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:0 */ 3181 P18_0_LIN0_LIN_TX12 = 21, /* Digital Active - lin[0].lin_tx[12]:1 */ 3182 P18_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:0 */ 3183 P18_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 3184 3185 /* P18.1 */ 3186 P18_1_GPIO = 0, /* GPIO controls 'out' */ 3187 P18_1_AMUXA = 4, /* Analog mux bus A */ 3188 P18_1_AMUXB = 5, /* Analog mux bus B */ 3189 P18_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3190 P18_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3191 P18_1_TCPWM1_LINE263 = 8, /* Digital Active - tcpwm[1].line[263]:1 */ 3192 P18_1_TCPWM1_LINE_COMPL262 = 9, /* Digital Active - tcpwm[1].line_compl[262]:1 */ 3193 P18_1_TCPWM1_TR_ONE_CNT_IN789 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[789]:1 */ 3194 P18_1_TCPWM1_TR_ONE_CNT_IN787 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[787]:1 */ 3195 P18_1_TCPWM1_LINE_COMPL512 = 16, /* Digital Active - tcpwm[1].line_compl[512]:0 */ 3196 P18_1_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:0 */ 3197 P18_1_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:0 */ 3198 P18_1_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:0 */ 3199 P18_1_SCB3_SPI_MISO = 21, /* Digital Active - scb[3].spi_miso:1 */ 3200 P18_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:0 */ 3201 P18_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 3202 3203 /* P18.2 */ 3204 P18_2_GPIO = 0, /* GPIO controls 'out' */ 3205 P18_2_AMUXA = 4, /* Analog mux bus A */ 3206 P18_2_AMUXB = 5, /* Analog mux bus B */ 3207 P18_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3208 P18_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3209 P18_2_TCPWM1_LINE55 = 8, /* Digital Active - tcpwm[1].line[55]:1 */ 3210 P18_2_TCPWM1_LINE_COMPL263 = 9, /* Digital Active - tcpwm[1].line_compl[263]:1 */ 3211 P18_2_TCPWM1_TR_ONE_CNT_IN165 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[165]:1 */ 3212 P18_2_TCPWM1_TR_ONE_CNT_IN790 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[790]:1 */ 3213 P18_2_TCPWM1_LINE513 = 16, /* Digital Active - tcpwm[1].line[513]:0 */ 3214 P18_2_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:0 */ 3215 P18_2_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:0 */ 3216 P18_2_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:0 */ 3217 P18_2_SCB3_SPI_MOSI = 21, /* Digital Active - scb[3].spi_mosi:1 */ 3218 P18_2_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er:0 */ 3219 3220 /* P18.3 */ 3221 P18_3_GPIO = 0, /* GPIO controls 'out' */ 3222 P18_3_AMUXA = 4, /* Analog mux bus A */ 3223 P18_3_AMUXB = 5, /* Analog mux bus B */ 3224 P18_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3225 P18_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3226 P18_3_TCPWM1_LINE54 = 8, /* Digital Active - tcpwm[1].line[54]:1 */ 3227 P18_3_TCPWM1_LINE_COMPL55 = 9, /* Digital Active - tcpwm[1].line_compl[55]:1 */ 3228 P18_3_TCPWM1_TR_ONE_CNT_IN162 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[162]:1 */ 3229 P18_3_TCPWM1_TR_ONE_CNT_IN166 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[166]:1 */ 3230 P18_3_TCPWM1_LINE_COMPL513 = 16, /* Digital Active - tcpwm[1].line_compl[513]:0 */ 3231 P18_3_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:0 */ 3232 P18_3_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:0 */ 3233 P18_3_SCB3_SPI_CLK = 21, /* Digital Active - scb[3].spi_clk:2 */ 3234 P18_3_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:0 */ 3235 P18_3_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:0 */ 3236 3237 /* P18.4 */ 3238 P18_4_GPIO = 0, /* GPIO controls 'out' */ 3239 P18_4_AMUXA = 4, /* Analog mux bus A */ 3240 P18_4_AMUXB = 5, /* Analog mux bus B */ 3241 P18_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3242 P18_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3243 P18_4_TCPWM1_LINE53 = 8, /* Digital Active - tcpwm[1].line[53]:1 */ 3244 P18_4_TCPWM1_LINE_COMPL54 = 9, /* Digital Active - tcpwm[1].line_compl[54]:1 */ 3245 P18_4_TCPWM1_TR_ONE_CNT_IN159 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[159]:1 */ 3246 P18_4_TCPWM1_TR_ONE_CNT_IN163 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[163]:1 */ 3247 P18_4_TCPWM1_LINE514 = 16, /* Digital Active - tcpwm[1].line[514]:0 */ 3248 P18_4_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:0 */ 3249 P18_4_SCB3_SPI_SELECT0 = 21, /* Digital Active - scb[3].spi_select0:2 */ 3250 P18_4_TCPWM0_LINE258 = 22, /* Digital Active - tcpwm[0].line[258] */ 3251 P18_4_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:0 */ 3252 P18_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 3253 3254 /* P18.5 */ 3255 P18_5_GPIO = 0, /* GPIO controls 'out' */ 3256 P18_5_AMUXA = 4, /* Analog mux bus A */ 3257 P18_5_AMUXB = 5, /* Analog mux bus B */ 3258 P18_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3259 P18_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3260 P18_5_TCPWM1_LINE52 = 8, /* Digital Active - tcpwm[1].line[52]:1 */ 3261 P18_5_TCPWM1_LINE_COMPL53 = 9, /* Digital Active - tcpwm[1].line_compl[53]:1 */ 3262 P18_5_TCPWM1_TR_ONE_CNT_IN156 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[156]:1 */ 3263 P18_5_TCPWM1_TR_ONE_CNT_IN160 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[160]:1 */ 3264 P18_5_TCPWM1_LINE_COMPL514 = 16, /* Digital Active - tcpwm[1].line_compl[514]:0 */ 3265 P18_5_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:0 */ 3266 P18_5_TCPWM0_LINE_COMPL258 = 22, /* Digital Active - tcpwm[0].line_compl[258] */ 3267 P18_5_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:0 */ 3268 P18_5_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 3269 3270 /* P18.6 */ 3271 P18_6_GPIO = 0, /* GPIO controls 'out' */ 3272 P18_6_AMUXA = 4, /* Analog mux bus A */ 3273 P18_6_AMUXB = 5, /* Analog mux bus B */ 3274 P18_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3275 P18_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3276 P18_6_TCPWM1_LINE51 = 8, /* Digital Active - tcpwm[1].line[51]:1 */ 3277 P18_6_TCPWM1_LINE_COMPL52 = 9, /* Digital Active - tcpwm[1].line_compl[52]:1 */ 3278 P18_6_TCPWM1_TR_ONE_CNT_IN153 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[153]:1 */ 3279 P18_6_TCPWM1_TR_ONE_CNT_IN157 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[157]:1 */ 3280 P18_6_TCPWM1_LINE515 = 16, /* Digital Active - tcpwm[1].line[515]:0 */ 3281 P18_6_SCB1_SPI_SELECT3 = 19, /* Digital Active - scb[1].spi_select3:0 */ 3282 P18_6_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:0 */ 3283 P18_6_TCPWM0_TR_ONE_CNT_IN774 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[774] */ 3284 P18_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:0 */ 3285 P18_6_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 3286 3287 /* P18.7 */ 3288 P18_7_GPIO = 0, /* GPIO controls 'out' */ 3289 P18_7_AMUXA = 4, /* Analog mux bus A */ 3290 P18_7_AMUXB = 5, /* Analog mux bus B */ 3291 P18_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3292 P18_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3293 P18_7_TCPWM1_LINE50 = 8, /* Digital Active - tcpwm[1].line[50]:1 */ 3294 P18_7_TCPWM1_LINE_COMPL51 = 9, /* Digital Active - tcpwm[1].line_compl[51]:1 */ 3295 P18_7_TCPWM1_TR_ONE_CNT_IN150 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[150]:1 */ 3296 P18_7_TCPWM1_TR_ONE_CNT_IN154 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[154]:1 */ 3297 P18_7_TCPWM1_LINE_COMPL515 = 16, /* Digital Active - tcpwm[1].line_compl[515]:0 */ 3298 P18_7_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:0 */ 3299 P18_7_TCPWM0_TR_ONE_CNT_IN775 = 22, /* Digital Active - tcpwm[0].tr_one_cnt_in[775] */ 3300 P18_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:0 */ 3301 P18_7_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 3302 3303 /* P19.0 */ 3304 P19_0_GPIO = 0, /* GPIO controls 'out' */ 3305 P19_0_AMUXA = 4, /* Analog mux bus A */ 3306 P19_0_AMUXB = 5, /* Analog mux bus B */ 3307 P19_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3308 P19_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3309 P19_0_TCPWM1_LINE259 = 8, /* Digital Active - tcpwm[1].line[259]:2 */ 3310 P19_0_TCPWM1_LINE_COMPL50 = 9, /* Digital Active - tcpwm[1].line_compl[50]:1 */ 3311 P19_0_TCPWM1_TR_ONE_CNT_IN777 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[777]:2 */ 3312 P19_0_TCPWM1_TR_ONE_CNT_IN151 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[151]:1 */ 3313 P19_0_TCPWM1_TR_ONE_CNT_IN1536 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1536]:0 */ 3314 P19_0_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:1 */ 3315 P19_0_SCB2_UART_RX = 19, /* Digital Active - scb[2].uart_rx:1 */ 3316 P19_0_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:0 */ 3317 P19_0_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:0 */ 3318 P19_0_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 3319 3320 /* P19.1 */ 3321 P19_1_GPIO = 0, /* GPIO controls 'out' */ 3322 P19_1_AMUXA = 4, /* Analog mux bus A */ 3323 P19_1_AMUXB = 5, /* Analog mux bus B */ 3324 P19_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3325 P19_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3326 P19_1_TCPWM1_LINE26 = 8, /* Digital Active - tcpwm[1].line[26]:1 */ 3327 P19_1_TCPWM1_LINE_COMPL259 = 9, /* Digital Active - tcpwm[1].line_compl[259]:2 */ 3328 P19_1_TCPWM1_TR_ONE_CNT_IN78 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[78]:1 */ 3329 P19_1_TCPWM1_TR_ONE_CNT_IN778 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[778]:2 */ 3330 P19_1_TCPWM1_TR_ONE_CNT_IN1537 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1537]:0 */ 3331 P19_1_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:1 */ 3332 P19_1_SCB2_I2C_SDA = 18, /* Digital Active - scb[2].i2c_sda:1 */ 3333 P19_1_SCB2_UART_TX = 19, /* Digital Active - scb[2].uart_tx:1 */ 3334 P19_1_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:0 */ 3335 P19_1_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:0 */ 3336 P19_1_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 3337 3338 /* P19.2 */ 3339 P19_2_GPIO = 0, /* GPIO controls 'out' */ 3340 P19_2_AMUXA = 4, /* Analog mux bus A */ 3341 P19_2_AMUXB = 5, /* Analog mux bus B */ 3342 P19_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3343 P19_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3344 P19_2_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:2 */ 3345 P19_2_TCPWM1_LINE_COMPL26 = 9, /* Digital Active - tcpwm[1].line_compl[26]:1 */ 3346 P19_2_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:2 */ 3347 P19_2_TCPWM1_TR_ONE_CNT_IN79 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[79]:1 */ 3348 P19_2_TCPWM1_TR_ONE_CNT_IN1539 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1539]:0 */ 3349 P19_2_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:1 */ 3350 P19_2_SCB2_I2C_SCL = 18, /* Digital Active - scb[2].i2c_scl:1 */ 3351 P19_2_SCB2_UART_RTS = 19, /* Digital Active - scb[2].uart_rts:1 */ 3352 P19_2_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:0 */ 3353 P19_2_PERI_TR_IO_INPUT28 = 26, /* Digital Active - peri.tr_io_input[28]:0 */ 3354 3355 /* P19.3 */ 3356 P19_3_GPIO = 0, /* GPIO controls 'out' */ 3357 P19_3_AMUXA = 4, /* Analog mux bus A */ 3358 P19_3_AMUXB = 5, /* Analog mux bus B */ 3359 P19_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3360 P19_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3361 P19_3_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:2 */ 3362 P19_3_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:2 */ 3363 P19_3_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:2 */ 3364 P19_3_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:2 */ 3365 P19_3_TCPWM1_TR_ONE_CNT_IN1540 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1540]:0 */ 3366 P19_3_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:1 */ 3367 P19_3_SCB2_UART_CTS = 19, /* Digital Active - scb[2].uart_cts:1 */ 3368 P19_3_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:0 */ 3369 P19_3_PERI_TR_IO_INPUT29 = 26, /* Digital Active - peri.tr_io_input[29]:0 */ 3370 3371 /* P19.4 */ 3372 P19_4_GPIO = 0, /* GPIO controls 'out' */ 3373 P19_4_AMUXA = 4, /* Analog mux bus A */ 3374 P19_4_AMUXB = 5, /* Analog mux bus B */ 3375 P19_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3376 P19_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3377 P19_4_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:2 */ 3378 P19_4_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:2 */ 3379 P19_4_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:2 */ 3380 P19_4_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:2 */ 3381 P19_4_TCPWM1_TR_ONE_CNT_IN1542 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1542]:0 */ 3382 P19_4_SCB2_SPI_SELECT1 = 17, /* Digital Active - scb[2].spi_select1:1 */ 3383 3384 /* P20.0 */ 3385 P20_0_GPIO = 0, /* GPIO controls 'out' */ 3386 P20_0_AMUXA = 4, /* Analog mux bus A */ 3387 P20_0_AMUXB = 5, /* Analog mux bus B */ 3388 P20_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3389 P20_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3390 P20_0_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:2 */ 3391 P20_0_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:2 */ 3392 P20_0_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:2 */ 3393 P20_0_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:2 */ 3394 P20_0_TCPWM1_TR_ONE_CNT_IN1543 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1543]:0 */ 3395 P20_0_SCB2_SPI_SELECT2 = 17, /* Digital Active - scb[2].spi_select2:1 */ 3396 P20_0_LIN0_LIN_RX5 = 20, /* Digital Active - lin[0].lin_rx[5]:0 */ 3397 3398 /* P20.1 */ 3399 P20_1_GPIO = 0, /* GPIO controls 'out' */ 3400 P20_1_AMUXA = 4, /* Analog mux bus A */ 3401 P20_1_AMUXB = 5, /* Analog mux bus B */ 3402 P20_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3403 P20_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3404 P20_1_TCPWM1_LINE49 = 8, /* Digital Active - tcpwm[1].line[49]:1 */ 3405 P20_1_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:2 */ 3406 P20_1_TCPWM1_TR_ONE_CNT_IN147 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[147]:1 */ 3407 P20_1_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:2 */ 3408 P20_1_TCPWM1_TR_ONE_CNT_IN1545 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1545]:0 */ 3409 P20_1_LIN0_LIN_TX5 = 20, /* Digital Active - lin[0].lin_tx[5]:0 */ 3410 3411 /* P20.2 */ 3412 P20_2_GPIO = 0, /* GPIO controls 'out' */ 3413 P20_2_AMUXA = 4, /* Analog mux bus A */ 3414 P20_2_AMUXB = 5, /* Analog mux bus B */ 3415 P20_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3416 P20_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3417 P20_2_TCPWM1_LINE48 = 8, /* Digital Active - tcpwm[1].line[48]:1 */ 3418 P20_2_TCPWM1_LINE_COMPL49 = 9, /* Digital Active - tcpwm[1].line_compl[49]:1 */ 3419 P20_2_TCPWM1_TR_ONE_CNT_IN144 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[144]:1 */ 3420 P20_2_TCPWM1_TR_ONE_CNT_IN148 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[148]:1 */ 3421 P20_2_TCPWM1_TR_ONE_CNT_IN1546 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1546]:0 */ 3422 P20_2_LIN0_LIN_EN5 = 20, /* Digital Active - lin[0].lin_en[5]:0 */ 3423 3424 /* P20.3 */ 3425 P20_3_GPIO = 0, /* GPIO controls 'out' */ 3426 P20_3_AMUXA = 4, /* Analog mux bus A */ 3427 P20_3_AMUXB = 5, /* Analog mux bus B */ 3428 P20_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3429 P20_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3430 P20_3_TCPWM1_LINE47 = 8, /* Digital Active - tcpwm[1].line[47]:1 */ 3431 P20_3_TCPWM1_LINE_COMPL48 = 9, /* Digital Active - tcpwm[1].line_compl[48]:1 */ 3432 P20_3_TCPWM1_TR_ONE_CNT_IN141 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[141]:1 */ 3433 P20_3_TCPWM1_TR_ONE_CNT_IN145 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[145]:1 */ 3434 P20_3_SCB1_UART_RX = 17, /* Digital Active - scb[1].uart_rx:1 */ 3435 P20_3_SCB1_SPI_MISO = 19, /* Digital Active - scb[1].spi_miso:1 */ 3436 P20_3_CANFD1_TTCAN_TX2 = 21, /* Digital Active - canfd[1].ttcan_tx[2]:1 */ 3437 3438 /* P20.4 */ 3439 P20_4_GPIO = 0, /* GPIO controls 'out' */ 3440 P20_4_AMUXA = 4, /* Analog mux bus A */ 3441 P20_4_AMUXB = 5, /* Analog mux bus B */ 3442 P20_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3443 P20_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3444 P20_4_TCPWM1_LINE46 = 8, /* Digital Active - tcpwm[1].line[46]:1 */ 3445 P20_4_TCPWM1_LINE_COMPL47 = 9, /* Digital Active - tcpwm[1].line_compl[47]:1 */ 3446 P20_4_TCPWM1_TR_ONE_CNT_IN138 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[138]:1 */ 3447 P20_4_TCPWM1_TR_ONE_CNT_IN142 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[142]:1 */ 3448 P20_4_SCB1_UART_TX = 17, /* Digital Active - scb[1].uart_tx:1 */ 3449 P20_4_SCB1_I2C_SDA = 18, /* Digital Active - scb[1].i2c_sda:1 */ 3450 P20_4_SCB1_SPI_MOSI = 19, /* Digital Active - scb[1].spi_mosi:1 */ 3451 P20_4_CANFD1_TTCAN_RX2 = 21, /* Digital Active - canfd[1].ttcan_rx[2]:1 */ 3452 3453 /* P20.5 */ 3454 P20_5_GPIO = 0, /* GPIO controls 'out' */ 3455 P20_5_AMUXA = 4, /* Analog mux bus A */ 3456 P20_5_AMUXB = 5, /* Analog mux bus B */ 3457 P20_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3458 P20_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3459 P20_5_TCPWM1_LINE45 = 8, /* Digital Active - tcpwm[1].line[45]:1 */ 3460 P20_5_TCPWM1_LINE_COMPL46 = 9, /* Digital Active - tcpwm[1].line_compl[46]:1 */ 3461 P20_5_TCPWM1_TR_ONE_CNT_IN135 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[135]:1 */ 3462 P20_5_TCPWM1_TR_ONE_CNT_IN139 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[139]:1 */ 3463 P20_5_SCB1_UART_RTS = 17, /* Digital Active - scb[1].uart_rts:1 */ 3464 P20_5_SCB1_I2C_SCL = 18, /* Digital Active - scb[1].i2c_scl:1 */ 3465 P20_5_SCB1_SPI_CLK = 19, /* Digital Active - scb[1].spi_clk:1 */ 3466 3467 /* P20.6 */ 3468 P20_6_GPIO = 0, /* GPIO controls 'out' */ 3469 P20_6_AMUXA = 4, /* Analog mux bus A */ 3470 P20_6_AMUXB = 5, /* Analog mux bus B */ 3471 P20_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3472 P20_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3473 P20_6_TCPWM1_LINE44 = 8, /* Digital Active - tcpwm[1].line[44]:1 */ 3474 P20_6_TCPWM1_LINE_COMPL45 = 9, /* Digital Active - tcpwm[1].line_compl[45]:1 */ 3475 P20_6_TCPWM1_TR_ONE_CNT_IN132 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[132]:1 */ 3476 P20_6_TCPWM1_TR_ONE_CNT_IN136 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[136]:1 */ 3477 P20_6_SCB1_UART_CTS = 17, /* Digital Active - scb[1].uart_cts:1 */ 3478 P20_6_SCB1_SPI_SELECT0 = 19, /* Digital Active - scb[1].spi_select0:1 */ 3479 P20_6_CANFD1_TTCAN_TX4 = 21, /* Digital Active - canfd[1].ttcan_tx[4]:0 */ 3480 3481 /* P20.7 */ 3482 P20_7_GPIO = 0, /* GPIO controls 'out' */ 3483 P20_7_AMUXA = 4, /* Analog mux bus A */ 3484 P20_7_AMUXB = 5, /* Analog mux bus B */ 3485 P20_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3486 P20_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3487 P20_7_TCPWM1_LINE43 = 8, /* Digital Active - tcpwm[1].line[43]:1 */ 3488 P20_7_TCPWM1_LINE_COMPL44 = 9, /* Digital Active - tcpwm[1].line_compl[44]:1 */ 3489 P20_7_TCPWM1_TR_ONE_CNT_IN129 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[129]:1 */ 3490 P20_7_TCPWM1_TR_ONE_CNT_IN133 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[133]:1 */ 3491 P20_7_SCB1_SPI_SELECT1 = 19, /* Digital Active - scb[1].spi_select1:1 */ 3492 P20_7_CANFD1_TTCAN_RX4 = 21, /* Digital Active - canfd[1].ttcan_rx[4]:0 */ 3493 3494 /* P21.0 */ 3495 P21_0_GPIO = 0, /* GPIO controls 'out' */ 3496 P21_0_AMUXA = 4, /* Analog mux bus A */ 3497 P21_0_AMUXB = 5, /* Analog mux bus B */ 3498 P21_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3499 P21_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3500 P21_0_TCPWM1_LINE42 = 8, /* Digital Active - tcpwm[1].line[42]:1 */ 3501 P21_0_TCPWM1_LINE_COMPL43 = 9, /* Digital Active - tcpwm[1].line_compl[43]:1 */ 3502 P21_0_TCPWM1_TR_ONE_CNT_IN126 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[126]:1 */ 3503 P21_0_TCPWM1_TR_ONE_CNT_IN130 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[130]:1 */ 3504 P21_0_SCB1_SPI_SELECT2 = 19, /* Digital Active - scb[1].spi_select2:1 */ 3505 3506 /* P21.1 */ 3507 P21_1_GPIO = 0, /* GPIO controls 'out' */ 3508 P21_1_AMUXA = 4, /* Analog mux bus A */ 3509 P21_1_AMUXB = 5, /* Analog mux bus B */ 3510 P21_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3511 P21_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3512 P21_1_TCPWM1_LINE41 = 8, /* Digital Active - tcpwm[1].line[41]:1 */ 3513 P21_1_TCPWM1_LINE_COMPL42 = 9, /* Digital Active - tcpwm[1].line_compl[42]:1 */ 3514 P21_1_TCPWM1_TR_ONE_CNT_IN123 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[123]:1 */ 3515 P21_1_TCPWM1_TR_ONE_CNT_IN127 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[127]:1 */ 3516 3517 /* P21.2 */ 3518 P21_2_GPIO = 0, /* GPIO controls 'out' */ 3519 P21_2_AMUXA = 4, /* Analog mux bus A */ 3520 P21_2_AMUXB = 5, /* Analog mux bus B */ 3521 P21_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3522 P21_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3523 P21_2_TCPWM1_LINE40 = 8, /* Digital Active - tcpwm[1].line[40]:1 */ 3524 P21_2_TCPWM1_LINE_COMPL41 = 9, /* Digital Active - tcpwm[1].line_compl[41]:1 */ 3525 P21_2_TCPWM1_TR_ONE_CNT_IN120 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[120]:1 */ 3526 P21_2_TCPWM1_TR_ONE_CNT_IN124 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[124]:1 */ 3527 P21_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 3528 P21_2_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:2 */ 3529 P21_2_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 3530 3531 /* P21.3 */ 3532 P21_3_GPIO = 0, /* GPIO controls 'out' */ 3533 P21_3_AMUXA = 4, /* Analog mux bus A */ 3534 P21_3_AMUXB = 5, /* Analog mux bus B */ 3535 P21_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3536 P21_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3537 P21_3_TCPWM1_LINE39 = 8, /* Digital Active - tcpwm[1].line[39]:1 */ 3538 P21_3_TCPWM1_LINE_COMPL40 = 9, /* Digital Active - tcpwm[1].line_compl[40]:1 */ 3539 P21_3_TCPWM1_TR_ONE_CNT_IN117 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[117]:1 */ 3540 P21_3_TCPWM1_TR_ONE_CNT_IN121 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[121]:1 */ 3541 3542 /* P21.4 */ 3543 P21_4_GPIO = 0, /* GPIO controls 'out' */ 3544 P21_4_AMUXA = 4, /* Analog mux bus A */ 3545 P21_4_AMUXB = 5, /* Analog mux bus B */ 3546 P21_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3547 P21_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3548 P21_4_TCPWM1_LINE38 = 8, /* Digital Active - tcpwm[1].line[38]:1 */ 3549 P21_4_TCPWM1_LINE_COMPL39 = 9, /* Digital Active - tcpwm[1].line_compl[39]:1 */ 3550 P21_4_TCPWM1_TR_ONE_CNT_IN114 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[114]:1 */ 3551 P21_4_TCPWM1_TR_ONE_CNT_IN118 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[118]:1 */ 3552 3553 /* P21.5 */ 3554 P21_5_GPIO = 0, /* GPIO controls 'out' */ 3555 P21_5_AMUXA = 4, /* Analog mux bus A */ 3556 P21_5_AMUXB = 5, /* Analog mux bus B */ 3557 P21_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3558 P21_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3559 P21_5_TCPWM1_LINE37 = 8, /* Digital Active - tcpwm[1].line[37]:1 */ 3560 P21_5_TCPWM1_LINE_COMPL38 = 9, /* Digital Active - tcpwm[1].line_compl[38]:1 */ 3561 P21_5_TCPWM1_TR_ONE_CNT_IN111 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[111]:1 */ 3562 P21_5_TCPWM1_TR_ONE_CNT_IN115 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[115]:1 */ 3563 P21_5_TCPWM1_TR_ONE_CNT_IN106 = 18, /* Digital Active - tcpwm[1].tr_one_cnt_in[106]:1 */ 3564 P21_5_TCPWM1_TR_ONE_CNT_IN102 = 19, /* Digital Active - tcpwm[1].tr_one_cnt_in[102]:1 */ 3565 P21_5_LIN0_LIN_RX0 = 20, /* Digital Active - lin[0].lin_rx[0]:1 */ 3566 P21_5_CANFD1_TTCAN_TX1 = 21, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 3567 P21_5_TCPWM1_LINE34 = 22, /* Digital Active - tcpwm[1].line[34]:1 */ 3568 P21_5_TCPWM1_LINE_COMPL35 = 23, /* Digital Active - tcpwm[1].line_compl[35]:1 */ 3569 P21_5_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:0 */ 3570 P21_5_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 3571 3572 /* P21.6 */ 3573 P21_6_GPIO = 0, /* GPIO controls 'out' */ 3574 P21_6_AMUXA = 4, /* Analog mux bus A */ 3575 P21_6_AMUXB = 5, /* Analog mux bus B */ 3576 P21_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3577 P21_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3578 P21_6_TCPWM1_LINE36 = 8, /* Digital Active - tcpwm[1].line[36]:1 */ 3579 P21_6_TCPWM1_LINE_COMPL37 = 9, /* Digital Active - tcpwm[1].line_compl[37]:1 */ 3580 P21_6_TCPWM1_TR_ONE_CNT_IN108 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[108]:1 */ 3581 P21_6_TCPWM1_TR_ONE_CNT_IN112 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[112]:1 */ 3582 P21_6_LIN0_LIN_TX0 = 20, /* Digital Active - lin[0].lin_tx[0]:1 */ 3583 P21_6_LIN0_LIN_RX13 = 21, /* Digital Active - lin[0].lin_rx[13]:1 */ 3584 P21_6_CPUSS_CLK_FM_PUMP = 26, /* Digital Active - cpuss.clk_fm_pump */ 3585 3586 /* P21.7 */ 3587 P21_7_GPIO = 0, /* GPIO controls 'out' */ 3588 P21_7_AMUXA = 4, /* Analog mux bus A */ 3589 P21_7_AMUXB = 5, /* Analog mux bus B */ 3590 P21_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3591 P21_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3592 P21_7_TCPWM1_LINE35 = 8, /* Digital Active - tcpwm[1].line[35]:1 */ 3593 P21_7_TCPWM1_LINE_COMPL36 = 9, /* Digital Active - tcpwm[1].line_compl[36]:1 */ 3594 P21_7_TCPWM1_TR_ONE_CNT_IN105 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[105]:1 */ 3595 P21_7_TCPWM1_TR_ONE_CNT_IN109 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[109]:1 */ 3596 P21_7_SCB6_UART_RX = 17, /* Digital Active - scb[6].uart_rx:1 */ 3597 P21_7_SCB6_SPI_MISO = 19, /* Digital Active - scb[6].spi_miso:1 */ 3598 P21_7_LIN0_LIN_EN0 = 20, /* Digital Active - lin[0].lin_en[0]:1 */ 3599 P21_7_LIN0_LIN_TX13 = 21, /* Digital Active - lin[0].lin_tx[13]:1 */ 3600 P21_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 3601 P21_7_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 3602 3603 /* P22.1 */ 3604 P22_1_GPIO = 0, /* GPIO controls 'out' */ 3605 P22_1_AMUXA = 4, /* Analog mux bus A */ 3606 P22_1_AMUXB = 5, /* Analog mux bus B */ 3607 P22_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3608 P22_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3609 P22_1_TCPWM1_LINE33 = 8, /* Digital Active - tcpwm[1].line[33]:1 */ 3610 P22_1_TCPWM1_LINE_COMPL34 = 9, /* Digital Active - tcpwm[1].line_compl[34]:1 */ 3611 P22_1_TCPWM1_TR_ONE_CNT_IN99 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[99]:1 */ 3612 P22_1_TCPWM1_TR_ONE_CNT_IN103 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[103]:1 */ 3613 P22_1_SCB6_UART_TX = 17, /* Digital Active - scb[6].uart_tx:1 */ 3614 P22_1_SCB6_I2C_SDA = 18, /* Digital Active - scb[6].i2c_sda:1 */ 3615 P22_1_SCB6_SPI_MOSI = 19, /* Digital Active - scb[6].spi_mosi:1 */ 3616 P22_1_CANFD1_TTCAN_RX1 = 21, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 3617 P22_1_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 3618 3619 /* P22.2 */ 3620 P22_2_GPIO = 0, /* GPIO controls 'out' */ 3621 P22_2_AMUXA = 4, /* Analog mux bus A */ 3622 P22_2_AMUXB = 5, /* Analog mux bus B */ 3623 P22_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3624 P22_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3625 P22_2_TCPWM1_LINE32 = 8, /* Digital Active - tcpwm[1].line[32]:1 */ 3626 P22_2_TCPWM1_LINE_COMPL33 = 9, /* Digital Active - tcpwm[1].line_compl[33]:1 */ 3627 P22_2_TCPWM1_TR_ONE_CNT_IN96 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[96]:1 */ 3628 P22_2_TCPWM1_TR_ONE_CNT_IN100 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[100]:1 */ 3629 P22_2_SCB6_UART_RTS = 17, /* Digital Active - scb[6].uart_rts:1 */ 3630 P22_2_SCB6_I2C_SCL = 18, /* Digital Active - scb[6].i2c_scl:1 */ 3631 P22_2_SCB6_SPI_CLK = 19, /* Digital Active - scb[6].spi_clk:1 */ 3632 P22_2_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 3633 3634 /* P22.3 */ 3635 P22_3_GPIO = 0, /* GPIO controls 'out' */ 3636 P22_3_AMUXA = 4, /* Analog mux bus A */ 3637 P22_3_AMUXB = 5, /* Analog mux bus B */ 3638 P22_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3639 P22_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3640 P22_3_TCPWM1_LINE31 = 8, /* Digital Active - tcpwm[1].line[31]:1 */ 3641 P22_3_TCPWM1_LINE_COMPL32 = 9, /* Digital Active - tcpwm[1].line_compl[32]:1 */ 3642 P22_3_TCPWM1_TR_ONE_CNT_IN93 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[93]:1 */ 3643 P22_3_TCPWM1_TR_ONE_CNT_IN97 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[97]:1 */ 3644 P22_3_SCB6_UART_CTS = 17, /* Digital Active - scb[6].uart_cts:1 */ 3645 P22_3_SCB6_SPI_SELECT0 = 19, /* Digital Active - scb[6].spi_select0:1 */ 3646 P22_3_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 3647 3648 /* P22.4 */ 3649 P22_4_GPIO = 0, /* GPIO controls 'out' */ 3650 P22_4_AMUXA = 4, /* Analog mux bus A */ 3651 P22_4_AMUXB = 5, /* Analog mux bus B */ 3652 P22_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3653 P22_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3654 P22_4_TCPWM1_LINE30 = 8, /* Digital Active - tcpwm[1].line[30]:1 */ 3655 P22_4_TCPWM1_LINE_COMPL31 = 9, /* Digital Active - tcpwm[1].line_compl[31]:1 */ 3656 P22_4_TCPWM1_TR_ONE_CNT_IN90 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[90]:1 */ 3657 P22_4_TCPWM1_TR_ONE_CNT_IN94 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[94]:1 */ 3658 P22_4_SCB6_SPI_SELECT1 = 19, /* Digital Active - scb[6].spi_select1:1 */ 3659 P22_4_CPUSS_TRACE_CLOCK = 27, /* Digital Active - cpuss.trace_clock:1 */ 3660 3661 /* P22.5 */ 3662 P22_5_GPIO = 0, /* GPIO controls 'out' */ 3663 P22_5_AMUXA = 4, /* Analog mux bus A */ 3664 P22_5_AMUXB = 5, /* Analog mux bus B */ 3665 P22_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3666 P22_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3667 P22_5_TCPWM1_LINE29 = 8, /* Digital Active - tcpwm[1].line[29]:1 */ 3668 P22_5_TCPWM1_LINE_COMPL30 = 9, /* Digital Active - tcpwm[1].line_compl[30]:1 */ 3669 P22_5_TCPWM1_TR_ONE_CNT_IN87 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[87]:1 */ 3670 P22_5_TCPWM1_TR_ONE_CNT_IN91 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[91]:1 */ 3671 P22_5_TCPWM1_LINE520 = 16, /* Digital Active - tcpwm[1].line[520]:0 */ 3672 P22_5_SCB6_SPI_SELECT2 = 19, /* Digital Active - scb[6].spi_select2:1 */ 3673 P22_5_LIN0_LIN_RX7 = 20, /* Digital Active - lin[0].lin_rx[7]:1 */ 3674 3675 /* P22.6 */ 3676 P22_6_GPIO = 0, /* GPIO controls 'out' */ 3677 P22_6_AMUXA = 4, /* Analog mux bus A */ 3678 P22_6_AMUXB = 5, /* Analog mux bus B */ 3679 P22_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3680 P22_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3681 P22_6_TCPWM1_LINE28 = 8, /* Digital Active - tcpwm[1].line[28]:1 */ 3682 P22_6_TCPWM1_LINE_COMPL29 = 9, /* Digital Active - tcpwm[1].line_compl[29]:1 */ 3683 P22_6_TCPWM1_TR_ONE_CNT_IN84 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[84]:1 */ 3684 P22_6_TCPWM1_TR_ONE_CNT_IN88 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[88]:1 */ 3685 P22_6_TCPWM1_LINE_COMPL520 = 16, /* Digital Active - tcpwm[1].line_compl[520]:0 */ 3686 P22_6_LIN0_LIN_TX7 = 20, /* Digital Active - lin[0].lin_tx[7]:1 */ 3687 3688 /* P22.7 */ 3689 P22_7_GPIO = 0, /* GPIO controls 'out' */ 3690 P22_7_AMUXA = 4, /* Analog mux bus A */ 3691 P22_7_AMUXB = 5, /* Analog mux bus B */ 3692 P22_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3693 P22_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3694 P22_7_TCPWM1_LINE27 = 8, /* Digital Active - tcpwm[1].line[27]:1 */ 3695 P22_7_TCPWM1_LINE_COMPL28 = 9, /* Digital Active - tcpwm[1].line_compl[28]:1 */ 3696 P22_7_TCPWM1_TR_ONE_CNT_IN81 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[81]:1 */ 3697 P22_7_TCPWM1_TR_ONE_CNT_IN85 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[85]:1 */ 3698 P22_7_TCPWM1_TR_ONE_CNT_IN1560 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1560]:0 */ 3699 P22_7_LIN0_LIN_RX14 = 18, /* Digital Active - lin[0].lin_rx[14]:1 */ 3700 P22_7_LIN0_LIN_EN7 = 20, /* Digital Active - lin[0].lin_en[7]:1 */ 3701 3702 /* P23.0 */ 3703 P23_0_GPIO = 0, /* GPIO controls 'out' */ 3704 P23_0_AMUXA = 4, /* Analog mux bus A */ 3705 P23_0_AMUXB = 5, /* Analog mux bus B */ 3706 P23_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3707 P23_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3708 P23_0_TCPWM1_LINE264 = 8, /* Digital Active - tcpwm[1].line[264]:1 */ 3709 P23_0_TCPWM1_LINE_COMPL27 = 9, /* Digital Active - tcpwm[1].line_compl[27]:1 */ 3710 P23_0_TCPWM1_TR_ONE_CNT_IN792 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[792]:1 */ 3711 P23_0_TCPWM1_TR_ONE_CNT_IN82 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[82]:1 */ 3712 P23_0_TCPWM1_TR_ONE_CNT_IN1561 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1561]:0 */ 3713 P23_0_SCB7_UART_RX = 17, /* Digital Active - scb[7].uart_rx:1 */ 3714 P23_0_LIN0_LIN_TX14 = 18, /* Digital Active - lin[0].lin_tx[14]:1 */ 3715 P23_0_SCB7_SPI_MISO = 19, /* Digital Active - scb[7].spi_miso:1 */ 3716 P23_0_CANFD1_TTCAN_TX0 = 21, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 3717 P23_0_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 3718 3719 /* P23.1 */ 3720 P23_1_GPIO = 0, /* GPIO controls 'out' */ 3721 P23_1_AMUXA = 4, /* Analog mux bus A */ 3722 P23_1_AMUXB = 5, /* Analog mux bus B */ 3723 P23_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3724 P23_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3725 P23_1_TCPWM1_LINE265 = 8, /* Digital Active - tcpwm[1].line[265]:1 */ 3726 P23_1_TCPWM1_LINE_COMPL264 = 9, /* Digital Active - tcpwm[1].line_compl[264]:1 */ 3727 P23_1_TCPWM1_TR_ONE_CNT_IN795 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[795]:1 */ 3728 P23_1_TCPWM1_TR_ONE_CNT_IN793 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[793]:1 */ 3729 P23_1_SCB7_UART_TX = 17, /* Digital Active - scb[7].uart_tx:1 */ 3730 P23_1_SCB7_I2C_SDA = 18, /* Digital Active - scb[7].i2c_sda:1 */ 3731 P23_1_SCB7_SPI_MOSI = 19, /* Digital Active - scb[7].spi_mosi:1 */ 3732 P23_1_CANFD1_TTCAN_RX0 = 21, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 3733 P23_1_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 3734 3735 /* P23.2 */ 3736 P23_2_GPIO = 0, /* GPIO controls 'out' */ 3737 P23_2_AMUXA = 4, /* Analog mux bus A */ 3738 P23_2_AMUXB = 5, /* Analog mux bus B */ 3739 P23_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3740 P23_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3741 P23_2_TCPWM1_LINE266 = 8, /* Digital Active - tcpwm[1].line[266]:1 */ 3742 P23_2_TCPWM1_LINE_COMPL265 = 9, /* Digital Active - tcpwm[1].line_compl[265]:1 */ 3743 P23_2_TCPWM1_TR_ONE_CNT_IN798 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[798]:1 */ 3744 P23_2_TCPWM1_TR_ONE_CNT_IN796 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[796]:1 */ 3745 P23_2_SCB7_UART_RTS = 17, /* Digital Active - scb[7].uart_rts:1 */ 3746 P23_2_SCB7_I2C_SCL = 18, /* Digital Active - scb[7].i2c_scl:1 */ 3747 P23_2_SCB7_SPI_CLK = 19, /* Digital Active - scb[7].spi_clk:1 */ 3748 P23_2_LIN0_LIN_RX6 = 20, /* Digital Active - lin[0].lin_rx[6]:2 */ 3749 P23_2_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:1 */ 3750 3751 /* P23.3 */ 3752 P23_3_GPIO = 0, /* GPIO controls 'out' */ 3753 P23_3_AMUXA = 4, /* Analog mux bus A */ 3754 P23_3_AMUXB = 5, /* Analog mux bus B */ 3755 P23_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3756 P23_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3757 P23_3_TCPWM1_LINE267 = 8, /* Digital Active - tcpwm[1].line[267]:1 */ 3758 P23_3_TCPWM1_LINE_COMPL266 = 9, /* Digital Active - tcpwm[1].line_compl[266]:1 */ 3759 P23_3_TCPWM1_TR_ONE_CNT_IN801 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[801]:1 */ 3760 P23_3_TCPWM1_TR_ONE_CNT_IN799 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[799]:1 */ 3761 P23_3_SCB7_UART_CTS = 17, /* Digital Active - scb[7].uart_cts:1 */ 3762 P23_3_SCB7_SPI_SELECT0 = 19, /* Digital Active - scb[7].spi_select0:1 */ 3763 P23_3_LIN0_LIN_TX6 = 20, /* Digital Active - lin[0].lin_tx[6]:2 */ 3764 P23_3_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:0 */ 3765 P23_3_PERI_TR_IO_INPUT30 = 26, /* Digital Active - peri.tr_io_input[30]:0 */ 3766 P23_3_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:1 */ 3767 P23_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 3768 3769 /* P23.4 */ 3770 P23_4_GPIO = 0, /* GPIO controls 'out' */ 3771 P23_4_AMUXA = 4, /* Analog mux bus A */ 3772 P23_4_AMUXB = 5, /* Analog mux bus B */ 3773 P23_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3774 P23_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3775 P23_4_TCPWM1_LINE25 = 8, /* Digital Active - tcpwm[1].line[25]:1 */ 3776 P23_4_TCPWM1_LINE_COMPL267 = 9, /* Digital Active - tcpwm[1].line_compl[267]:1 */ 3777 P23_4_TCPWM1_TR_ONE_CNT_IN75 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[75]:1 */ 3778 P23_4_TCPWM1_TR_ONE_CNT_IN802 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[802]:1 */ 3779 P23_4_TCPWM1_LINE521 = 16, /* Digital Active - tcpwm[1].line[521]:0 */ 3780 P23_4_SCB2_SPI_MISO = 17, /* Digital Active - scb[2].spi_miso:2 */ 3781 P23_4_SCB7_SPI_SELECT1 = 19, /* Digital Active - scb[7].spi_select1:1 */ 3782 P23_4_PERI_TR_IO_INPUT31 = 26, /* Digital Active - peri.tr_io_input[31]:0 */ 3783 P23_4_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:2 */ 3784 P23_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 3785 P23_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 3786 3787 /* P23.5 */ 3788 P23_5_GPIO = 0, /* GPIO controls 'out' */ 3789 P23_5_AMUXA = 4, /* Analog mux bus A */ 3790 P23_5_AMUXB = 5, /* Analog mux bus B */ 3791 P23_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3792 P23_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3793 P23_5_TCPWM1_LINE24 = 8, /* Digital Active - tcpwm[1].line[24]:1 */ 3794 P23_5_TCPWM1_LINE_COMPL25 = 9, /* Digital Active - tcpwm[1].line_compl[25]:1 */ 3795 P23_5_TCPWM1_TR_ONE_CNT_IN72 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[72]:1 */ 3796 P23_5_TCPWM1_TR_ONE_CNT_IN76 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[76]:1 */ 3797 P23_5_TCPWM1_LINE_COMPL521 = 16, /* Digital Active - tcpwm[1].line_compl[521]:0 */ 3798 P23_5_SCB2_SPI_MOSI = 17, /* Digital Active - scb[2].spi_mosi:2 */ 3799 P23_5_SCB7_SPI_SELECT2 = 19, /* Digital Active - scb[7].spi_select2:1 */ 3800 P23_5_LIN0_LIN_RX9 = 23, /* Digital Active - lin[0].lin_rx[9]:0 */ 3801 P23_5_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 3802 3803 /* P23.6 */ 3804 P23_6_GPIO = 0, /* GPIO controls 'out' */ 3805 P23_6_AMUXA = 4, /* Analog mux bus A */ 3806 P23_6_AMUXB = 5, /* Analog mux bus B */ 3807 P23_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3808 P23_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3809 P23_6_TCPWM1_LINE23 = 8, /* Digital Active - tcpwm[1].line[23]:1 */ 3810 P23_6_TCPWM1_LINE_COMPL24 = 9, /* Digital Active - tcpwm[1].line_compl[24]:1 */ 3811 P23_6_TCPWM1_TR_ONE_CNT_IN69 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[69]:1 */ 3812 P23_6_TCPWM1_TR_ONE_CNT_IN73 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[73]:1 */ 3813 P23_6_TCPWM1_TR_ONE_CNT_IN1563 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1563]:0 */ 3814 P23_6_SCB2_SPI_CLK = 17, /* Digital Active - scb[2].spi_clk:2 */ 3815 P23_6_LIN0_LIN_TX9 = 23, /* Digital Active - lin[0].lin_tx[9]:0 */ 3816 P23_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 3817 3818 /* P23.7 */ 3819 P23_7_GPIO = 0, /* GPIO controls 'out' */ 3820 P23_7_AMUXA = 4, /* Analog mux bus A */ 3821 P23_7_AMUXB = 5, /* Analog mux bus B */ 3822 P23_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3823 P23_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3824 P23_7_TCPWM1_LINE22 = 8, /* Digital Active - tcpwm[1].line[22]:1 */ 3825 P23_7_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:1 */ 3826 P23_7_TCPWM1_TR_ONE_CNT_IN66 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[66]:1 */ 3827 P23_7_TCPWM1_TR_ONE_CNT_IN70 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[70]:1 */ 3828 P23_7_TCPWM1_TR_ONE_CNT_IN1564 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1564]:0 */ 3829 P23_7_SCB2_SPI_SELECT0 = 17, /* Digital Active - scb[2].spi_select0:2 */ 3830 P23_7_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 3831 P23_7_LIN0_LIN_EN9 = 23, /* Digital Active - lin[0].lin_en[9]:0 */ 3832 P23_7_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:2 */ 3833 P23_7_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 3834 P23_7_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 3835 3836 /* P24.0 */ 3837 P24_0_GPIO = 0, /* GPIO controls 'out' */ 3838 P24_0_AMUXA = 4, /* Analog mux bus A */ 3839 P24_0_AMUXB = 5, /* Analog mux bus B */ 3840 P24_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3841 P24_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3842 P24_0_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:0 */ 3843 P24_0_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:2 */ 3844 P24_0_SDHC0_CARD_DETECT_N = 25, /* Digital Active - sdhc[0].card_detect_n:1 */ 3845 3846 /* P24.1 */ 3847 P24_1_GPIO = 0, /* GPIO controls 'out' */ 3848 P24_1_AMUXA = 4, /* Analog mux bus A */ 3849 P24_1_AMUXB = 5, /* Analog mux bus B */ 3850 P24_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3851 P24_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3852 P24_1_SMIF0_SPIHB_CLK = 23, /* Digital Active - smif[0].spihb_clk:1 */ 3853 P24_1_SDHC0_CARD_MECH_WRITE_PROT = 25, /* Digital Active - sdhc[0].card_mech_write_prot:1 */ 3854 3855 /* P24.2 */ 3856 P24_2_GPIO = 0, /* GPIO controls 'out' */ 3857 P24_2_AMUXA = 4, /* Analog mux bus A */ 3858 P24_2_AMUXB = 5, /* Analog mux bus B */ 3859 P24_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3860 P24_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3861 P24_2_SMIF0_SPIHB_RWDS = 23, /* Digital Active - smif[0].spihb_rwds:1 */ 3862 P24_2_SDHC0_CLK_CARD = 25, /* Digital Active - sdhc[0].clk_card:1 */ 3863 3864 /* P24.3 */ 3865 P24_3_GPIO = 0, /* GPIO controls 'out' */ 3866 P24_3_AMUXA = 4, /* Analog mux bus A */ 3867 P24_3_AMUXB = 5, /* Analog mux bus B */ 3868 P24_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3869 P24_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3870 P24_3_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:0 */ 3871 P24_3_SMIF0_SPIHB_SELECT0 = 23, /* Digital Active - smif[0].spihb_select0:1 */ 3872 P24_3_SDHC0_CARD_CMD = 25, /* Digital Active - sdhc[0].card_cmd:1 */ 3873 3874 /* P24.4 */ 3875 P24_4_GPIO = 0, /* GPIO controls 'out' */ 3876 P24_4_AMUXA = 4, /* Analog mux bus A */ 3877 P24_4_AMUXB = 5, /* Analog mux bus B */ 3878 P24_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3879 P24_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3880 P24_4_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:0 */ 3881 P24_4_SRSS_DDFT_CLK_DIRECT = 22, /* Digital Active - srss.ddft_clk_direct */ 3882 P24_4_SMIF0_SPIHB_SELECT1 = 23, /* Digital Active - smif[0].spihb_select1:1 */ 3883 P24_4_SDHC0_CARD_IF_PWR_EN = 25, /* Digital Active - sdhc[0].card_if_pwr_en:1 */ 3884 3885 /* P25.0 */ 3886 P25_0_GPIO = 0, /* GPIO controls 'out' */ 3887 P25_0_AMUXA = 4, /* Analog mux bus A */ 3888 P25_0_AMUXB = 5, /* Analog mux bus B */ 3889 P25_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3890 P25_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3891 P25_0_SMIF0_SPIHB_DATA0 = 23, /* Digital Active - smif[0].spihb_data0:1 */ 3892 P25_0_SDHC0_CARD_DAT_3TO00 = 25, /* Digital Active - sdhc[0].card_dat_3to0[0]:1 */ 3893 3894 /* P25.1 */ 3895 P25_1_GPIO = 0, /* GPIO controls 'out' */ 3896 P25_1_AMUXA = 4, /* Analog mux bus A */ 3897 P25_1_AMUXB = 5, /* Analog mux bus B */ 3898 P25_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3899 P25_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3900 P25_1_SMIF0_SPIHB_DATA1 = 23, /* Digital Active - smif[0].spihb_data1:1 */ 3901 P25_1_SDHC0_CARD_DAT_3TO01 = 25, /* Digital Active - sdhc[0].card_dat_3to0[1]:1 */ 3902 3903 /* P25.2 */ 3904 P25_2_GPIO = 0, /* GPIO controls 'out' */ 3905 P25_2_AMUXA = 4, /* Analog mux bus A */ 3906 P25_2_AMUXB = 5, /* Analog mux bus B */ 3907 P25_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3908 P25_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3909 P25_2_SMIF0_SPIHB_DATA2 = 23, /* Digital Active - smif[0].spihb_data2:1 */ 3910 P25_2_SDHC0_CARD_DAT_3TO02 = 25, /* Digital Active - sdhc[0].card_dat_3to0[2]:1 */ 3911 3912 /* P25.3 */ 3913 P25_3_GPIO = 0, /* GPIO controls 'out' */ 3914 P25_3_AMUXA = 4, /* Analog mux bus A */ 3915 P25_3_AMUXB = 5, /* Analog mux bus B */ 3916 P25_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3917 P25_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3918 P25_3_SMIF0_SPIHB_DATA3 = 23, /* Digital Active - smif[0].spihb_data3:1 */ 3919 P25_3_SDHC0_CARD_DAT_3TO03 = 25, /* Digital Active - sdhc[0].card_dat_3to0[3]:1 */ 3920 3921 /* P25.4 */ 3922 P25_4_GPIO = 0, /* GPIO controls 'out' */ 3923 P25_4_AMUXA = 4, /* Analog mux bus A */ 3924 P25_4_AMUXB = 5, /* Analog mux bus B */ 3925 P25_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3926 P25_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3927 P25_4_SMIF0_SPIHB_DATA4 = 23, /* Digital Active - smif[0].spihb_data4:1 */ 3928 P25_4_SDHC0_CARD_DAT_7TO40 = 25, /* Digital Active - sdhc[0].card_dat_7to4[0]:1 */ 3929 3930 /* P25.5 */ 3931 P25_5_GPIO = 0, /* GPIO controls 'out' */ 3932 P25_5_AMUXA = 4, /* Analog mux bus A */ 3933 P25_5_AMUXB = 5, /* Analog mux bus B */ 3934 P25_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3935 P25_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3936 P25_5_SMIF0_SPIHB_DATA5 = 23, /* Digital Active - smif[0].spihb_data5:1 */ 3937 P25_5_SDHC0_CARD_DAT_7TO41 = 25, /* Digital Active - sdhc[0].card_dat_7to4[1]:1 */ 3938 3939 /* P25.6 */ 3940 P25_6_GPIO = 0, /* GPIO controls 'out' */ 3941 P25_6_AMUXA = 4, /* Analog mux bus A */ 3942 P25_6_AMUXB = 5, /* Analog mux bus B */ 3943 P25_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3944 P25_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3945 P25_6_SMIF0_SPIHB_DATA6 = 23, /* Digital Active - smif[0].spihb_data6:1 */ 3946 P25_6_SDHC0_CARD_DAT_7TO42 = 25, /* Digital Active - sdhc[0].card_dat_7to4[2]:1 */ 3947 3948 /* P25.7 */ 3949 P25_7_GPIO = 0, /* GPIO controls 'out' */ 3950 P25_7_AMUXA = 4, /* Analog mux bus A */ 3951 P25_7_AMUXB = 5, /* Analog mux bus B */ 3952 P25_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3953 P25_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3954 P25_7_SMIF0_SPIHB_DATA7 = 23, /* Digital Active - smif[0].spihb_data7:1 */ 3955 P25_7_SDHC0_CARD_DAT_7TO43 = 25, /* Digital Active - sdhc[0].card_dat_7to4[3]:1 */ 3956 3957 /* P26.0 */ 3958 P26_0_GPIO = 0, /* GPIO controls 'out' */ 3959 P26_0_AMUXA = 4, /* Analog mux bus A */ 3960 P26_0_AMUXB = 5, /* Analog mux bus B */ 3961 P26_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3962 P26_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3963 P26_0_ETH1_REF_CLK = 27, /* Digital Active - eth[1].ref_clk:0 */ 3964 3965 /* P26.1 */ 3966 P26_1_GPIO = 0, /* GPIO controls 'out' */ 3967 P26_1_AMUXA = 4, /* Analog mux bus A */ 3968 P26_1_AMUXB = 5, /* Analog mux bus B */ 3969 P26_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3970 P26_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3971 P26_1_ETH1_TX_CTL = 27, /* Digital Active - eth[1].tx_ctl:0 */ 3972 3973 /* P26.2 */ 3974 P26_2_GPIO = 0, /* GPIO controls 'out' */ 3975 P26_2_AMUXA = 4, /* Analog mux bus A */ 3976 P26_2_AMUXB = 5, /* Analog mux bus B */ 3977 P26_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3978 P26_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3979 P26_2_ETH1_TX_CLK = 27, /* Digital Active - eth[1].tx_clk:0 */ 3980 3981 /* P26.3 */ 3982 P26_3_GPIO = 0, /* GPIO controls 'out' */ 3983 P26_3_AMUXA = 4, /* Analog mux bus A */ 3984 P26_3_AMUXB = 5, /* Analog mux bus B */ 3985 P26_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3986 P26_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3987 P26_3_ETH1_TXD0 = 27, /* Digital Active - eth[1].txd[0]:0 */ 3988 3989 /* P26.4 */ 3990 P26_4_GPIO = 0, /* GPIO controls 'out' */ 3991 P26_4_AMUXA = 4, /* Analog mux bus A */ 3992 P26_4_AMUXB = 5, /* Analog mux bus B */ 3993 P26_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 3994 P26_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 3995 P26_4_ETH1_TXD1 = 27, /* Digital Active - eth[1].txd[1]:0 */ 3996 3997 /* P26.5 */ 3998 P26_5_GPIO = 0, /* GPIO controls 'out' */ 3999 P26_5_AMUXA = 4, /* Analog mux bus A */ 4000 P26_5_AMUXB = 5, /* Analog mux bus B */ 4001 P26_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4002 P26_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4003 P26_5_ETH1_TXD2 = 27, /* Digital Active - eth[1].txd[2]:0 */ 4004 4005 /* P26.6 */ 4006 P26_6_GPIO = 0, /* GPIO controls 'out' */ 4007 P26_6_AMUXA = 4, /* Analog mux bus A */ 4008 P26_6_AMUXB = 5, /* Analog mux bus B */ 4009 P26_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4010 P26_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4011 P26_6_ETH1_TXD3 = 27, /* Digital Active - eth[1].txd[3]:0 */ 4012 4013 /* P26.7 */ 4014 P26_7_GPIO = 0, /* GPIO controls 'out' */ 4015 P26_7_AMUXA = 4, /* Analog mux bus A */ 4016 P26_7_AMUXB = 5, /* Analog mux bus B */ 4017 P26_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4018 P26_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4019 P26_7_ETH1_RXD0 = 27, /* Digital Active - eth[1].rxd[0]:0 */ 4020 4021 /* P27.0 */ 4022 P27_0_GPIO = 0, /* GPIO controls 'out' */ 4023 P27_0_AMUXA = 4, /* Analog mux bus A */ 4024 P27_0_AMUXB = 5, /* Analog mux bus B */ 4025 P27_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4026 P27_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4027 P27_0_ETH1_RXD1 = 27, /* Digital Active - eth[1].rxd[1]:0 */ 4028 4029 /* P27.1 */ 4030 P27_1_GPIO = 0, /* GPIO controls 'out' */ 4031 P27_1_AMUXA = 4, /* Analog mux bus A */ 4032 P27_1_AMUXB = 5, /* Analog mux bus B */ 4033 P27_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4034 P27_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4035 P27_1_ETH1_RXD2 = 27, /* Digital Active - eth[1].rxd[2]:0 */ 4036 4037 /* P27.2 */ 4038 P27_2_GPIO = 0, /* GPIO controls 'out' */ 4039 P27_2_AMUXA = 4, /* Analog mux bus A */ 4040 P27_2_AMUXB = 5, /* Analog mux bus B */ 4041 P27_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4042 P27_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4043 P27_2_ETH1_RXD3 = 27, /* Digital Active - eth[1].rxd[3]:0 */ 4044 4045 /* P27.3 */ 4046 P27_3_GPIO = 0, /* GPIO controls 'out' */ 4047 P27_3_AMUXA = 4, /* Analog mux bus A */ 4048 P27_3_AMUXB = 5, /* Analog mux bus B */ 4049 P27_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4050 P27_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4051 P27_3_ETH1_RX_CTL = 27, /* Digital Active - eth[1].rx_ctl:0 */ 4052 4053 /* P27.4 */ 4054 P27_4_GPIO = 0, /* GPIO controls 'out' */ 4055 P27_4_AMUXA = 4, /* Analog mux bus A */ 4056 P27_4_AMUXB = 5, /* Analog mux bus B */ 4057 P27_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4058 P27_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4059 P27_4_ETH1_RX_CLK = 27, /* Digital Active - eth[1].rx_clk:0 */ 4060 4061 /* P27.5 */ 4062 P27_5_GPIO = 0, /* GPIO controls 'out' */ 4063 P27_5_AMUXA = 4, /* Analog mux bus A */ 4064 P27_5_AMUXB = 5, /* Analog mux bus B */ 4065 P27_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4066 P27_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4067 P27_5_ETH1_MDIO = 27, /* Digital Active - eth[1].mdio:0 */ 4068 4069 /* P27.6 */ 4070 P27_6_GPIO = 0, /* GPIO controls 'out' */ 4071 P27_6_AMUXA = 4, /* Analog mux bus A */ 4072 P27_6_AMUXB = 5, /* Analog mux bus B */ 4073 P27_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4074 P27_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4075 P27_6_ETH1_MDC = 27, /* Digital Active - eth[1].mdc:0 */ 4076 4077 /* P27.7 */ 4078 P27_7_GPIO = 0, /* GPIO controls 'out' */ 4079 P27_7_AMUXA = 4, /* Analog mux bus A */ 4080 P27_7_AMUXB = 5, /* Analog mux bus B */ 4081 P27_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4082 P27_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4083 P27_7_SRSS_IO_CLK_HF5 = 25, /* Digital Active - srss.io_clk_hf[5]:1 */ 4084 P27_7_ETH1_ETH_TSU_TIMER_CMP_VAL = 27, /* Digital Active - eth[1].eth_tsu_timer_cmp_val:0 */ 4085 4086 /* P28.0 */ 4087 P28_0_GPIO = 0, /* GPIO controls 'out' */ 4088 P28_0_AMUXA = 4, /* Analog mux bus A */ 4089 P28_0_AMUXB = 5, /* Analog mux bus B */ 4090 P28_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4091 P28_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4092 P28_0_TCPWM1_LINE63 = 8, /* Digital Active - tcpwm[1].line[63]:0 */ 4093 P28_0_TCPWM1_LINE_COMPL65 = 9, /* Digital Active - tcpwm[1].line_compl[65]:1 */ 4094 P28_0_TCPWM1_TR_ONE_CNT_IN189 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[189]:0 */ 4095 P28_0_TCPWM1_TR_ONE_CNT_IN196 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[196]:1 */ 4096 P28_0_TCPWM1_LINE524 = 16, /* Digital Active - tcpwm[1].line[524]:1 */ 4097 P28_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:0 */ 4098 P28_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:0 */ 4099 4100 /* P28.1 */ 4101 P28_1_GPIO = 0, /* GPIO controls 'out' */ 4102 P28_1_AMUXA = 4, /* Analog mux bus A */ 4103 P28_1_AMUXB = 5, /* Analog mux bus B */ 4104 P28_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4105 P28_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4106 P28_1_TCPWM1_LINE64 = 8, /* Digital Active - tcpwm[1].line[64]:0 */ 4107 P28_1_TCPWM1_LINE_COMPL63 = 9, /* Digital Active - tcpwm[1].line_compl[63]:0 */ 4108 P28_1_TCPWM1_TR_ONE_CNT_IN192 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[192]:0 */ 4109 P28_1_TCPWM1_TR_ONE_CNT_IN190 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[190]:0 */ 4110 P28_1_TCPWM1_LINE_COMPL524 = 16, /* Digital Active - tcpwm[1].line_compl[524]:1 */ 4111 P28_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:0 */ 4112 P28_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:0 */ 4113 P28_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:0 */ 4114 P28_1_LIN0_LIN_RX17 = 20, /* Digital Active - lin[0].lin_rx[17]:0 */ 4115 4116 /* P28.2 */ 4117 P28_2_GPIO = 0, /* GPIO controls 'out' */ 4118 P28_2_AMUXA = 4, /* Analog mux bus A */ 4119 P28_2_AMUXB = 5, /* Analog mux bus B */ 4120 P28_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4121 P28_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4122 P28_2_TCPWM1_LINE65 = 8, /* Digital Active - tcpwm[1].line[65]:0 */ 4123 P28_2_TCPWM1_LINE_COMPL64 = 9, /* Digital Active - tcpwm[1].line_compl[64]:0 */ 4124 P28_2_TCPWM1_TR_ONE_CNT_IN195 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[195]:0 */ 4125 P28_2_TCPWM1_TR_ONE_CNT_IN193 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[193]:0 */ 4126 P28_2_TCPWM1_TR_ONE_CNT_IN1572 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1572]:1 */ 4127 P28_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:0 */ 4128 P28_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:0 */ 4129 P28_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:0 */ 4130 P28_2_LIN0_LIN_TX17 = 20, /* Digital Active - lin[0].lin_tx[17]:0 */ 4131 4132 /* P28.3 */ 4133 P28_3_GPIO = 0, /* GPIO controls 'out' */ 4134 P28_3_AMUXA = 4, /* Analog mux bus A */ 4135 P28_3_AMUXB = 5, /* Analog mux bus B */ 4136 P28_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4137 P28_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4138 P28_3_TCPWM1_LINE66 = 8, /* Digital Active - tcpwm[1].line[66]:0 */ 4139 P28_3_TCPWM1_LINE_COMPL65 = 9, /* Digital Active - tcpwm[1].line_compl[65]:0 */ 4140 P28_3_TCPWM1_TR_ONE_CNT_IN198 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[198]:0 */ 4141 P28_3_TCPWM1_TR_ONE_CNT_IN196 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[196]:0 */ 4142 P28_3_TCPWM1_TR_ONE_CNT_IN1573 = 16, /* Digital Active - tcpwm[1].tr_one_cnt_in[1573]:1 */ 4143 P28_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:0 */ 4144 P28_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:0 */ 4145 P28_3_LIN0_LIN_EN17 = 20, /* Digital Active - lin[0].lin_en[17]:0 */ 4146 4147 /* P28.4 */ 4148 P28_4_GPIO = 0, /* GPIO controls 'out' */ 4149 P28_4_AMUXA = 4, /* Analog mux bus A */ 4150 P28_4_AMUXB = 5, /* Analog mux bus B */ 4151 P28_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4152 P28_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4153 P28_4_TCPWM1_LINE67 = 8, /* Digital Active - tcpwm[1].line[67]:0 */ 4154 P28_4_TCPWM1_LINE_COMPL66 = 9, /* Digital Active - tcpwm[1].line_compl[66]:0 */ 4155 P28_4_TCPWM1_TR_ONE_CNT_IN201 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[201]:0 */ 4156 P28_4_TCPWM1_TR_ONE_CNT_IN199 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[199]:0 */ 4157 P28_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:0 */ 4158 P28_4_LIN0_LIN_RX18 = 20, /* Digital Active - lin[0].lin_rx[18]:0 */ 4159 4160 /* P28.5 */ 4161 P28_5_GPIO = 0, /* GPIO controls 'out' */ 4162 P28_5_AMUXA = 4, /* Analog mux bus A */ 4163 P28_5_AMUXB = 5, /* Analog mux bus B */ 4164 P28_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4165 P28_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4166 P28_5_TCPWM1_LINE68 = 8, /* Digital Active - tcpwm[1].line[68]:0 */ 4167 P28_5_TCPWM1_LINE_COMPL67 = 9, /* Digital Active - tcpwm[1].line_compl[67]:0 */ 4168 P28_5_TCPWM1_TR_ONE_CNT_IN204 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[204]:0 */ 4169 P28_5_TCPWM1_TR_ONE_CNT_IN202 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[202]:0 */ 4170 P28_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:0 */ 4171 P28_5_LIN0_LIN_TX18 = 20, /* Digital Active - lin[0].lin_tx[18]:0 */ 4172 4173 /* P28.6 */ 4174 P28_6_GPIO = 0, /* GPIO controls 'out' */ 4175 P28_6_AMUXA = 4, /* Analog mux bus A */ 4176 P28_6_AMUXB = 5, /* Analog mux bus B */ 4177 P28_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4178 P28_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4179 P28_6_TCPWM1_LINE69 = 8, /* Digital Active - tcpwm[1].line[69]:0 */ 4180 P28_6_TCPWM1_LINE_COMPL68 = 9, /* Digital Active - tcpwm[1].line_compl[68]:0 */ 4181 P28_6_TCPWM1_TR_ONE_CNT_IN207 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[207]:0 */ 4182 P28_6_TCPWM1_TR_ONE_CNT_IN205 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[205]:0 */ 4183 P28_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:0 */ 4184 P28_6_LIN0_LIN_EN18 = 20, /* Digital Active - lin[0].lin_en[18]:0 */ 4185 4186 /* P28.7 */ 4187 P28_7_GPIO = 0, /* GPIO controls 'out' */ 4188 P28_7_AMUXA = 4, /* Analog mux bus A */ 4189 P28_7_AMUXB = 5, /* Analog mux bus B */ 4190 P28_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4191 P28_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4192 P28_7_TCPWM1_LINE70 = 8, /* Digital Active - tcpwm[1].line[70]:0 */ 4193 P28_7_TCPWM1_LINE_COMPL69 = 9, /* Digital Active - tcpwm[1].line_compl[69]:0 */ 4194 P28_7_TCPWM1_TR_ONE_CNT_IN210 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[210]:0 */ 4195 P28_7_TCPWM1_TR_ONE_CNT_IN208 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[208]:0 */ 4196 P28_7_LIN0_LIN_RX19 = 20, /* Digital Active - lin[0].lin_rx[19]:0 */ 4197 4198 /* P29.0 */ 4199 P29_0_GPIO = 0, /* GPIO controls 'out' */ 4200 P29_0_AMUXA = 4, /* Analog mux bus A */ 4201 P29_0_AMUXB = 5, /* Analog mux bus B */ 4202 P29_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4203 P29_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4204 P29_0_TCPWM1_LINE76 = 8, /* Digital Active - tcpwm[1].line[76]:0 */ 4205 P29_0_TCPWM1_LINE_COMPL75 = 9, /* Digital Active - tcpwm[1].line_compl[75]:0 */ 4206 P29_0_TCPWM1_TR_ONE_CNT_IN228 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[228]:0 */ 4207 P29_0_TCPWM1_TR_ONE_CNT_IN226 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[226]:0 */ 4208 P29_0_LIN0_LIN_TX19 = 20, /* Digital Active - lin[0].lin_tx[19]:0 */ 4209 4210 /* P29.1 */ 4211 P29_1_GPIO = 0, /* GPIO controls 'out' */ 4212 P29_1_AMUXA = 4, /* Analog mux bus A */ 4213 P29_1_AMUXB = 5, /* Analog mux bus B */ 4214 P29_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4215 P29_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4216 P29_1_TCPWM1_LINE77 = 8, /* Digital Active - tcpwm[1].line[77]:0 */ 4217 P29_1_TCPWM1_LINE_COMPL76 = 9, /* Digital Active - tcpwm[1].line_compl[76]:0 */ 4218 P29_1_TCPWM1_TR_ONE_CNT_IN231 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[231]:0 */ 4219 P29_1_TCPWM1_TR_ONE_CNT_IN229 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[229]:0 */ 4220 P29_1_LIN0_LIN_EN19 = 20, /* Digital Active - lin[0].lin_en[19]:0 */ 4221 4222 /* P29.2 */ 4223 P29_2_GPIO = 0, /* GPIO controls 'out' */ 4224 P29_2_AMUXA = 4, /* Analog mux bus A */ 4225 P29_2_AMUXB = 5, /* Analog mux bus B */ 4226 P29_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4227 P29_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4228 P29_2_TCPWM1_LINE78 = 8, /* Digital Active - tcpwm[1].line[78]:0 */ 4229 P29_2_TCPWM1_LINE_COMPL77 = 9, /* Digital Active - tcpwm[1].line_compl[77]:0 */ 4230 P29_2_TCPWM1_TR_ONE_CNT_IN234 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[234]:0 */ 4231 P29_2_TCPWM1_TR_ONE_CNT_IN232 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[232]:0 */ 4232 4233 /* P29.3 */ 4234 P29_3_GPIO = 0, /* GPIO controls 'out' */ 4235 P29_3_AMUXA = 4, /* Analog mux bus A */ 4236 P29_3_AMUXB = 5, /* Analog mux bus B */ 4237 P29_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4238 P29_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4239 P29_3_TCPWM1_LINE79 = 8, /* Digital Active - tcpwm[1].line[79]:0 */ 4240 P29_3_TCPWM1_LINE_COMPL78 = 9, /* Digital Active - tcpwm[1].line_compl[78]:0 */ 4241 P29_3_TCPWM1_TR_ONE_CNT_IN237 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[237]:0 */ 4242 P29_3_TCPWM1_TR_ONE_CNT_IN235 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[235]:0 */ 4243 4244 /* P29.4 */ 4245 P29_4_GPIO = 0, /* GPIO controls 'out' */ 4246 P29_4_AMUXA = 4, /* Analog mux bus A */ 4247 P29_4_AMUXB = 5, /* Analog mux bus B */ 4248 P29_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4249 P29_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4250 P29_4_TCPWM1_LINE80 = 8, /* Digital Active - tcpwm[1].line[80]:0 */ 4251 P29_4_TCPWM1_LINE_COMPL79 = 9, /* Digital Active - tcpwm[1].line_compl[79]:0 */ 4252 P29_4_TCPWM1_TR_ONE_CNT_IN240 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[240]:0 */ 4253 P29_4_TCPWM1_TR_ONE_CNT_IN238 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[238]:0 */ 4254 4255 /* P29.5 */ 4256 P29_5_GPIO = 0, /* GPIO controls 'out' */ 4257 P29_5_AMUXA = 4, /* Analog mux bus A */ 4258 P29_5_AMUXB = 5, /* Analog mux bus B */ 4259 P29_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4260 P29_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4261 P29_5_TCPWM1_LINE81 = 8, /* Digital Active - tcpwm[1].line[81]:0 */ 4262 P29_5_TCPWM1_LINE_COMPL80 = 9, /* Digital Active - tcpwm[1].line_compl[80]:0 */ 4263 P29_5_TCPWM1_TR_ONE_CNT_IN243 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[243]:0 */ 4264 P29_5_TCPWM1_TR_ONE_CNT_IN241 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[241]:0 */ 4265 4266 /* P29.6 */ 4267 P29_6_GPIO = 0, /* GPIO controls 'out' */ 4268 P29_6_AMUXA = 4, /* Analog mux bus A */ 4269 P29_6_AMUXB = 5, /* Analog mux bus B */ 4270 P29_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4271 P29_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4272 P29_6_TCPWM1_LINE82 = 8, /* Digital Active - tcpwm[1].line[82]:0 */ 4273 P29_6_TCPWM1_LINE_COMPL81 = 9, /* Digital Active - tcpwm[1].line_compl[81]:0 */ 4274 P29_6_TCPWM1_TR_ONE_CNT_IN246 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[246]:0 */ 4275 P29_6_TCPWM1_TR_ONE_CNT_IN244 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[244]:0 */ 4276 4277 /* P29.7 */ 4278 P29_7_GPIO = 0, /* GPIO controls 'out' */ 4279 P29_7_AMUXA = 4, /* Analog mux bus A */ 4280 P29_7_AMUXB = 5, /* Analog mux bus B */ 4281 P29_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4282 P29_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4283 P29_7_TCPWM1_LINE83 = 8, /* Digital Active - tcpwm[1].line[83]:0 */ 4284 P29_7_TCPWM1_LINE_COMPL82 = 9, /* Digital Active - tcpwm[1].line_compl[82]:0 */ 4285 P29_7_TCPWM1_TR_ONE_CNT_IN249 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[249]:0 */ 4286 P29_7_TCPWM1_TR_ONE_CNT_IN247 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[247]:0 */ 4287 4288 /* P30.0 */ 4289 P30_0_GPIO = 0, /* GPIO controls 'out' */ 4290 P30_0_AMUXA = 4, /* Analog mux bus A */ 4291 P30_0_AMUXB = 5, /* Analog mux bus B */ 4292 P30_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4293 P30_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4294 P30_0_TCPWM1_LINE83 = 8, /* Digital Active - tcpwm[1].line[83]:1 */ 4295 P30_0_TCPWM1_LINE_COMPL83 = 9, /* Digital Active - tcpwm[1].line_compl[83]:0 */ 4296 P30_0_TCPWM1_TR_ONE_CNT_IN249 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[249]:1 */ 4297 P30_0_TCPWM1_TR_ONE_CNT_IN250 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[250]:0 */ 4298 P30_0_SCB9_UART_RTS = 17, /* Digital Active - scb[9].uart_rts:1 */ 4299 P30_0_SCB9_I2C_SCL = 18, /* Digital Active - scb[9].i2c_scl:1 */ 4300 P30_0_SCB9_SPI_CLK = 19, /* Digital Active - scb[9].spi_clk:1 */ 4301 P30_0_PERI_TR_IO_INPUT34 = 26, /* Digital Active - peri.tr_io_input[34]:0 */ 4302 4303 /* P30.1 */ 4304 P30_1_GPIO = 0, /* GPIO controls 'out' */ 4305 P30_1_AMUXA = 4, /* Analog mux bus A */ 4306 P30_1_AMUXB = 5, /* Analog mux bus B */ 4307 P30_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4308 P30_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4309 P30_1_TCPWM1_LINE82 = 8, /* Digital Active - tcpwm[1].line[82]:1 */ 4310 P30_1_TCPWM1_LINE_COMPL83 = 9, /* Digital Active - tcpwm[1].line_compl[83]:1 */ 4311 P30_1_TCPWM1_TR_ONE_CNT_IN246 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[246]:1 */ 4312 P30_1_TCPWM1_TR_ONE_CNT_IN250 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[250]:1 */ 4313 P30_1_SCB9_UART_CTS = 17, /* Digital Active - scb[9].uart_cts:1 */ 4314 P30_1_SCB9_SPI_SELECT0 = 19, /* Digital Active - scb[9].spi_select0:1 */ 4315 P30_1_LIN0_LIN_RX16 = 20, /* Digital Active - lin[0].lin_rx[16]:2 */ 4316 P30_1_PERI_TR_IO_INPUT35 = 26, /* Digital Active - peri.tr_io_input[35]:0 */ 4317 4318 /* P30.2 */ 4319 P30_2_GPIO = 0, /* GPIO controls 'out' */ 4320 P30_2_AMUXA = 4, /* Analog mux bus A */ 4321 P30_2_AMUXB = 5, /* Analog mux bus B */ 4322 P30_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4323 P30_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4324 P30_2_TCPWM1_LINE81 = 8, /* Digital Active - tcpwm[1].line[81]:1 */ 4325 P30_2_TCPWM1_LINE_COMPL82 = 9, /* Digital Active - tcpwm[1].line_compl[82]:1 */ 4326 P30_2_TCPWM1_TR_ONE_CNT_IN243 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[243]:1 */ 4327 P30_2_TCPWM1_TR_ONE_CNT_IN247 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[247]:1 */ 4328 P30_2_SCB9_SPI_SELECT1 = 19, /* Digital Active - scb[9].spi_select1:1 */ 4329 P30_2_LIN0_LIN_TX16 = 20, /* Digital Active - lin[0].lin_tx[16]:2 */ 4330 P30_2_CANFD1_TTCAN_TX3 = 21, /* Digital Active - canfd[1].ttcan_tx[3]:2 */ 4331 P30_2_PERI_TR_IO_INPUT36 = 26, /* Digital Active - peri.tr_io_input[36]:0 */ 4332 4333 /* P30.3 */ 4334 P30_3_GPIO = 0, /* GPIO controls 'out' */ 4335 P30_3_AMUXA = 4, /* Analog mux bus A */ 4336 P30_3_AMUXB = 5, /* Analog mux bus B */ 4337 P30_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4338 P30_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4339 P30_3_TCPWM1_LINE80 = 8, /* Digital Active - tcpwm[1].line[80]:1 */ 4340 P30_3_TCPWM1_LINE_COMPL81 = 9, /* Digital Active - tcpwm[1].line_compl[81]:1 */ 4341 P30_3_TCPWM1_TR_ONE_CNT_IN240 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[240]:1 */ 4342 P30_3_TCPWM1_TR_ONE_CNT_IN244 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[244]:1 */ 4343 P30_3_SCB9_SPI_SELECT2 = 19, /* Digital Active - scb[9].spi_select2:1 */ 4344 P30_3_LIN0_LIN_EN16 = 20, /* Digital Active - lin[0].lin_en[16]:2 */ 4345 P30_3_CANFD1_TTCAN_RX3 = 21, /* Digital Active - canfd[1].ttcan_rx[3]:2 */ 4346 P30_3_PERI_TR_IO_INPUT37 = 26, /* Digital Active - peri.tr_io_input[37]:0 */ 4347 4348 /* P31.0 */ 4349 P31_0_GPIO = 0, /* GPIO controls 'out' */ 4350 P31_0_AMUXA = 4, /* Analog mux bus A */ 4351 P31_0_AMUXB = 5, /* Analog mux bus B */ 4352 P31_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4353 P31_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4354 P31_0_TCPWM1_LINE79 = 8, /* Digital Active - tcpwm[1].line[79]:1 */ 4355 P31_0_TCPWM1_LINE_COMPL80 = 9, /* Digital Active - tcpwm[1].line_compl[80]:1 */ 4356 P31_0_TCPWM1_TR_ONE_CNT_IN237 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[237]:1 */ 4357 P31_0_TCPWM1_TR_ONE_CNT_IN241 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[241]:1 */ 4358 P31_0_LIN0_LIN_RX17 = 20, /* Digital Active - lin[0].lin_rx[17]:1 */ 4359 4360 /* P31.1 */ 4361 P31_1_GPIO = 0, /* GPIO controls 'out' */ 4362 P31_1_AMUXA = 4, /* Analog mux bus A */ 4363 P31_1_AMUXB = 5, /* Analog mux bus B */ 4364 P31_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4365 P31_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4366 P31_1_TCPWM1_LINE78 = 8, /* Digital Active - tcpwm[1].line[78]:1 */ 4367 P31_1_TCPWM1_LINE_COMPL79 = 9, /* Digital Active - tcpwm[1].line_compl[79]:1 */ 4368 P31_1_TCPWM1_TR_ONE_CNT_IN234 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[234]:1 */ 4369 P31_1_TCPWM1_TR_ONE_CNT_IN238 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[238]:1 */ 4370 P31_1_LIN0_LIN_TX17 = 20, /* Digital Active - lin[0].lin_tx[17]:1 */ 4371 4372 /* P31.2 */ 4373 P31_2_GPIO = 0, /* GPIO controls 'out' */ 4374 P31_2_AMUXA = 4, /* Analog mux bus A */ 4375 P31_2_AMUXB = 5, /* Analog mux bus B */ 4376 P31_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4377 P31_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4378 P31_2_TCPWM1_LINE77 = 8, /* Digital Active - tcpwm[1].line[77]:1 */ 4379 P31_2_TCPWM1_LINE_COMPL78 = 9, /* Digital Active - tcpwm[1].line_compl[78]:1 */ 4380 P31_2_TCPWM1_TR_ONE_CNT_IN231 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[231]:1 */ 4381 P31_2_TCPWM1_TR_ONE_CNT_IN235 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[235]:1 */ 4382 P31_2_LIN0_LIN_EN17 = 20, /* Digital Active - lin[0].lin_en[17]:1 */ 4383 4384 /* P32.0 */ 4385 P32_0_GPIO = 0, /* GPIO controls 'out' */ 4386 P32_0_AMUXA = 4, /* Analog mux bus A */ 4387 P32_0_AMUXB = 5, /* Analog mux bus B */ 4388 P32_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4389 P32_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4390 P32_0_TCPWM1_LINE76 = 8, /* Digital Active - tcpwm[1].line[76]:1 */ 4391 P32_0_TCPWM1_LINE_COMPL77 = 9, /* Digital Active - tcpwm[1].line_compl[77]:1 */ 4392 P32_0_TCPWM1_TR_ONE_CNT_IN228 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[228]:1 */ 4393 P32_0_TCPWM1_TR_ONE_CNT_IN232 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[232]:1 */ 4394 P32_0_SCB10_UART_RX = 17, /* Digital Active - scb[10].uart_rx:1 */ 4395 P32_0_SCB10_SPI_MISO = 19, /* Digital Active - scb[10].spi_miso:1 */ 4396 P32_0_PERI_TR_IO_INPUT40 = 26, /* Digital Active - peri.tr_io_input[40]:0 */ 4397 4398 /* P32.1 */ 4399 P32_1_GPIO = 0, /* GPIO controls 'out' */ 4400 P32_1_AMUXA = 4, /* Analog mux bus A */ 4401 P32_1_AMUXB = 5, /* Analog mux bus B */ 4402 P32_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4403 P32_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4404 P32_1_TCPWM1_LINE75 = 8, /* Digital Active - tcpwm[1].line[75]:1 */ 4405 P32_1_TCPWM1_LINE_COMPL76 = 9, /* Digital Active - tcpwm[1].line_compl[76]:1 */ 4406 P32_1_TCPWM1_TR_ONE_CNT_IN225 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[225]:1 */ 4407 P32_1_TCPWM1_TR_ONE_CNT_IN229 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[229]:1 */ 4408 P32_1_SCB10_UART_TX = 17, /* Digital Active - scb[10].uart_tx:1 */ 4409 P32_1_SCB10_I2C_SDA = 18, /* Digital Active - scb[10].i2c_sda:1 */ 4410 P32_1_SCB10_SPI_MOSI = 19, /* Digital Active - scb[10].spi_mosi:1 */ 4411 P32_1_PERI_TR_IO_INPUT41 = 26, /* Digital Active - peri.tr_io_input[41]:0 */ 4412 4413 /* P32.2 */ 4414 P32_2_GPIO = 0, /* GPIO controls 'out' */ 4415 P32_2_AMUXA = 4, /* Analog mux bus A */ 4416 P32_2_AMUXB = 5, /* Analog mux bus B */ 4417 P32_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4418 P32_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4419 P32_2_TCPWM1_LINE74 = 8, /* Digital Active - tcpwm[1].line[74]:1 */ 4420 P32_2_TCPWM1_LINE_COMPL75 = 9, /* Digital Active - tcpwm[1].line_compl[75]:1 */ 4421 P32_2_TCPWM1_TR_ONE_CNT_IN222 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[222]:1 */ 4422 P32_2_TCPWM1_TR_ONE_CNT_IN226 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[226]:1 */ 4423 P32_2_SCB10_UART_RTS = 17, /* Digital Active - scb[10].uart_rts:1 */ 4424 P32_2_SCB10_I2C_SCL = 18, /* Digital Active - scb[10].i2c_scl:1 */ 4425 P32_2_SCB10_SPI_CLK = 19, /* Digital Active - scb[10].spi_clk:1 */ 4426 P32_2_LIN0_LIN_RX18 = 20, /* Digital Active - lin[0].lin_rx[18]:1 */ 4427 P32_2_PERI_TR_IO_INPUT42 = 26, /* Digital Active - peri.tr_io_input[42]:0 */ 4428 4429 /* P32.3 */ 4430 P32_3_GPIO = 0, /* GPIO controls 'out' */ 4431 P32_3_AMUXA = 4, /* Analog mux bus A */ 4432 P32_3_AMUXB = 5, /* Analog mux bus B */ 4433 P32_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4434 P32_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4435 P32_3_TCPWM1_LINE73 = 8, /* Digital Active - tcpwm[1].line[73]:1 */ 4436 P32_3_TCPWM1_LINE_COMPL74 = 9, /* Digital Active - tcpwm[1].line_compl[74]:1 */ 4437 P32_3_TCPWM1_TR_ONE_CNT_IN219 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[219]:1 */ 4438 P32_3_TCPWM1_TR_ONE_CNT_IN223 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[223]:1 */ 4439 P32_3_SCB10_UART_CTS = 17, /* Digital Active - scb[10].uart_cts:1 */ 4440 P32_3_SCB10_SPI_SELECT0 = 19, /* Digital Active - scb[10].spi_select0:1 */ 4441 P32_3_LIN0_LIN_TX18 = 20, /* Digital Active - lin[0].lin_tx[18]:1 */ 4442 P32_3_PERI_TR_IO_INPUT43 = 26, /* Digital Active - peri.tr_io_input[43]:0 */ 4443 4444 /* P32.4 */ 4445 P32_4_GPIO = 0, /* GPIO controls 'out' */ 4446 P32_4_AMUXA = 4, /* Analog mux bus A */ 4447 P32_4_AMUXB = 5, /* Analog mux bus B */ 4448 P32_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4449 P32_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4450 P32_4_TCPWM1_LINE72 = 8, /* Digital Active - tcpwm[1].line[72]:1 */ 4451 P32_4_TCPWM1_LINE_COMPL73 = 9, /* Digital Active - tcpwm[1].line_compl[73]:1 */ 4452 P32_4_TCPWM1_TR_ONE_CNT_IN216 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[216]:1 */ 4453 P32_4_TCPWM1_TR_ONE_CNT_IN220 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[220]:1 */ 4454 P32_4_LIN0_LIN_RX10 = 18, /* Digital Active - lin[0].lin_rx[10]:1 */ 4455 P32_4_SCB10_SPI_SELECT1 = 19, /* Digital Active - scb[10].spi_select1:1 */ 4456 P32_4_LIN0_LIN_EN18 = 20, /* Digital Active - lin[0].lin_en[18]:1 */ 4457 P32_4_PERI_TR_IO_INPUT44 = 26, /* Digital Active - peri.tr_io_input[44]:0 */ 4458 4459 /* P32.5 */ 4460 P32_5_GPIO = 0, /* GPIO controls 'out' */ 4461 P32_5_AMUXA = 4, /* Analog mux bus A */ 4462 P32_5_AMUXB = 5, /* Analog mux bus B */ 4463 P32_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4464 P32_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4465 P32_5_TCPWM1_LINE71 = 8, /* Digital Active - tcpwm[1].line[71]:1 */ 4466 P32_5_TCPWM1_LINE_COMPL72 = 9, /* Digital Active - tcpwm[1].line_compl[72]:1 */ 4467 P32_5_TCPWM1_TR_ONE_CNT_IN213 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[213]:1 */ 4468 P32_5_TCPWM1_TR_ONE_CNT_IN217 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[217]:1 */ 4469 P32_5_LIN0_LIN_TX10 = 18, /* Digital Active - lin[0].lin_tx[10]:1 */ 4470 P32_5_SCB10_SPI_SELECT2 = 19, /* Digital Active - scb[10].spi_select2:1 */ 4471 P32_5_LIN0_LIN_RX19 = 20, /* Digital Active - lin[0].lin_rx[19]:1 */ 4472 P32_5_PERI_TR_IO_INPUT45 = 26, /* Digital Active - peri.tr_io_input[45]:0 */ 4473 4474 /* P32.6 */ 4475 P32_6_GPIO = 0, /* GPIO controls 'out' */ 4476 P32_6_AMUXA = 4, /* Analog mux bus A */ 4477 P32_6_AMUXB = 5, /* Analog mux bus B */ 4478 P32_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4479 P32_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4480 P32_6_TCPWM1_LINE70 = 8, /* Digital Active - tcpwm[1].line[70]:1 */ 4481 P32_6_TCPWM1_LINE_COMPL71 = 9, /* Digital Active - tcpwm[1].line_compl[71]:1 */ 4482 P32_6_TCPWM1_TR_ONE_CNT_IN210 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[210]:1 */ 4483 P32_6_TCPWM1_TR_ONE_CNT_IN214 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[214]:1 */ 4484 P32_6_LIN0_LIN_EN10 = 18, /* Digital Active - lin[0].lin_en[10]:1 */ 4485 P32_6_SCB10_SPI_SELECT3 = 19, /* Digital Active - scb[10].spi_select3:1 */ 4486 P32_6_LIN0_LIN_TX19 = 20, /* Digital Active - lin[0].lin_tx[19]:1 */ 4487 P32_6_CANFD1_TTCAN_TX4 = 21, /* Digital Active - canfd[1].ttcan_tx[4]:1 */ 4488 P32_6_PERI_TR_IO_INPUT46 = 26, /* Digital Active - peri.tr_io_input[46]:0 */ 4489 4490 /* P32.7 */ 4491 P32_7_GPIO = 0, /* GPIO controls 'out' */ 4492 P32_7_AMUXA = 4, /* Analog mux bus A */ 4493 P32_7_AMUXB = 5, /* Analog mux bus B */ 4494 P32_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4495 P32_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4496 P32_7_TCPWM1_LINE69 = 8, /* Digital Active - tcpwm[1].line[69]:1 */ 4497 P32_7_TCPWM1_LINE_COMPL70 = 9, /* Digital Active - tcpwm[1].line_compl[70]:1 */ 4498 P32_7_TCPWM1_TR_ONE_CNT_IN207 = 10, /* Digital Active - tcpwm[1].tr_one_cnt_in[207]:1 */ 4499 P32_7_TCPWM1_TR_ONE_CNT_IN211 = 11, /* Digital Active - tcpwm[1].tr_one_cnt_in[211]:1 */ 4500 P32_7_LIN0_LIN_EN19 = 20, /* Digital Active - lin[0].lin_en[19]:1 */ 4501 P32_7_CANFD1_TTCAN_RX4 = 21, /* Digital Active - canfd[1].ttcan_rx[4]:1 */ 4502 P32_7_PERI_TR_IO_INPUT47 = 26, /* Digital Active - peri.tr_io_input[47]:0 */ 4503 4504 /* P33.0 */ 4505 P33_0_GPIO = 0, /* GPIO controls 'out' */ 4506 P33_0_AMUXA = 4, /* Analog mux bus A */ 4507 P33_0_AMUXB = 5, /* Analog mux bus B */ 4508 P33_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4509 P33_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4510 P33_0_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk:1 */ 4511 4512 /* P33.1 */ 4513 P33_1_GPIO = 0, /* GPIO controls 'out' */ 4514 P33_1_AMUXA = 4, /* Analog mux bus A */ 4515 P33_1_AMUXB = 5, /* Analog mux bus B */ 4516 P33_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4517 P33_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4518 P33_1_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl:1 */ 4519 P33_1_ETH1_TX_ER = 27, /* Digital Active - eth[1].tx_er:0 */ 4520 4521 /* P33.2 */ 4522 P33_2_GPIO = 0, /* GPIO controls 'out' */ 4523 P33_2_AMUXA = 4, /* Analog mux bus A */ 4524 P33_2_AMUXB = 5, /* Analog mux bus B */ 4525 P33_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4526 P33_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4527 P33_2_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk:1 */ 4528 4529 /* P33.3 */ 4530 P33_3_GPIO = 0, /* GPIO controls 'out' */ 4531 P33_3_AMUXA = 4, /* Analog mux bus A */ 4532 P33_3_AMUXB = 5, /* Analog mux bus B */ 4533 P33_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4534 P33_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4535 P33_3_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0]:1 */ 4536 P33_3_ETH1_TXD4 = 27, /* Digital Active - eth[1].txd[4]:0 */ 4537 4538 /* P33.4 */ 4539 P33_4_GPIO = 0, /* GPIO controls 'out' */ 4540 P33_4_AMUXA = 4, /* Analog mux bus A */ 4541 P33_4_AMUXB = 5, /* Analog mux bus B */ 4542 P33_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4543 P33_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4544 P33_4_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1]:1 */ 4545 P33_4_ETH1_TXD5 = 27, /* Digital Active - eth[1].txd[5]:0 */ 4546 4547 /* P33.5 */ 4548 P33_5_GPIO = 0, /* GPIO controls 'out' */ 4549 P33_5_AMUXA = 4, /* Analog mux bus A */ 4550 P33_5_AMUXB = 5, /* Analog mux bus B */ 4551 P33_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4552 P33_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4553 P33_5_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2]:1 */ 4554 P33_5_ETH1_TXD6 = 27, /* Digital Active - eth[1].txd[6]:0 */ 4555 4556 /* P33.6 */ 4557 P33_6_GPIO = 0, /* GPIO controls 'out' */ 4558 P33_6_AMUXA = 4, /* Analog mux bus A */ 4559 P33_6_AMUXB = 5, /* Analog mux bus B */ 4560 P33_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4561 P33_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4562 P33_6_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3]:1 */ 4563 P33_6_ETH1_TXD7 = 27, /* Digital Active - eth[1].txd[7]:0 */ 4564 4565 /* P33.7 */ 4566 P33_7_GPIO = 0, /* GPIO controls 'out' */ 4567 P33_7_AMUXA = 4, /* Analog mux bus A */ 4568 P33_7_AMUXB = 5, /* Analog mux bus B */ 4569 P33_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4570 P33_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4571 P33_7_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0]:1 */ 4572 P33_7_ETH1_RXD4 = 27, /* Digital Active - eth[1].rxd[4]:0 */ 4573 4574 /* P34.0 */ 4575 P34_0_GPIO = 0, /* GPIO controls 'out' */ 4576 P34_0_AMUXA = 4, /* Analog mux bus A */ 4577 P34_0_AMUXB = 5, /* Analog mux bus B */ 4578 P34_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4579 P34_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4580 P34_0_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1]:1 */ 4581 P34_0_ETH1_RXD5 = 27, /* Digital Active - eth[1].rxd[5]:0 */ 4582 4583 /* P34.1 */ 4584 P34_1_GPIO = 0, /* GPIO controls 'out' */ 4585 P34_1_AMUXA = 4, /* Analog mux bus A */ 4586 P34_1_AMUXB = 5, /* Analog mux bus B */ 4587 P34_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4588 P34_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4589 P34_1_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2]:1 */ 4590 P34_1_ETH1_RXD6 = 27, /* Digital Active - eth[1].rxd[6]:0 */ 4591 4592 /* P34.2 */ 4593 P34_2_GPIO = 0, /* GPIO controls 'out' */ 4594 P34_2_AMUXA = 4, /* Analog mux bus A */ 4595 P34_2_AMUXB = 5, /* Analog mux bus B */ 4596 P34_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4597 P34_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4598 P34_2_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3]:1 */ 4599 P34_2_ETH1_RXD7 = 27, /* Digital Active - eth[1].rxd[7]:0 */ 4600 4601 /* P34.3 */ 4602 P34_3_GPIO = 0, /* GPIO controls 'out' */ 4603 P34_3_AMUXA = 4, /* Analog mux bus A */ 4604 P34_3_AMUXB = 5, /* Analog mux bus B */ 4605 P34_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4606 P34_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4607 P34_3_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl:1 */ 4608 P34_3_ETH1_RX_ER = 27, /* Digital Active - eth[1].rx_er:0 */ 4609 4610 /* P34.4 */ 4611 P34_4_GPIO = 0, /* GPIO controls 'out' */ 4612 P34_4_AMUXA = 4, /* Analog mux bus A */ 4613 P34_4_AMUXB = 5, /* Analog mux bus B */ 4614 P34_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4615 P34_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4616 P34_4_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk:1 */ 4617 4618 /* P34.5 */ 4619 P34_5_GPIO = 0, /* GPIO controls 'out' */ 4620 P34_5_AMUXA = 4, /* Analog mux bus A */ 4621 P34_5_AMUXB = 5, /* Analog mux bus B */ 4622 P34_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4623 P34_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4624 P34_5_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio:1 */ 4625 4626 /* P34.6 */ 4627 P34_6_GPIO = 0, /* GPIO controls 'out' */ 4628 P34_6_AMUXA = 4, /* Analog mux bus A */ 4629 P34_6_AMUXB = 5, /* Analog mux bus B */ 4630 P34_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4631 P34_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4632 P34_6_ETH0_MDC = 24, /* Digital Active - eth[0].mdc:1 */ 4633 4634 /* P34.7 */ 4635 P34_7_GPIO = 0, /* GPIO controls 'out' */ 4636 P34_7_AMUXA = 4, /* Analog mux bus A */ 4637 P34_7_AMUXB = 5, /* Analog mux bus B */ 4638 P34_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 4639 P34_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 4640 P34_7_ETH0_ETH_TSU_TIMER_CMP_VAL = 24, /* Digital Active - eth[0].eth_tsu_timer_cmp_val:1 */ 4641 P34_7_SRSS_IO_CLK_HF5 = 25 /* Digital Active - srss.io_clk_hf[5]:0 */ 4642 } en_hsiom_sel_t; 4643 4644 #endif /* _GPIO_XMC7200_320_BGA_H_ */ 4645 4646 4647 /* [] END OF FILE */ 4648
