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Searched refs:INTR_M_SET (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_scb.h92 __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ member
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_scb_v2.h94 __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ member
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_scb_v4.h98 __IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */ member
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h1174 #define SCB_INTR_M_SET(base) (((CySCB_V1_Type*) (base))->INTR_M_SET)
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1822 #define SCB_INTR_M_SET(base) (((CySCB_Type*) (base))->INTR_M_SET)
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h505 #define SCB_INTR_M_SET(base) (((CySCB_Type*) (base))->INTR_M_SET)