1 /***************************************************************************//** 2 * \file cyip_flashc.h 3 * 4 * \brief 5 * FLASHC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FLASHC_H_ 28 #define _CYIP_FLASHC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FLASHC 34 *******************************************************************************/ 35 36 #define FLASHC_FM_CTL_ECT_SECTION_SIZE 0x00001000UL 37 #define FLASHC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Flash Macro Registers (FLASHC_FM_CTL_ECT) 41 */ 42 typedef struct { 43 __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash Macro Control */ 44 __IOM uint32_t FM_CODE_MARGIN; /*!< 0x00000004 Flash Macro Margin Mode on Code Flash */ 45 __OM uint32_t FM_ADDR; /*!< 0x00000008 Flash Macro Address */ 46 __IM uint32_t RESERVED[5]; 47 __IOM uint32_t INTR; /*!< 0x00000020 Interrupt */ 48 __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt Set */ 49 __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt Mask */ 50 __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt Masked */ 51 __OM uint32_t ECC_OVERRIDE; /*!< 0x00000030 ECC Data In override information and control bits */ 52 __IM uint32_t RESERVED1[3]; 53 __OM uint32_t FM_DATA; /*!< 0x00000040 Flash macro data_in[31 to 0] both Code and Work Flash */ 54 __IM uint32_t RESERVED2[8]; 55 __IOM uint32_t BOOKMARK; /*!< 0x00000064 Bookmark register - keeps the current FW HV seq */ 56 __IM uint32_t RESERVED3[230]; 57 __IOM uint32_t MAIN_FLASH_SAFETY; /*!< 0x00000400 Main (Code) Flash Security enable */ 58 __IM uint32_t STATUS; /*!< 0x00000404 Status read from Flash Macro */ 59 __IM uint32_t RESERVED4[62]; 60 __IOM uint32_t WORK_FLASH_SAFETY; /*!< 0x00000500 Work Flash Security enable */ 61 __IM uint32_t RESERVED5[703]; 62 } FLASHC_FM_CTL_ECT_Type; /*!< Size = 4096 (0x1000) */ 63 64 /** 65 * \brief Flash controller (FLASHC) 66 */ 67 typedef struct { 68 __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */ 69 __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */ 70 __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */ 71 __IM uint32_t RESERVED[165]; 72 __IOM uint32_t ECC_CTL; /*!< 0x000002A0 ECC control */ 73 __IM uint32_t RESERVED1[3]; 74 __IOM uint32_t FM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */ 75 __IOM uint32_t FM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */ 76 __IM uint32_t FM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */ 77 __IOM uint32_t FM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */ 78 __IM uint32_t RESERVED2[80]; 79 __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */ 80 __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */ 81 __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */ 82 __IM uint32_t RESERVED3[13]; 83 __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */ 84 __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */ 85 __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */ 86 __IM uint32_t RESERVED4[5]; 87 __IOM uint32_t CM0_STATUS; /*!< 0x00000460 CM0+ interface status */ 88 __IM uint32_t RESERVED5[31]; 89 __IOM uint32_t CM7_0_STATUS; /*!< 0x000004E0 CM7 #0 interface status */ 90 __IM uint32_t RESERVED6[31]; 91 __IOM uint32_t CM7_1_STATUS; /*!< 0x00000560 CM7 #1 interface status */ 92 __IM uint32_t RESERVED7[7]; 93 __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000580 Cryptography buffer control */ 94 __IM uint32_t RESERVED8[31]; 95 __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000600 Datawire 0 buffer control */ 96 __IM uint32_t RESERVED9[31]; 97 __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000680 Datawire 1 buffer control */ 98 __IM uint32_t RESERVED10[31]; 99 __IOM uint32_t DMAC_BUFF_CTL; /*!< 0x00000700 DMA controller buffer control */ 100 __IM uint32_t RESERVED11[31]; 101 __IOM uint32_t SLOW0_MS_BUFF_CTL; /*!< 0x00000780 Slow external master 0 buffer control */ 102 __IM uint32_t RESERVED12[31]; 103 __IOM uint32_t SLOW1_MS_BUFF_CTL; /*!< 0x00000800 Slow external master 1 buffer control */ 104 __IM uint32_t RESERVED13[14847]; 105 FLASHC_FM_CTL_ECT_Type FM_CTL_ECT; /*!< 0x0000F000 Flash Macro Registers */ 106 } FLASHC_Type; /*!< Size = 65536 (0x10000) */ 107 108 109 /* FLASHC_FM_CTL_ECT.FM_CTL */ 110 #define FLASHC_FM_CTL_ECT_FM_CTL_FM_MODE_Pos 0UL 111 #define FLASHC_FM_CTL_ECT_FM_CTL_FM_MODE_Msk 0x1FUL 112 #define FLASHC_FM_CTL_ECT_FM_CTL_EMB_START_Pos 31UL 113 #define FLASHC_FM_CTL_ECT_FM_CTL_EMB_START_Msk 0x80000000UL 114 /* FLASHC_FM_CTL_ECT.FM_CODE_MARGIN */ 115 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Pos 0UL 116 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Msk 0x1FFUL 117 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Pos 9UL 118 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Msk 0x200UL 119 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Pos 10UL 120 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Msk 0xFC00UL 121 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Pos 29UL 122 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Msk 0x20000000UL 123 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Pos 30UL 124 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Msk 0x40000000UL 125 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_EN_Pos 31UL 126 #define FLASHC_FM_CTL_ECT_FM_CODE_MARGIN_MARGIN_MODE_EN_Msk 0x80000000UL 127 /* FLASHC_FM_CTL_ECT.FM_ADDR */ 128 #define FLASHC_FM_CTL_ECT_FM_ADDR_FM_ADDR_Pos 0UL 129 #define FLASHC_FM_CTL_ECT_FM_ADDR_FM_ADDR_Msk 0xFFFFFFFFUL 130 /* FLASHC_FM_CTL_ECT.INTR */ 131 #define FLASHC_FM_CTL_ECT_INTR_INTR_Pos 0UL 132 #define FLASHC_FM_CTL_ECT_INTR_INTR_Msk 0x1UL 133 /* FLASHC_FM_CTL_ECT.INTR_SET */ 134 #define FLASHC_FM_CTL_ECT_INTR_SET_INTR_SET_Pos 0UL 135 #define FLASHC_FM_CTL_ECT_INTR_SET_INTR_SET_Msk 0x1UL 136 /* FLASHC_FM_CTL_ECT.INTR_MASK */ 137 #define FLASHC_FM_CTL_ECT_INTR_MASK_INTR_MASK_Pos 0UL 138 #define FLASHC_FM_CTL_ECT_INTR_MASK_INTR_MASK_Msk 0x1UL 139 /* FLASHC_FM_CTL_ECT.INTR_MASKED */ 140 #define FLASHC_FM_CTL_ECT_INTR_MASKED_INTR_MASKED_Pos 0UL 141 #define FLASHC_FM_CTL_ECT_INTR_MASKED_INTR_MASKED_Msk 0x1UL 142 /* FLASHC_FM_CTL_ECT.ECC_OVERRIDE */ 143 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Pos 0UL 144 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Msk 0xFFUL 145 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Pos 30UL 146 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Msk 0x40000000UL 147 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Pos 31UL 148 #define FLASHC_FM_CTL_ECT_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Msk 0x80000000UL 149 /* FLASHC_FM_CTL_ECT.FM_DATA */ 150 #define FLASHC_FM_CTL_ECT_FM_DATA_FM_DATA_Pos 0UL 151 #define FLASHC_FM_CTL_ECT_FM_DATA_FM_DATA_Msk 0xFFFFFFFFUL 152 /* FLASHC_FM_CTL_ECT.BOOKMARK */ 153 #define FLASHC_FM_CTL_ECT_BOOKMARK_BOOKMARK_Pos 0UL 154 #define FLASHC_FM_CTL_ECT_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL 155 /* FLASHC_FM_CTL_ECT.MAIN_FLASH_SAFETY */ 156 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Pos 0UL 157 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk 0x1UL 158 /* FLASHC_FM_CTL_ECT.STATUS */ 159 #define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Pos 0UL 160 #define FLASHC_FM_CTL_ECT_STATUS_PGM_CODE_Msk 0x1UL 161 #define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Pos 1UL 162 #define FLASHC_FM_CTL_ECT_STATUS_PGM_WORK_Msk 0x2UL 163 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Pos 2UL 164 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_CODE_Msk 0x4UL 165 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Pos 3UL 166 #define FLASHC_FM_CTL_ECT_STATUS_ERASE_WORK_Msk 0x8UL 167 #define FLASHC_FM_CTL_ECT_STATUS_ERS_SUSPEND_Pos 4UL 168 #define FLASHC_FM_CTL_ECT_STATUS_ERS_SUSPEND_Msk 0x10UL 169 #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Pos 5UL 170 #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHECK_WORK_Msk 0x20UL 171 #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHCEK_PASS_Pos 6UL 172 #define FLASHC_FM_CTL_ECT_STATUS_BLANK_CHCEK_PASS_Msk 0x40UL 173 #define FLASHC_FM_CTL_ECT_STATUS_POR_1B_ECC_CORRECTED_Pos 27UL 174 #define FLASHC_FM_CTL_ECT_STATUS_POR_1B_ECC_CORRECTED_Msk 0x8000000UL 175 #define FLASHC_FM_CTL_ECT_STATUS_POR_2B_ECC_ERROR_Pos 28UL 176 #define FLASHC_FM_CTL_ECT_STATUS_POR_2B_ECC_ERROR_Msk 0x10000000UL 177 #define FLASHC_FM_CTL_ECT_STATUS_NATIVE_POR_Pos 29UL 178 #define FLASHC_FM_CTL_ECT_STATUS_NATIVE_POR_Msk 0x20000000UL 179 #define FLASHC_FM_CTL_ECT_STATUS_HANG_Pos 30UL 180 #define FLASHC_FM_CTL_ECT_STATUS_HANG_Msk 0x40000000UL 181 #define FLASHC_FM_CTL_ECT_STATUS_BUSY_Pos 31UL 182 #define FLASHC_FM_CTL_ECT_STATUS_BUSY_Msk 0x80000000UL 183 /* FLASHC_FM_CTL_ECT.WORK_FLASH_SAFETY */ 184 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Pos 0UL 185 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk 0x1UL 186 187 188 /* FLASHC.FLASH_CTL */ 189 #define FLASHC_FLASH_CTL_WS_Pos 0UL 190 #define FLASHC_FLASH_CTL_WS_Msk 0xFUL 191 #define FLASHC_FLASH_CTL_MAIN_MAP_Pos 8UL 192 #define FLASHC_FLASH_CTL_MAIN_MAP_Msk 0x100UL 193 #define FLASHC_FLASH_CTL_WORK_MAP_Pos 9UL 194 #define FLASHC_FLASH_CTL_WORK_MAP_Msk 0x200UL 195 #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL 196 #define FLASHC_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL 197 #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Pos 13UL 198 #define FLASHC_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL 199 #define FLASHC_FLASH_CTL_MAIN_ECC_EN_Pos 16UL 200 #define FLASHC_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL 201 #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL 202 #define FLASHC_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL 203 #define FLASHC_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL 204 #define FLASHC_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL 205 #define FLASHC_FLASH_CTL_WORK_ECC_EN_Pos 20UL 206 #define FLASHC_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL 207 #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL 208 #define FLASHC_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL 209 #define FLASHC_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL 210 #define FLASHC_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL 211 #define FLASHC_FLASH_CTL_WORK_SEQ_RD_EN_Pos 24UL 212 #define FLASHC_FLASH_CTL_WORK_SEQ_RD_EN_Msk 0x1000000UL 213 /* FLASHC.FLASH_PWR_CTL */ 214 #define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL 215 #define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL 216 #define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL 217 #define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL 218 /* FLASHC.FLASH_CMD */ 219 #define FLASHC_FLASH_CMD_INV_Pos 0UL 220 #define FLASHC_FLASH_CMD_INV_Msk 0x1UL 221 #define FLASHC_FLASH_CMD_BUFF_INV_Pos 1UL 222 #define FLASHC_FLASH_CMD_BUFF_INV_Msk 0x2UL 223 /* FLASHC.ECC_CTL */ 224 #define FLASHC_ECC_CTL_WORD_ADDR_Pos 0UL 225 #define FLASHC_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL 226 #define FLASHC_ECC_CTL_PARITY_Pos 24UL 227 #define FLASHC_ECC_CTL_PARITY_Msk 0xFF000000UL 228 /* FLASHC.FM_SRAM_ECC_CTL0 */ 229 #define FLASHC_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL 230 #define FLASHC_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL 231 /* FLASHC.FM_SRAM_ECC_CTL1 */ 232 #define FLASHC_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL 233 #define FLASHC_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL 234 /* FLASHC.FM_SRAM_ECC_CTL2 */ 235 #define FLASHC_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL 236 #define FLASHC_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL 237 /* FLASHC.FM_SRAM_ECC_CTL3 */ 238 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL 239 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL 240 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL 241 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL 242 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL 243 #define FLASHC_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL 244 /* FLASHC.CM0_CA_CTL0 */ 245 #define FLASHC_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL 246 #define FLASHC_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL 247 #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL 248 #define FLASHC_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL 249 #define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL 250 #define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL 251 #define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL 252 #define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL 253 #define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL 254 #define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL 255 #define FLASHC_CM0_CA_CTL0_CA_EN_Pos 31UL 256 #define FLASHC_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL 257 /* FLASHC.CM0_CA_CTL1 */ 258 #define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL 259 #define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL 260 #define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL 261 #define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 262 /* FLASHC.CM0_CA_CTL2 */ 263 #define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL 264 #define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 265 /* FLASHC.CM0_CA_STATUS0 */ 266 #define FLASHC_CM0_CA_STATUS0_VALID32_Pos 0UL 267 #define FLASHC_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL 268 /* FLASHC.CM0_CA_STATUS1 */ 269 #define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL 270 #define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 271 /* FLASHC.CM0_CA_STATUS2 */ 272 #define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL 273 #define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL 274 /* FLASHC.CM0_STATUS */ 275 #define FLASHC_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 276 #define FLASHC_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 277 #define FLASHC_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL 278 #define FLASHC_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 279 /* FLASHC.CM7_0_STATUS */ 280 #define FLASHC_CM7_0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 281 #define FLASHC_CM7_0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 282 #define FLASHC_CM7_0_STATUS_WORK_INTERNAL_ERR_Pos 1UL 283 #define FLASHC_CM7_0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 284 /* FLASHC.CM7_1_STATUS */ 285 #define FLASHC_CM7_1_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 286 #define FLASHC_CM7_1_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 287 #define FLASHC_CM7_1_STATUS_WORK_INTERNAL_ERR_Pos 1UL 288 #define FLASHC_CM7_1_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 289 /* FLASHC.CRYPTO_BUFF_CTL */ 290 #define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL 291 #define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL 292 /* FLASHC.DW0_BUFF_CTL */ 293 #define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL 294 #define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 295 /* FLASHC.DW1_BUFF_CTL */ 296 #define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL 297 #define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 298 /* FLASHC.DMAC_BUFF_CTL */ 299 #define FLASHC_DMAC_BUFF_CTL_PREF_EN_Pos 30UL 300 #define FLASHC_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL 301 /* FLASHC.SLOW0_MS_BUFF_CTL */ 302 #define FLASHC_SLOW0_MS_BUFF_CTL_PREF_EN_Pos 30UL 303 #define FLASHC_SLOW0_MS_BUFF_CTL_PREF_EN_Msk 0x40000000UL 304 /* FLASHC.SLOW1_MS_BUFF_CTL */ 305 #define FLASHC_SLOW1_MS_BUFF_CTL_PREF_EN_Pos 30UL 306 #define FLASHC_SLOW1_MS_BUFF_CTL_PREF_EN_Msk 0x40000000UL 307 308 309 #endif /* _CYIP_FLASHC_H_ */ 310 311 312 /* [] END OF FILE */ 313
