1 /***************************************************************************//** 2 * \file cyip_evtgen.h 3 * 4 * \brief 5 * EVTGEN IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_EVTGEN_H_ 28 #define _CYIP_EVTGEN_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * EVTGEN 34 *******************************************************************************/ 35 36 #define EVTGEN_COMP_STRUCT_SECTION_SIZE 0x00000020UL 37 #define EVTGEN_SECTION_SIZE 0x00001000UL 38 39 /** 40 * \brief Comparator structure (EVTGEN_COMP_STRUCT) 41 */ 42 typedef struct { 43 __IOM uint32_t COMP_CTL; /*!< 0x00000000 Comparator control */ 44 __IOM uint32_t COMP0; /*!< 0x00000004 Comparator 0 (Active functionality) */ 45 __IOM uint32_t COMP1; /*!< 0x00000008 Comparator 1 (DeepSleep functionality) */ 46 __IM uint32_t RESERVED[5]; 47 } EVTGEN_COMP_STRUCT_Type; /*!< Size = 32 (0x20) */ 48 49 /** 50 * \brief Event generator (EVTGEN) 51 */ 52 typedef struct { 53 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 54 __IM uint32_t COMP0_STATUS; /*!< 0x00000004 Comparator structures comparator 0 status */ 55 __IM uint32_t COMP1_STATUS; /*!< 0x00000008 Comparator structures comparator 1 status */ 56 __IM uint32_t RESERVED; 57 __IM uint32_t COUNTER_STATUS; /*!< 0x00000010 Counter status */ 58 __IM uint32_t COUNTER; /*!< 0x00000014 Counter */ 59 __IM uint32_t RESERVED1[2]; 60 __IOM uint32_t RATIO_CTL; /*!< 0x00000020 Ratio control */ 61 __IOM uint32_t RATIO; /*!< 0x00000024 Ratio */ 62 __IM uint32_t RESERVED2[2]; 63 __IOM uint32_t REF_CLOCK_CTL; /*!< 0x00000030 Reference clock control */ 64 __IM uint32_t RESERVED3[435]; 65 __IOM uint32_t INTR; /*!< 0x00000700 Interrupt */ 66 __IOM uint32_t INTR_SET; /*!< 0x00000704 Interrupt set */ 67 __IOM uint32_t INTR_MASK; /*!< 0x00000708 Interrupt mask */ 68 __IM uint32_t INTR_MASKED; /*!< 0x0000070C Interrupt masked */ 69 __IOM uint32_t INTR_DPSLP; /*!< 0x00000710 DeepSleep interrupt */ 70 __IOM uint32_t INTR_DPSLP_SET; /*!< 0x00000714 DeepSleep interrupt set */ 71 __IOM uint32_t INTR_DPSLP_MASK; /*!< 0x00000718 DeepSleep interrupt mask */ 72 __IM uint32_t INTR_DPSLP_MASKED; /*!< 0x0000071C DeepSleep interrupt masked */ 73 __IM uint32_t RESERVED4[56]; 74 EVTGEN_COMP_STRUCT_Type COMP_STRUCT[32]; /*!< 0x00000800 Comparator structure */ 75 } EVTGEN_Type; /*!< Size = 3072 (0xC00) */ 76 77 78 /* EVTGEN_COMP_STRUCT.COMP_CTL */ 79 #define EVTGEN_COMP_STRUCT_COMP_CTL_COMP0_EN_Pos 0UL 80 #define EVTGEN_COMP_STRUCT_COMP_CTL_COMP0_EN_Msk 0x1UL 81 #define EVTGEN_COMP_STRUCT_COMP_CTL_COMP1_EN_Pos 1UL 82 #define EVTGEN_COMP_STRUCT_COMP_CTL_COMP1_EN_Msk 0x2UL 83 #define EVTGEN_COMP_STRUCT_COMP_CTL_TR_OUT_EDGE_Pos 16UL 84 #define EVTGEN_COMP_STRUCT_COMP_CTL_TR_OUT_EDGE_Msk 0x10000UL 85 #define EVTGEN_COMP_STRUCT_COMP_CTL_ENABLED_Pos 31UL 86 #define EVTGEN_COMP_STRUCT_COMP_CTL_ENABLED_Msk 0x80000000UL 87 /* EVTGEN_COMP_STRUCT.COMP0 */ 88 #define EVTGEN_COMP_STRUCT_COMP0_INT32_Pos 0UL 89 #define EVTGEN_COMP_STRUCT_COMP0_INT32_Msk 0xFFFFFFFFUL 90 /* EVTGEN_COMP_STRUCT.COMP1 */ 91 #define EVTGEN_COMP_STRUCT_COMP1_INT32_Pos 0UL 92 #define EVTGEN_COMP_STRUCT_COMP1_INT32_Msk 0xFFFFFFFFUL 93 94 95 /* EVTGEN.CTL */ 96 #define EVTGEN_CTL_ENABLED_Pos 31UL 97 #define EVTGEN_CTL_ENABLED_Msk 0x80000000UL 98 /* EVTGEN.COMP0_STATUS */ 99 #define EVTGEN_COMP0_STATUS_COMP0_OUT_Pos 0UL 100 #define EVTGEN_COMP0_STATUS_COMP0_OUT_Msk 0xFFFFUL 101 /* EVTGEN.COMP1_STATUS */ 102 #define EVTGEN_COMP1_STATUS_COMP1_OUT_Pos 0UL 103 #define EVTGEN_COMP1_STATUS_COMP1_OUT_Msk 0xFFFFUL 104 /* EVTGEN.COUNTER_STATUS */ 105 #define EVTGEN_COUNTER_STATUS_VALID_Pos 31UL 106 #define EVTGEN_COUNTER_STATUS_VALID_Msk 0x80000000UL 107 /* EVTGEN.COUNTER */ 108 #define EVTGEN_COUNTER_INT32_Pos 0UL 109 #define EVTGEN_COUNTER_INT32_Msk 0xFFFFFFFFUL 110 /* EVTGEN.RATIO_CTL */ 111 #define EVTGEN_RATIO_CTL_DYNAMIC_MODE_Pos 16UL 112 #define EVTGEN_RATIO_CTL_DYNAMIC_MODE_Msk 0x70000UL 113 #define EVTGEN_RATIO_CTL_DYNAMIC_Pos 30UL 114 #define EVTGEN_RATIO_CTL_DYNAMIC_Msk 0x40000000UL 115 #define EVTGEN_RATIO_CTL_VALID_Pos 31UL 116 #define EVTGEN_RATIO_CTL_VALID_Msk 0x80000000UL 117 /* EVTGEN.RATIO */ 118 #define EVTGEN_RATIO_FRAC8_Pos 8UL 119 #define EVTGEN_RATIO_FRAC8_Msk 0xFF00UL 120 #define EVTGEN_RATIO_INT16_Pos 16UL 121 #define EVTGEN_RATIO_INT16_Msk 0xFFFF0000UL 122 /* EVTGEN.REF_CLOCK_CTL */ 123 #define EVTGEN_REF_CLOCK_CTL_INT_DIV_Pos 0UL 124 #define EVTGEN_REF_CLOCK_CTL_INT_DIV_Msk 0xFFUL 125 /* EVTGEN.INTR */ 126 #define EVTGEN_INTR_COMP0_Pos 0UL 127 #define EVTGEN_INTR_COMP0_Msk 0xFFFFUL 128 /* EVTGEN.INTR_SET */ 129 #define EVTGEN_INTR_SET_COMP0_Pos 0UL 130 #define EVTGEN_INTR_SET_COMP0_Msk 0xFFFFUL 131 /* EVTGEN.INTR_MASK */ 132 #define EVTGEN_INTR_MASK_COMP0_Pos 0UL 133 #define EVTGEN_INTR_MASK_COMP0_Msk 0xFFFFUL 134 /* EVTGEN.INTR_MASKED */ 135 #define EVTGEN_INTR_MASKED_COMP0_Pos 0UL 136 #define EVTGEN_INTR_MASKED_COMP0_Msk 0xFFFFUL 137 /* EVTGEN.INTR_DPSLP */ 138 #define EVTGEN_INTR_DPSLP_COMP1_Pos 0UL 139 #define EVTGEN_INTR_DPSLP_COMP1_Msk 0xFFFFUL 140 /* EVTGEN.INTR_DPSLP_SET */ 141 #define EVTGEN_INTR_DPSLP_SET_COMP1_Pos 0UL 142 #define EVTGEN_INTR_DPSLP_SET_COMP1_Msk 0xFFFFUL 143 /* EVTGEN.INTR_DPSLP_MASK */ 144 #define EVTGEN_INTR_DPSLP_MASK_COMP1_Pos 0UL 145 #define EVTGEN_INTR_DPSLP_MASK_COMP1_Msk 0xFFFFUL 146 /* EVTGEN.INTR_DPSLP_MASKED */ 147 #define EVTGEN_INTR_DPSLP_MASKED_COMP1_Pos 0UL 148 #define EVTGEN_INTR_DPSLP_MASKED_COMP1_Msk 0xFFFFUL 149 150 151 #endif /* _CYIP_EVTGEN_H_ */ 152 153 154 /* [] END OF FILE */ 155
