1 /***************************************************************************//** 2 * \file cyip_dw.h 3 * 4 * \brief 5 * DW IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_DW_H_ 28 #define _CYIP_DW_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * DW 34 *******************************************************************************/ 35 36 #define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL 37 #define DW_SECTION_SIZE 0x00001000UL 38 39 /** 40 * \brief DW channel structure (DW_CH_STRUCT) 41 */ 42 typedef struct { 43 __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */ 44 __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */ 45 __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */ 46 __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */ 47 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 48 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 49 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 50 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 51 } DW_CH_STRUCT_V1_Type; /*!< Size = 32 (0x20) */ 52 53 /** 54 * \brief Datawire Controller (DW) 55 */ 56 typedef struct { 57 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 58 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 59 __IM uint32_t PENDING; /*!< 0x00000008 Pending channels */ 60 __IM uint32_t RESERVED; 61 __IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */ 62 __IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */ 63 __IM uint32_t RESERVED1[2]; 64 __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */ 65 __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */ 66 __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */ 67 __IM uint32_t RESERVED2; 68 __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */ 69 __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */ 70 __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */ 71 __IM uint32_t RESERVED3; 72 __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */ 73 __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */ 74 __IM uint32_t RESERVED4[494]; 75 DW_CH_STRUCT_V1_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */ 76 } DW_V1_Type; /*!< Size = 3072 (0xC00) */ 77 78 79 /* DW_CH_STRUCT.CH_CTL */ 80 #define DW_CH_STRUCT_CH_CTL_P_Pos 0UL 81 #define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL 82 #define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL 83 #define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL 84 #define DW_CH_STRUCT_CH_CTL_B_Pos 2UL 85 #define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL 86 #define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL 87 #define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL 88 #define DW_CH_STRUCT_CH_CTL_PRIO_Pos 16UL 89 #define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x30000UL 90 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 18UL 91 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x40000UL 92 #define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL 93 #define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL 94 /* DW_CH_STRUCT.CH_STATUS */ 95 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL 96 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL 97 /* DW_CH_STRUCT.CH_IDX */ 98 #define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL 99 #define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL 100 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL 101 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL 102 /* DW_CH_STRUCT.CH_CURR_PTR */ 103 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL 104 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL 105 /* DW_CH_STRUCT.INTR */ 106 #define DW_CH_STRUCT_INTR_CH_Pos 0UL 107 #define DW_CH_STRUCT_INTR_CH_Msk 0x1UL 108 /* DW_CH_STRUCT.INTR_SET */ 109 #define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL 110 #define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL 111 /* DW_CH_STRUCT.INTR_MASK */ 112 #define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL 113 #define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL 114 /* DW_CH_STRUCT.INTR_MASKED */ 115 #define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL 116 #define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL 117 118 119 /* DW.CTL */ 120 #define DW_CTL_ENABLED_Pos 31UL 121 #define DW_CTL_ENABLED_Msk 0x80000000UL 122 /* DW.STATUS */ 123 #define DW_STATUS_P_Pos 0UL 124 #define DW_STATUS_P_Msk 0x1UL 125 #define DW_STATUS_NS_Pos 1UL 126 #define DW_STATUS_NS_Msk 0x2UL 127 #define DW_STATUS_B_Pos 2UL 128 #define DW_STATUS_B_Msk 0x4UL 129 #define DW_STATUS_PC_Pos 4UL 130 #define DW_STATUS_PC_Msk 0xF0UL 131 #define DW_STATUS_CH_IDX_Pos 8UL 132 #define DW_STATUS_CH_IDX_Msk 0x1F00UL 133 #define DW_STATUS_PRIO_Pos 16UL 134 #define DW_STATUS_PRIO_Msk 0x30000UL 135 #define DW_STATUS_PREEMPTABLE_Pos 18UL 136 #define DW_STATUS_PREEMPTABLE_Msk 0x40000UL 137 #define DW_STATUS_STATE_Pos 20UL 138 #define DW_STATUS_STATE_Msk 0x700000UL 139 #define DW_STATUS_ACTIVE_Pos 31UL 140 #define DW_STATUS_ACTIVE_Msk 0x80000000UL 141 /* DW.PENDING */ 142 #define DW_PENDING_CH_PENDING_Pos 0UL 143 #define DW_PENDING_CH_PENDING_Msk 0xFFFFFFFFUL 144 /* DW.STATUS_INTR */ 145 #define DW_STATUS_INTR_CH_Pos 0UL 146 #define DW_STATUS_INTR_CH_Msk 0xFFFFFFFFUL 147 /* DW.STATUS_INTR_MASKED */ 148 #define DW_STATUS_INTR_MASKED_CH_Pos 0UL 149 #define DW_STATUS_INTR_MASKED_CH_Msk 0xFFFFFFFFUL 150 /* DW.ACT_DESCR_CTL */ 151 #define DW_ACT_DESCR_CTL_DATA_Pos 0UL 152 #define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL 153 /* DW.ACT_DESCR_SRC */ 154 #define DW_ACT_DESCR_SRC_DATA_Pos 0UL 155 #define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL 156 /* DW.ACT_DESCR_DST */ 157 #define DW_ACT_DESCR_DST_DATA_Pos 0UL 158 #define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL 159 /* DW.ACT_DESCR_X_CTL */ 160 #define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL 161 #define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL 162 /* DW.ACT_DESCR_Y_CTL */ 163 #define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL 164 #define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL 165 /* DW.ACT_DESCR_NEXT_PTR */ 166 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL 167 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL 168 /* DW.ACT_SRC */ 169 #define DW_ACT_SRC_SRC_ADDR_Pos 0UL 170 #define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL 171 /* DW.ACT_DST */ 172 #define DW_ACT_DST_DST_ADDR_Pos 0UL 173 #define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL 174 175 176 #endif /* _CYIP_DW_H_ */ 177 178 179 /* [] END OF FILE */ 180
