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Searched refs:DW_CTL_ENABLED_Msk (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_dw.h121 #define DW_CTL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_dw.h150 #define DW_CTL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-3.6.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_dw.h150 #define DW_CTL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_dma.h625 DW_CTL(base) |= DW_CTL_ENABLED_Msk; in Cy_DMA_Enable()
644 DW_CTL(base) &= (uint32_t) ~DW_CTL_ENABLED_Msk; in Cy_DMA_Disable()