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Searched refs:Cy_SysClk_PllIsEnabled (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_utils_impl.c691 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
696 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
701 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
Dcyhal_clock.c1578 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_PLL400M); in _cyhal_clock_is_enabled_pll()
1583 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_DPLL_LP); in _cyhal_clock_is_enabled_pll()
1586 return Cy_SysClk_PllIsEnabled(clock->channel + 1); in _cyhal_clock_is_enabled_pll()
1714 bool enabled = Cy_SysClk_PllIsEnabled(pll_idx); in _cyhal_clock_set_frequency_pll()
Dcyhal_usb_dev.c295 …if ( Cy_SysClk_PllIsEnabled(path) && (CY_SYSCLK_CLKPATH_IN_IMO == Cy_SysClk_ClkPathGetSource(path)… in _cyhal_usb_dev_hf_clock_setup()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c1432 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_ValidateAllPLL()
1446 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_ValidateAllPLL()
2830 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_SystemConfig()
2851 if((devConfig->pll0Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1))) in Cy_PRA_SystemConfig()
2874 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_SystemConfig()
2895 if((devConfig->pll1Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2))) in Cy_PRA_SystemConfig()
Dcy_sysclk.c1772 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) in Cy_SysClk_PllIsEnabled() function
1915 else if (Cy_SysClk_PllIsEnabled(clkPath)) in Cy_SysClk_PllManualConfigure()
2552 if ((0UL == fllpll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllpll)) in Cy_SysClk_DeepSleepCallback()
2849 …enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode… in Cy_SysClk_PllGetFrequency()
Dcy_sysclk_v2.c2757 … if (clkPath < (CY_SRSS_NUM_PLL) && Cy_SysClk_PllIsEnabled(clkPath)) /* PLL? (always path 1...N)*/ in Cy_SysClk_ClkPathGetFrequency()
2771 else if ((clkPath != 0UL) && (clkPath <= (CY_SRSS_NUM_PLL)) && Cy_SysClk_PllIsEnabled(clkPath)) in Cy_SysClk_ClkPathGetFrequency()
2785 …else if (clkPath <= (CY_SRSS_NUM_PLL) && Cy_SysClk_PllIsEnabled(clkPath)) /* PLL? (always path 1..… in Cy_SysClk_ClkPathGetFrequency()
4736 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) in Cy_SysClk_PllIsEnabled() function
Dcy_pra.c2954 if ((0UL == fllPll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllPll)) in Cy_PRA_ClkDSBeforeTransition()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2444 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath);