Home
last modified time | relevance | path

Searched refs:Cy_SysClk_PllEnable (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_usb_dev.c257 result = Cy_SysClk_PllEnable(pll, 1000000); in _cyhal_usb_dev_init_pll()
Dcyhal_clock.c1665 ? Cy_SysClk_PllEnable(pll_idx, wait_for_lock ? _CYHAL_CLOCK_PLL_LOCK_TIME : 0UL) in _cyhal_clock_set_enabled_pll()
1748 cy_rslt_t rslt2 = Cy_SysClk_PllEnable(pll_idx, _CYHAL_CLOCK_PLL_LOCK_TIME); in _cyhal_clock_set_frequency_pll()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2422 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus);
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c260 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(clkPath, 10000u)) in Cy_PRA_PllInit()
Dcy_sysclk.c1973 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) in Cy_SysClk_PllEnable() function
Dcy_sysclk_v2.c5016 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus) in Cy_SysClk_PllEnable() function