Searched refs:CY_TDM_SEL_SRSS_CLK0 (Results 1 – 2 of 2) sorted by relevance
268 CY_TDM_SEL_SRSS_CLK0 = 0U, /**< Interface clock is selected as clk_if_srss[0]. */ enumerator
1790 pdl_config->tx_config->clkSel = mclk_tx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()1809 pdl_config->rx_config->clkSel = mclk_rx ? CY_TDM_SEL_MCLK_IN : CY_TDM_SEL_SRSS_CLK0; in _cyhal_audioss_populate_pdl_config()