CY_SYSCLK_DIV_8_BIT (reference) in projects: hal_infineon-3.6.0

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Searched refs:CY_SYSCLK_DIV_8_BIT (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-3.6.0/mtb-hal-cat1/include_pvt/
D	cyhal_hw_resources.h	249 …BLOCK_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((gr), CY_SYSCLK_DIV_8_BIT), /… 260 …ERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST((instance), (gr), CY_SYSCLK_DIV_8_BIT), /… 274 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /!< 8bit Peripheral Divider / 308 …CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /!< Equivalent to CYHAL_CLOCK_BLO… 392 …CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /!< Equivalent to CYHAL_CLOCK_BLO… 472 …CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLO…
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
D	cy_sysclk.c	46 if (dividerType == CY_SYSCLK_DIV_8_BIT) in Cy_SysClk_PeriphSetDivider() 77 if (dividerType == CY_SYSCLK_DIV_8_BIT) in Cy_SysClk_PeriphGetDivider() 153 if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) \|\| in Cy_SysClk_PeriphAssignDivider() 180 if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) \|\| in Cy_SysClk_PeriphEnableDivider() 205 if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) \|\| in Cy_SysClk_PeriphDisableDivider() 228 if (((dividerTypePA == CY_SYSCLK_DIV_8_BIT) && (dividerNumPA < PERI_DIV_8_NR)) \|\| in Cy_SysClk_PeriphEnablePhaseAlignDivider() 256 CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) \|\| \ in Cy_SysClk_PeriphGetDividerEnabled() 263 case CY_SYSCLK_DIV_8_BIT: in Cy_SysClk_PeriphGetDividerEnabled() 2730 CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR)) \|\| \ in Cy_SysClk_PeriphGetFrequency() 2738 case CY_SYSCLK_DIV_8_BIT: in Cy_SysClk_PeriphGetFrequency()
D	cy_ctdac.c	`405 if ((dividerType == CY_SYSCLK_DIV_8_BIT) \|\| (dividerType == CY_SYSCLK_DIV_16_BIT)) in Cy_CTDAC_ConfigureClock() 424 if ((dividerType == CY_SYSCLK_DIV_8_BIT) \|\| (dividerType == CY_SYSCLK_DIV_16_BIT)) in Cy_CTDAC_ConfigureClock()`
D	cy_sysclk_v2.c	52 if (dividerType == CY_SYSCLK_DIV_8_BIT) in Cy_SysClk_PeriPclkSetDivider() 87 if (dividerType == CY_SYSCLK_DIV_8_BIT) in Cy_SysClk_PeriPclkGetDivider() 182 …if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < (PERI_DIV_8_NR(instNum, grpNum)))) … in Cy_SysClk_PeriPclkAssignDivider() 222 …if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < (PERI_DIV_8_NR(instNum, grpNum)))) … in Cy_SysClk_PeriPclkEnableDivider() 253 …if (((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < (PERI_DIV_8_NR(instNum, grpNum)))) … in Cy_SysClk_PeriPclkDisableDivider() 282 …if (((dividerTypePA == CY_SYSCLK_DIV_8_BIT) && (dividerNumPA < (PERI_DIV_8_NR(instNum, grpNum))… in Cy_SysClk_PeriPclkEnablePhaseAlignDivider() 315 …CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR(instNum, grpN… in Cy_SysClk_PeriPclkGetDividerEnabled() 322 case CY_SYSCLK_DIV_8_BIT: in Cy_SysClk_PeriPclkGetDividerEnabled() 5547 …CY_ASSERT_L1(((dividerType == CY_SYSCLK_DIV_8_BIT) && (dividerNum < PERI_DIV_8_NR(instNum , grp… in Cy_SysClk_PeriPclkGetFrequency() 5559 case CY_SYSCLK_DIV_8_BIT: in Cy_SysClk_PeriPclkGetFrequency()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
D	cy_ctdac.h	`388 #define CY_CTDAC_FAST_CLKCFG_TYPE CY_SYSCLK_DIV_8_BIT …`
D	cy_sysclk.h	`6046 CY_SYSCLK_DIV_8_BIT = 0U, /*< Divider Type is an 8 bit divider / enumerator`
/hal_infineon-3.6.0/mtb-hal-cat1/source/
D	cyhal_dac.c	`111 .dividerType = CY_SYSCLK_DIV_8_BIT,`

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