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Searched refs:CY_SCB_SPI_RX_INTR_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_scb_spi.h874 #define CY_SCB_SPI_RX_INTR_MASK (CY_SCB_SPI_RX_TRIGGER | CY_SCB_SPI_RX_NOT_EMPTY | CY_SCB_SPI_RX_… macro
1069 return (Cy_SCB_GetRxInterruptStatus(base) & CY_SCB_SPI_RX_INTR_MASK); in Cy_SCB_SPI_GetRxFifoStatus()
1096 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(clearMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_ClearRxFifoStatus()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_scb_spi.c88 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_Init()
176 SCB_INTR_RX_MASK(base) = (config->rxFifoIntEnableMask & CY_SCB_SPI_RX_INTR_MASK); in Cy_SCB_SPI_Init()