Searched refs:CY_DMA_INTR_CAUSE_SRC_MISAL (Results 1 – 2 of 2) sorted by relevance
406 if((status == CY_DMA_INTR_CAUSE_SRC_MISAL) || in _cyhal_dma_dw_stage()
270 CY_DMA_INTR_CAUSE_SRC_MISAL = 4U, /**< Source address is not aligned. */ enumerator