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Searched refs:CY_ALIGN (Results 1 – 25 of 30) sorted by relevance

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/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/
Dcy_crypto_core_ecc_domain_params.c57 CY_ALIGN(4) static const uint8_t eccP192Polynomial[CY_CRYPTO_ECC_P192_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
64 CY_ALIGN(4) static const uint8_t eccP192PolyBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = in Cy_Crypto_Core_ECC_GetCurveParams()
71 CY_ALIGN(4) static const uint8_t eccP192Order[CY_CRYPTO_ECC_P192_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
79 CY_ALIGN(4) static const uint8_t eccP192OrderBarrett[CY_CRYPTO_ECC_P192_BYTE_SIZE + 1u] = in Cy_Crypto_Core_ECC_GetCurveParams()
88 CY_ALIGN(4) static const uint8_t eccP192BasePointX[CY_CRYPTO_ECC_P192_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
96 CY_ALIGN(4) static const uint8_t eccP192BasePointY[CY_CRYPTO_ECC_P192_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
106 CY_ALIGN(4) static const uint8_t eccP224Polynomial[CY_CRYPTO_ECC_P224_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
114 CY_ALIGN(4) static const uint8_t eccP224PolyBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = in Cy_Crypto_Core_ECC_GetCurveParams()
122 CY_ALIGN(4) static const uint8_t eccP224Order[CY_CRYPTO_ECC_P224_BYTE_SIZE] = in Cy_Crypto_Core_ECC_GetCurveParams()
130 CY_ALIGN(4) static const uint8_t eccP224OrderBarrett[CY_CRYPTO_ECC_P224_BYTE_SIZE + 1u] = in Cy_Crypto_Core_ECC_GetCurveParams()
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Dcy_cryptolite_ecdsa.c60 CY_ALIGN(4) static const uint8_t eccP192Polynomial[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
67 CY_ALIGN(4) static const uint8_t eccP192PolyBarrett[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE + 1u] = in Cy_Cryptolite_ECC_GetCurveParams()
74 CY_ALIGN(4) static const uint8_t eccP192Order[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
82 CY_ALIGN(4) static const uint8_t eccP192OrderBarrett[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE + 1u] = in Cy_Cryptolite_ECC_GetCurveParams()
91 CY_ALIGN(4) static const uint8_t eccP192BasePointX[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
99 CY_ALIGN(4) static const uint8_t eccP192BasePointY[CY_CRYPTOLITE_ECC_P192_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
108 CY_ALIGN(4) static const uint8_t eccP224Polynomial[CY_CRYPTOLITE_ECC_P224_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
116 CY_ALIGN(4) static const uint8_t eccP224PolyBarrett[CY_CRYPTOLITE_ECC_P224_BYTE_SIZE + 1u] = in Cy_Cryptolite_ECC_GetCurveParams()
124 CY_ALIGN(4) static const uint8_t eccP224Order[CY_CRYPTOLITE_ECC_P224_BYTE_SIZE] = in Cy_Cryptolite_ECC_GetCurveParams()
132 CY_ALIGN(4) static const uint8_t eccP224OrderBarrett[CY_CRYPTOLITE_ECC_P224_BYTE_SIZE + 1u] = in Cy_Cryptolite_ECC_GetCurveParams()
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Dcy_cryptolite_nist_p.c82 CY_ALIGN(4) uint8_t p_t_double[VU_BITS_TO_BYTES(2U*BIT_SIZE)]; // 2*bit_size in Cryptolite_EC_Bar_MulRed()
83 CY_ALIGN(4) uint8_t t2_plus2[VU_BITS_TO_BYTES(BIT_SIZE+2U+1U)]; // bit_size + 3 in Cryptolite_EC_Bar_MulRed()
155 CY_ALIGN(4) uint8_t ab_double[VU_BITS_TO_BYTES(2U * BIT_SIZE)]; // the variable size is ignored in Cryptolite_EC_MulMod()
209 CY_ALIGN(4) uint8_t my_a[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_DivMod()
210 CY_ALIGN(4) uint8_t my_b[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_DivMod()
211 CY_ALIGN(4) uint8_t my_v[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_DivMod()
212 CY_ALIGN(4) uint8_t temp[VU_BITS_TO_BYTES(BIT_SIZE+1U)]; in Cryptolite_EC_DivMod()
306 CY_ALIGN(4) uint8_t t1[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_XYCZ_ADD()
307 CY_ALIGN(4) uint8_t t2[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_XYCZ_ADD()
370 CY_ALIGN(4) uint8_t t1[VU_BITS_TO_BYTES(BIT_SIZE)]; in Cryptolite_EC_XYCZ_ADDC()
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Dcy_crypto_core_cmac_v2.c215 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static const uint8_t p_padding[16] = in Cy_Crypto_Core_V2_Cmac_Finish()
304 …CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_aes_buffers_t aesBuffersData = {{ 0 },… in Cy_Crypto_Core_V2_Cmac()
306 …CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_v2_cmac_buffers_t cmacBuffersData = {{0UL, … in Cy_Crypto_Core_V2_Cmac()
Dcy_cryptolite_vu.c58 CY_ALIGN(4) uint8_t temp[VU_BITS_TO_BYTES(VU_TEST_EQUAL_LESS_SIZE)]; in Cy_Cryptolite_Vu_test_equal()
74 CY_ALIGN(4) uint8_t temp[VU_BITS_TO_BYTES(VU_TEST_EQUAL_LESS_SIZE+1U)]={0}; in Cy_Cryptolite_Vu_test_less_than()
Dcy_crypto_core_hmac_v2.c414 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_hmac_state_t hmacState; in Cy_Crypto_Core_V2_Hmac()
416 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_v2_hmac_buffers_t hmacBuffer; in Cy_Crypto_Core_V2_Hmac()
Dcy_flash_srom.c21 CY_ALIGN(32) static un_srom_api_scrach_sram_t g_scratch; // This must locate on SRAM.
23 CY_ALIGN(32) static un_srom_api_args_2_t g_scratch2; // This must locate on SRAM.
Dcy_efuse.c48 CY_ALIGN(32) static volatile uint32_t opcode = 0UL;
Dcy_crypto_core_sha_v2.c594 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_v2_sha_buffers_t shaBuffers; in Cy_Crypto_Core_V2_Sha()
597 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static cy_stc_crypto_sha_state_t hashState; in Cy_Crypto_Core_V2_Sha()
Dcy_crypto_core_ecc_ecdsa.c83 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static uint8_t myKGX[CY_CRYPTO_ECC_MAX_BYTE_SIZE]; in Cy_Crypto_Core_ECC_SignHash()
85 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) static uint8_t myKGY[CY_CRYPTO_ECC_MAX_BYTE_SIZE]; in Cy_Crypto_Core_ECC_SignHash()
Dcy_crypto_core_des_v2.c57 CY_ALIGN(4)
Dcy_crypto_core_des_v1.c63 CY_ALIGN(4)
Dcy_ethif.c69 CY_ALIGN(32) static uint8_t cy_ethif_tx_desc_list[CY_ETH_DEFINE_NUM_IP][CY_ETH_DEFINE_NUM_TXQS][CY_…
76 CY_ALIGN(32) static uint8_t cy_ethif_rx_desc_list[CY_ETH_DEFINE_NUM_IP][CY_ETH_DEFINE_NUM_RXQS][((C…
84 CY_ALIGN(32) static volatile uint8_t g_tx_bdcount[CY_ETH_DEFINE_NUM_IP] = {0,};
Dcy_ipc_sema.c87 static cy_stc_ipc_sema_t cy_semaData CY_ALIGN(__SCB_DCACHE_LINE_SIZE); in Cy_IPC_Sema_Init()
/hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/
Dcy_cryptolite_ecdsa.h131 CY_ALIGN(4) uint8_t my_BARRETT_U[4*VU_BITS_TO_WORDS(BIT_SIZE+1)];
132 CY_ALIGN(4) uint8_t my_P[4*VU_BITS_TO_WORDS(BIT_SIZE)];
133 CY_ALIGN(4) uint8_t dividend[4*VU_BITS_TO_WORDS(BIT_SIZE)];
134 CY_ALIGN(4) uint8_t p_r[4*VU_BITS_TO_WORDS(BIT_SIZE)];
135 CY_ALIGN(4) uint8_t p_s[4*VU_BITS_TO_WORDS(BIT_SIZE)];
136 CY_ALIGN(4) uint8_t p_u1[4*VU_BITS_TO_WORDS(BIT_SIZE)];
137 CY_ALIGN(4) uint8_t p_u2[4*VU_BITS_TO_WORDS(BIT_SIZE)];
138 CY_ALIGN(4) uint8_t p_o[4*VU_BITS_TO_WORDS(BIT_SIZE)];
139 CY_ALIGN(4) uint8_t p_gx[4*VU_BITS_TO_WORDS(BIT_SIZE)];
140 CY_ALIGN(4) uint8_t p_gy[4*VU_BITS_TO_WORDS(BIT_SIZE)];
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Dcy_cryptolite_aes.h69 CY_ALIGN(4) uint32_t key[CY_CRYPTOLITE_AES_MAX_KEY_SIZE_U32];
72 CY_ALIGN(4) uint32_t block0[CY_CRYPTOLITE_AES_MAX_KEY_SIZE_U32];
76 CY_ALIGN(4) uint32_t block1[CY_CRYPTOLITE_AES_MAX_KEY_SIZE_U32];
80 CY_ALIGN(4) uint32_t block2[CY_CRYPTOLITE_AES_MAX_KEY_SIZE_U32];
81 CY_ALIGN(4) uint32_t block3[CY_CRYPTOLITE_AES_MAX_KEY_SIZE_U32];
85 CY_ALIGN(4) uint32_t dummy[1u];
Dcy_cryptolite_hmac.h69 CY_ALIGN(4) uint8_t ipad[CY_CRYPTOLITE_HMAC_MAX_PAD_SIZE];
70 CY_ALIGN(4) uint8_t opad[CY_CRYPTOLITE_HMAC_MAX_PAD_SIZE];
71 CY_ALIGN(4) uint8_t m0Key[CY_CRYPTOLITE_SHA256_BLOCK_SIZE];
Dcy_cryptolite_rsa.h92 CY_ALIGN(4)
128 CY_ALIGN(4) uint8_t p_buffer[CY_CRYPTOLITE_RSA_BUFFER_SIZE];
130 CY_ALIGN(4) uint32_t dummy[1u];
Dcy_crypto_core_cmac_v2.h55 CY_ALIGN(32) cy_stc_crypto_v2_cmac_state_t cmacState;
56 CY_ALIGN(32) uint8_t k[CY_CRYPTO_AES_BLOCK_SIZE];
/hal_infineon-3.6.0/core-lib/include/
Dcy_utils.h128 #define CY_ALIGN(align) __ALIGNED(align) macro
146 #define CY_ALIGN(align) __ALIGNED(align) macro
156 #define CY_ALIGN(align) CY_PRAGMA(data_alignment = align) macro
158 #define CY_ALIGN(align) __ALIGNED(align) macro
/hal_infineon-3.6.0/mtb-hal-cat1/include_pvt/
Dcyhal_ipc_impl.h129 …do { CY_SECTION_SHAREDMEM static uint8_t _cyhal_ipc_queue_pool[ITEMSIZE * NUM_ITEMS] CY_ALIGN(__SC…
142 …do { CY_SECTION_SHAREDMEM static cyhal_ipc_queue_t _cyhal_ipc_queue_handle CY_ALIGN(__SCB_DCACHE_L…
Dcyhal_hw_resources.h113 #define _CYHAL_DMA_ALIGN CY_ALIGN(8)
115 #define _CYHAL_DMA_ALIGN CY_ALIGN(__SCB_DCACHE_LINE_SIZE)
/hal_infineon-3.6.0/core-lib/
DREADME.md39 …oss compiler compatible code. Use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN attributes at the…
44 * `CY_ALIGN`
DRELEASE.md35 …oss compiler compatible code. Use the CY_NOINIT, CY_SECTION, CY_UNUSED, CY_ALIGN attributes at the…
40 * CY_ALIGN
/hal_infineon-3.6.0/mtb-hal-cat1/source/
Dcyhal_ipc.c310 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) in _cyhal_ipc_sema_init()
1058 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) in cyhal_ipc_queue_init()
1064 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) in cyhal_ipc_queue_init()
1070 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) in cyhal_ipc_queue_init()

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