1 /*
2 * Copyright 2024-2025 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 */
5 #include <zephyr/init.h>
6 #include <zephyr/device.h>
7 #include "fsl_power.h"
8 #include "fsl_clock.h"
9 #include <soc.h>
10 #include <fsl_glikey.h>
11
12 /*!< System oscillator settling time in us */
13 #define SYSOSC_SETTLING_US 220U
14 /*!< xtal frequency in Hz */
15 #define XTAL_SYS_CLK_HZ 24000000U
16
17 #if CONFIG_SOC_MIMXRT798S_CM33_CPU0
18 #define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon0))
19 #define EN_NUM 4
20 #elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
21 #define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon1))
22 #define EN_NUM 2
23 #endif
24
25 #define EDMA_EN_OFFSET 0x420
26 #define EDMA_EN_REG(instance, idx) ((uint32_t *)((uint32_t)(SYSCON_BASE) + \
27 (EDMA_EN_OFFSET) + 0x10U * (instance) + 4U * (idx)))
28
29 #define SET_UP_FLEXCOMM_CLOCK(x) \
30 do { \
31 CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x); \
32 RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn); \
33 CLOCK_EnableClock(kCLOCK_LPFlexComm##x); \
34 } while (0)
35
36 #ifdef CONFIG_SOC_MIMXRT798S_CM33_CPU0
37 #define SET_UP_CTIMER_CLOCK(x) \
38 do { \
39 CLOCK_AttachClk(kFRO0_DIV1_to_CTIMER##x); \
40 CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U); \
41 } while (0)
42 #elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
43 #define SET_UP_CTIMER_CLOCK(x) \
44 do { \
45 CLOCK_AttachClk(kFRO2_DIV1_to_CTIMER##x); \
46 CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U); \
47 } while (0)
48 #endif
49
50 const clock_main_pll_config_t g_mainPllConfig_clock_init = {
51 .main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */
52 .numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 .denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
54 .main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */
55 };
56
57 const clock_audio_pll_config_t g_audioPllConfig_clock_init = {
58 .audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */
59 .numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */
60 .denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
61 .audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */
62 .enableVcoOut = true};
63
64 static void BOARD_InitAHBSC(void);
65 #if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
66 static void edma_enable_all_request(uint8_t instance);
67 #endif
68
board_early_init_hook(void)69 void board_early_init_hook(void)
70 {
71 #if CONFIG_SOC_MIMXRT798S_CM33_CPU0
72 const clock_fro_config_t froAutotrimCfg = {
73 .targetFreq = 300000000U,
74 .range = 50U,
75 .trim1DelayUs = 15U,
76 .trim2DelayUs = 15U,
77 .refDiv = 1U,
78 .enableInt = 0U,
79 .coarseTrimEn = true,
80 };
81
82 POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
83
84 /* Power up OSC */
85 POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
86 /* Enable system OSC */
87 CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
88 /* Sets external XTAL OSC freq */
89 CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
90
91 /* Make sure FRO1 is enabled. */
92 POWER_DisablePD(kPDRUNCFG_PD_FRO1);
93
94 /* Switch to FRO1 for safe configure. */
95 CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE);
96 CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN);
97 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U);
98 CLOCK_AttachClk(kFRO1_DIV1_to_RAM);
99 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U);
100 CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
101 CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN);
102 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U);
103
104 #if CONFIG_FLASH_MCUX_XSPI_XIP
105 /* Change to common_base clock(Sourced by FRO1). */
106 xspi_clock_safe_config();
107 #endif
108
109 /* Ungate all FRO clock. */
110 POWER_DisablePD(kPDRUNCFG_GATE_FRO0);
111 /* Use close loop mode. */
112 CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn);
113 /* Enable FRO0 MAX clock for all domains.*/
114 CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable);
115
116 CLOCK_InitMainPll(&g_mainPllConfig_clock_init);
117 CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475 MHz */
118 CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396 MHz */
119 CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528 MHz */
120 /* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500 MHz -need 2 div -> 250 MHz*/
121 CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U);
122
123 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable);
124 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
125 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable);
126 CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
127
128 CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U);
129 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 237.5 MHz */
130
131 CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
132 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 237.5 MHz */
133
134 CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U);
135 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 237.5 MHz */
136
137 CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U);
138 CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 237.5 MHz */
139
140 CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U);
141 CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */
142
143 /* Configure Audio PLL clock source. */
144 CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */
145 CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */
146 CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
147 CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
148 CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
149
150 #if CONFIG_FLASH_MCUX_XSPI_XIP
151 /* Call function xspi_setup_clock() to set user configured clock for XSPI. */
152 xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
153 #endif /* CONFIG_FLASH_MCUX_XSPI_XIP */
154
155 #elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
156 /* Power up OSC in case it's not enabled. */
157 POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
158 /* Enable system OSC */
159 CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
160 /* Sets external XTAL OSC freq */
161 CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
162
163 CLOCK_AttachClk(kFRO1_DIV3_to_SENSE_BASE);
164 CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
165 CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
166
167 POWER_DisablePD(kPDRUNCFG_GATE_FRO2);
168 CLOCK_EnableFroClkFreq(FRO2, 300000000U, kCLOCK_FroAllOutEn);
169
170 CLOCK_EnableFro2ClkForDomain(kCLOCK_AllDomainEnable);
171
172 CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE);
173 CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
174 CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
175 #endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */
176
177 BOARD_InitAHBSC();
178
179 #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay)
180 CLOCK_EnableClock(kCLOCK_Dma0);
181 RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn);
182 edma_enable_all_request(0);
183 #endif
184
185 #if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay)
186 CLOCK_EnableClock(kCLOCK_Dma1);
187 RESET_ClearPeripheralReset(kDMA1_RST_SHIFT_RSTn);
188 edma_enable_all_request(1);
189 #endif
190
191 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon), okay)
192 RESET_ClearPeripheralReset(kIOPCTL0_RST_SHIFT_RSTn);
193 CLOCK_EnableClock(kCLOCK_Iopctl0);
194 #endif
195
196 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon1), okay)
197 RESET_ClearPeripheralReset(kIOPCTL1_RST_SHIFT_RSTn);
198 CLOCK_EnableClock(kCLOCK_Iopctl1);
199 #endif
200
201 #if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon2), okay)
202 RESET_ClearPeripheralReset(kIOPCTL2_RST_SHIFT_RSTn);
203 CLOCK_EnableClock(kCLOCK_Iopctl2);
204 #endif
205
206 #ifdef CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
207 CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
208 CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U);
209 #endif
210
211 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay)
212 SET_UP_FLEXCOMM_CLOCK(0);
213 #endif
214
215 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
216 SET_UP_FLEXCOMM_CLOCK(1);
217 #endif
218
219 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
220 SET_UP_FLEXCOMM_CLOCK(2);
221 #endif
222
223 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
224 SET_UP_FLEXCOMM_CLOCK(3);
225 #endif
226
227 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
228 SET_UP_FLEXCOMM_CLOCK(4);
229 #endif
230
231 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
232 SET_UP_FLEXCOMM_CLOCK(5);
233 #endif
234
235 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm6), okay)
236 SET_UP_FLEXCOMM_CLOCK(6);
237 #endif
238
239 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm7), okay)
240 SET_UP_FLEXCOMM_CLOCK(7);
241 #endif
242
243 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm8), okay)
244 SET_UP_FLEXCOMM_CLOCK(8);
245 #endif
246
247 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm9), okay)
248 SET_UP_FLEXCOMM_CLOCK(9);
249 #endif
250
251 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm10), okay)
252 SET_UP_FLEXCOMM_CLOCK(10);
253 #endif
254
255 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm11), okay)
256 SET_UP_FLEXCOMM_CLOCK(11);
257 #endif
258
259 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm12), okay)
260 SET_UP_FLEXCOMM_CLOCK(12);
261 #endif
262
263 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm13), okay)
264 SET_UP_FLEXCOMM_CLOCK(13);
265 #endif
266
267 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi14), okay)
268 CLOCK_AttachClk(kFRO1_DIV1_to_LPSPI14);
269 CLOCK_SetClkDiv(kCLOCK_DivLpspi14Clk, 3U);
270 CLOCK_EnableClock(kCLOCK_LPSpi14);
271 RESET_ClearPeripheralReset(kLPSPI14_RST_SHIFT_RSTn);
272 #endif
273
274 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c15), okay)
275 CLOCK_EnableClock(kCLOCK_LPI2c15);
276 RESET_ClearPeripheralReset(kLPI2C15_RST_SHIFT_RSTn);
277 #endif
278
279 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi16), okay)
280 CLOCK_AttachClk(kFRO0_DIV1_to_LPSPI16);
281 CLOCK_SetClkDiv(kCLOCK_DivLpspi16Clk, 1U);
282 CLOCK_EnableClock(kCLOCK_LPSpi16);
283 RESET_ClearPeripheralReset(kLPSPI16_RST_SHIFT_RSTn);
284 #endif
285
286 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm17), okay)
287 CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM17);
288 CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm17Clk, 4U);
289 #endif
290
291 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm18), okay)
292 CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM18);
293 CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm18Clk, 4U);
294 #endif
295
296 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm19), okay)
297 CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM19);
298 CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm19Clk, 4U);
299 #endif
300
301 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm20), okay)
302 CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM20);
303 CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm20Clk, 4U);
304 #endif
305
306 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio), okay)
307 CLOCK_AttachClk(kFRO0_DIV1_to_FLEXIO);
308 CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1U);
309 #endif
310
311 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
312 CLOCK_EnableClock(kCLOCK_Gpio0);
313 RESET_ClearPeripheralReset(kGPIO0_RST_SHIFT_RSTn);
314 #endif
315
316 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
317 CLOCK_EnableClock(kCLOCK_Gpio1);
318 RESET_ClearPeripheralReset(kGPIO1_RST_SHIFT_RSTn);
319 #endif
320
321 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
322 CLOCK_EnableClock(kCLOCK_Gpio2);
323 RESET_ClearPeripheralReset(kGPIO2_RST_SHIFT_RSTn);
324 #endif
325
326 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
327 CLOCK_EnableClock(kCLOCK_Gpio3);
328 RESET_ClearPeripheralReset(kGPIO3_RST_SHIFT_RSTn);
329 #endif
330
331 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
332 CLOCK_EnableClock(kCLOCK_Gpio4);
333 RESET_ClearPeripheralReset(kGPIO4_RST_SHIFT_RSTn);
334 #endif
335
336 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
337 CLOCK_EnableClock(kCLOCK_Gpio5);
338 RESET_ClearPeripheralReset(kGPIO5_RST_SHIFT_RSTn);
339 #endif
340
341 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
342 CLOCK_EnableClock(kCLOCK_Gpio6);
343 RESET_ClearPeripheralReset(kGPIO6_RST_SHIFT_RSTn);
344 #endif
345
346 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
347 CLOCK_EnableClock(kCLOCK_Gpio7);
348 RESET_ClearPeripheralReset(kGPIO7_RST_SHIFT_RSTn);
349 #endif
350
351 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay)
352 CLOCK_EnableClock(kCLOCK_Gpio8);
353 RESET_ClearPeripheralReset(kGPIO8_RST_SHIFT_RSTn);
354 #endif
355
356 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay)
357 CLOCK_EnableClock(kCLOCK_Gpio9);
358 RESET_ClearPeripheralReset(kGPIO9_RST_SHIFT_RSTn);
359 #endif
360
361 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio10), okay)
362 CLOCK_EnableClock(kCLOCK_Gpio10);
363 RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn);
364 #endif
365
366 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
367 SET_UP_CTIMER_CLOCK(0);
368 #endif
369
370 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
371 SET_UP_CTIMER_CLOCK(1);
372 #endif
373
374 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
375 SET_UP_CTIMER_CLOCK(2);
376 #endif
377
378 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
379 SET_UP_CTIMER_CLOCK(3);
380 #endif
381
382 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
383 SET_UP_CTIMER_CLOCK(4);
384 #endif
385
386 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer5), okay)
387 SET_UP_CTIMER_CLOCK(5);
388 #endif
389
390 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer6), okay)
391 SET_UP_CTIMER_CLOCK(6);
392 #endif
393
394 #if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer7), okay)
395 SET_UP_CTIMER_CLOCK(7);
396 #endif
397
398 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay)
399 CLOCK_AttachClk(kFRO1_DIV1_to_SENSE_MAIN);
400 CLOCK_AttachClk(kSENSE_BASE_to_ADC);
401 CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1U);
402 #endif
403
404 #if (DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer_cpu0), okay) || \
405 DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer_cpu1), okay))
406 CLOCK_AttachClk(kLPOSC_to_OSTIMER);
407 CLOCK_SetClkDiv(kCLOCK_DivOstimerClk, 1U);
408 #endif
409
410 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb0)) && CONFIG_UDC_NXP_EHCI
411 /* Power on usb ram array as need, powered USB0RAM array*/
412 POWER_DisablePD(kPDRUNCFG_APD_USB0_SRAM);
413 POWER_DisablePD(kPDRUNCFG_PPD_USB0_SRAM);
414 /* Apply the config */
415 POWER_ApplyPD();
416 /* disable the read and write gate */
417 SYSCON4->USB0_MEM_CTRL |= (SYSCON4_USB0_MEM_CTRL_MEM_WIG_MASK |
418 SYSCON4_USB0_MEM_CTRL_MEM_RIG_MASK |
419 SYSCON4_USB0_MEM_CTRL_MEM_STDBY_MASK);
420 /* Enable the USBPHY0 CLOCK */
421 SYSCON4->USBPHY0_CLK_ACTIVE |= SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_MASK;
422 CLOCK_AttachClk(k32KHZ_WAKE_to_USB);
423 CLOCK_AttachClk(kOSC_CLK_to_USB_24MHZ);
424 CLOCK_EnableClock(kCLOCK_Usb0);
425 CLOCK_EnableClock(kCLOCK_UsbphyRef);
426 RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
427 RESET_PeripheralReset(kUSBPHY0_RST_SHIFT_RSTn);
428 CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, usbClockFreq);
429 CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, usbClockFreq);
430 #endif
431
432 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
433 CLOCK_AttachClk(kLPOSC_to_WWDT0);
434 #endif
435
436 #if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay)
437 CLOCK_AttachClk(kFRO0_DIV6_to_SCT);
438 #endif
439 }
440
GlikeyWriteEnable(GLIKEY_Type * base,uint8_t idx)441 static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
442 {
443 (void)GLIKEY_SyncReset(base);
444
445 (void)GLIKEY_StartEnable(base, idx);
446 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1);
447 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2);
448 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3);
449 (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN);
450 }
451
GlikeyClearConfig(GLIKEY_Type * base)452 static void GlikeyClearConfig(GLIKEY_Type *base)
453 {
454 (void)GLIKEY_SyncReset(base);
455 }
456
457 /* Disable the secure check for AHBSC and enable periperhals/sram access for masters */
BOARD_InitAHBSC(void)458 static void BOARD_InitAHBSC(void)
459 {
460 #if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
461 GlikeyWriteEnable(GLIKEY0, 1U);
462 AHBSC0->MISC_CTRL_DP_REG = 0x000086aa;
463 /* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */
464 AHBSC0->MISC_CTRL_REG = 0x000086aa;
465
466 GlikeyWriteEnable(GLIKEY0, 7U);
467 /* Enable arbiter0 accessing SRAM */
468 AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
469 AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
470 AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
471 AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
472 AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
473 #endif
474
475 GlikeyWriteEnable(GLIKEY1, 1U);
476 AHBSC3->MISC_CTRL_DP_REG = 0x000086aa;
477 /* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/
478 AHBSC3->MISC_CTRL_REG = 0x000086aa;
479
480 GlikeyWriteEnable(GLIKEY1, 9U);
481 /* Enable arbiter1 accessing SRAM */
482 AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
483 AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
484 AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
485 AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
486 AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
487 AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
488
489 GlikeyWriteEnable(GLIKEY1, 8U);
490 /* Access enable for COMPUTE domain masters to common APB peripherals.*/
491 AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
492 AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
493 GlikeyWriteEnable(GLIKEY1, 7U);
494 AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
495 AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
496
497 GlikeyWriteEnable(GLIKEY2, 1U);
498 /*Disable secure and secure privilege checking. */
499 AHBSC4->MISC_CTRL_DP_REG = 0x000086aa;
500 AHBSC4->MISC_CTRL_REG = 0x000086aa;
501
502 #if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
503 GlikeyClearConfig(GLIKEY0);
504 #endif
505 GlikeyClearConfig(GLIKEY1);
506 GlikeyClearConfig(GLIKEY2);
507 }
508
509 #if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
edma_enable_all_request(uint8_t instance)510 static void edma_enable_all_request(uint8_t instance)
511 {
512 uint32_t *reg;
513
514 for (uint8_t idx = 0; idx < EN_NUM; idx++) {
515 reg = EDMA_EN_REG(instance, idx);
516 *reg |= 0xFFFFFFFF;
517 }
518 }
519 #endif
520
