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Searched refs:sel0Active (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c278 CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active)); in Cy_GPIO_Port_Init()
317 …_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active); in Cy_GPIO_Port_Init()
333 …A_REG32_SET(CY_PRA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Active); in Cy_GPIO_Port_Init()
338 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active; in Cy_GPIO_Port_Init()
342 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active; in Cy_GPIO_Port_Init()
354 HSIOM_PRT_PORT_SEL0(baseHSIOM) = config->sel0Active; in Cy_GPIO_Port_Init()
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/
Dcy_gpio.h306 uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */ member