Searched refs:regs (Results 1 – 5 of 5) sorted by relevance
222 XMC_ASSERT("XMC_ETH_MAC_InitEx: eth_mac is invalid", XMC_ETH_MAC_IsValidModule(eth_mac->regs)); in XMC_ETH_MAC_InitEx()227 eth_mac->regs->MAC_CONFIGURATION = (uint32_t)ETH_MAC_CONFIGURATION_IPC_Msk; in XMC_ETH_MAC_InitEx()230 eth_mac->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk; /* Disable Zero Quanta Pause */ in XMC_ETH_MAC_InitEx()232 eth_mac->regs->OPERATION_MODE = (uint32_t)ETH_OPERATION_MODE_RSF_Msk | in XMC_ETH_MAC_InitEx()237 eth_mac->regs->BUS_MODE = (uint32_t)ETH_BUS_MODE_ATDS_Msk | in XMC_ETH_MAC_InitEx()247 eth_mac->regs->STATUS = 0xFFFFFFFFUL; in XMC_ETH_MAC_InitEx()250 eth_mac->regs->MMC_TRANSMIT_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; in XMC_ETH_MAC_InitEx()251 eth_mac->regs->MMC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_INTERRUPT_MSK; in XMC_ETH_MAC_InitEx()252 eth_mac->regs->MMC_IPC_RECEIVE_INTERRUPT_MASK = ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK; in XMC_ETH_MAC_InitEx()255 eth_mac->regs->INTERRUPT_MASK = ETH_INTERRUPT_MASK_PMTIM_Msk | ETH_INTERRUPT_MASK_TSIM_Msk; in XMC_ETH_MAC_InitEx()[all …]
378 ETH_GLOBAL_TypeDef *regs; /**< ETH module 0 (now, we have a single ETH module) */ member510 eth_mac->regs->BUS_MODE |= (uint32_t)ETH_BUS_MODE_SWR_Msk; in XMC_ETH_MAC_Reset()511 while ((eth_mac->regs->BUS_MODE & (uint32_t)ETH_BUS_MODE_SWR_Msk) != 0U) in XMC_ETH_MAC_Reset()600 eth_mac->regs->MAC_ADDRESS0_HIGH = (uint32_t)(addr >> 32); in XMC_ETH_MAC_SetAddress()601 eth_mac->regs->MAC_ADDRESS0_LOW = (uint32_t)addr; in XMC_ETH_MAC_SetAddress()630 …return ((((uint64_t)eth_mac->regs->MAC_ADDRESS0_HIGH << 32)) | (uint64_t)eth_mac->regs->MAC_ADDRES… in XMC_ETH_MAC_GetAddress()705 eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_RA_Msk; in XMC_ETH_MAC_EnableFrameFilter()722 eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_RA_Msk; in XMC_ETH_MAC_DisableFrameFilter()739 eth_mac->regs->MAC_FRAME_FILTER |= (uint32_t)ETH_MAC_FRAME_FILTER_HPF_Msk; in XMC_ETH_MAC_EnableHashPerfectFilter()755 eth_mac->regs->MAC_FRAME_FILTER &= (uint32_t)~ETH_MAC_FRAME_FILTER_HPF_Msk; in XMC_ETH_MAC_EnablePerfectFilter()[all …]
1903 void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs) in Cy_SysPm_SaveRegisters() argument1905 CY_ASSERT_L1(NULL != regs); in Cy_SysPm_SaveRegisters()1908 regs->CY_SYSPM_CM0_CLOCK_CTL_REG = CPUSS_CM0_CLOCK_CTL; in Cy_SysPm_SaveRegisters()1909 regs->CY_SYSPM_CM4_CLOCK_CTL_REG = CPUSS_CM4_CLOCK_CTL; in Cy_SysPm_SaveRegisters()1913 regs->CY_SYSPM_UDB_UDBIF_BANK_CTL_REG = UDB_UDBIF_BANK_CTL; in Cy_SysPm_SaveRegisters()1915 regs->CY_SYSPM_UDB_BCTL_MDCLK_EN_REG = UDB_BCTL_MDCLK_EN; in Cy_SysPm_SaveRegisters()1916 regs->CY_SYSPM_UDB_BCTL_MBCLK_EN_REG = UDB_BCTL_MBCLK_EN; in Cy_SysPm_SaveRegisters()1917 regs->CY_SYSPM_UDB_BCTL_BOTSEL_L_REG = UDB_BCTL_BOTSEL_L; in Cy_SysPm_SaveRegisters()1918 regs->CY_SYSPM_UDB_BCTL_BOTSEL_U_REG = UDB_BCTL_BOTSEL_U; in Cy_SysPm_SaveRegisters()1919 regs->CY_SYSPM_UDB_BCTL_QCLK_EN0_REG = UDB_BCTL_QCLK_EN_0; in Cy_SysPm_SaveRegisters()[all …]
3987 void Cy_SysPm_SaveRegisters(cy_stc_syspm_backup_regs_t *regs);4022 void Cy_SysPm_RestoreRegisters(cy_stc_syspm_backup_regs_t const *regs);
130 ; These IRQs can only be triggered by SW via NVIC regs
