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Searched refs:lpPllCfg (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_sysclk_v2.c4024 manualConfig.lpPllCfg->feedbackDiv = (uint8_t)p; in Cy_SysClk_DpllLpConfigure()
4025 manualConfig.lpPllCfg->referenceDiv = (uint8_t)q; in Cy_SysClk_DpllLpConfigure()
4026 manualConfig.lpPllCfg->outputDiv = (uint8_t)out; in Cy_SysClk_DpllLpConfigure()
4027 manualConfig.lpPllCfg->fracEn = true; in Cy_SysClk_DpllLpConfigure()
4028 manualConfig.lpPllCfg->fracDiv = feedBackFracDiv; in Cy_SysClk_DpllLpConfigure()
4046 manualConfig.lpPllCfg->outputMode = config->outputMode; in Cy_SysClk_DpllLpConfigure()
4074 …else if ((config->lpPllCfg->outputDiv < CY_SYSCLK_DPLL_LP_MIN_OUTPUT_DIV) || (CY_SYSCLK_DPLL_LP… in Cy_SysClk_DpllLpManualConfigure()
4075 …(config->lpPllCfg->referenceDiv < CY_SYSCLK_DPLL_LP_MIN_REF_DIV) || (CY_SYSCLK_DPLL_LP_MAX_REF_… in Cy_SysClk_DpllLpManualConfigure()
4076 …(config->lpPllCfg->feedbackDiv < CY_SYSCLK_DPLL_LP_MIN_FB_DIV) || (CY_SYSCLK_DPLL_LP_MAX_FB_D… in Cy_SysClk_DpllLpManualConfigure()
4084 if (config->lpPllCfg->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_DpllLpManualConfigure()
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/hal_infineon-3.5.0/mtb-hal-cat1/source/
Dcyhal_clock.c1600 *feedbackDiv = cfg->lpPllCfg->feedbackDiv; in _cyhal_clock_extract_pll_params()
1601 *referenceDiv = cfg->lpPllCfg->referenceDiv; in _cyhal_clock_extract_pll_params()
1602 *outputDiv = cfg->lpPllCfg->outputDiv; in _cyhal_clock_extract_pll_params()
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2206 cy_stc_dpll_lp_config_t *lpPllCfg; /**< DPLL-LP configuration */ member