1 /***************************************************************************//**
2 * \file cy_syslib.h
3 * \version 3.40
4 *
5 * Provides an API declaration of the SysLib driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_syslib
28 * \{
29 * The system libraries provide APIs that can be called in the user application
30 * to handle the timing, logical checking or register.
31 *
32 * The functions and other declarations used in this driver are in cy_syslib.h.
33 * You can include cy_pdl.h to get access to all functions
34 * and declarations in the PDL.
35 *
36 * The SysLib driver contains a set of different system functions. These functions
37 * can be called in the application routine. Major features of the system library:
38 * * Delay functions
39 * * The register Read/Write macro
40 * * Assert and Halt
41 * * Assert Classes and Levels
42 * * A software reset
43 * * Reading the reset cause
44 * * An API to invalidate the flash cache and buffer
45 * * Data manipulation macro
46 * * A variable type definition from MISRA-C which specifies signedness
47 * * Cross compiler compatible attributes
48 * * Getting a silicon-unique ID API
49 * * Setting wait states API
50 * * Resetting the backup domain API
51 * * APIs to serve Fault handler
52 *
53 * \section group_syslib_configuration Configuration Considerations
54 * <b> Assertion Usage </b> <br />
55 * Use the CY_ASSERT() macro to check expressions that must be true if the
56 * program is running correctly. It is a convenient way to insert sanity checks.
57 * The CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
58 * <a href="https://github.com/Infineon/core-lib">Cypress Core Library (core-lib)</a>.
59 * The macro behavior is as follows: if the expression passed
60 * to the macro is false, the CPU is halted. \n
61 *
62 * Starting from the driver version 2.50, the CY_ASSERT macro was moved
63 * to the Cypress Core Library (core-lib). Also, the CY_ASSERT implementation
64 * was changed not to call Cy_SysLib_AssertFailed() function, so user application
65 * that relied on that should take this change into account. \n
66 *
67 *
68 * The PDL source code uses this assert mechanism extensively. It is recommended
69 * that you enable asserts when debugging firmware. \n
70 * <b> Assertion Classes and Levels </b> <br />
71 * The <a href="https://github.com/Infineon/core-lib">Cypress Core Library</a>
72 * defines three assert classes, which correspond to different
73 * kinds of parameters. There is a corresponding assert "level" for each class.
74 * <table class="doxtable">
75 * <tr><th>Class Macro</th><th>Level Macro</th><th>Type of check</th></tr>
76 * <tr>
77 * <td>CY_ASSERT_CLASS_1</td>
78 * <td>CY_ASSERT_L1</td>
79 * <td>A parameter that could change between different PSoC devices
80 * (e.g. the number of clock paths)</td>
81 * </tr>
82 * <tr>
83 * <td>CY_ASSERT_CLASS_2</td>
84 * <td>CY_ASSERT_L2</td>
85 * <td>A parameter that has fixed limits such as a counter period</td>
86 * </tr>
87 * <tr>
88 * <td>CY_ASSERT_CLASS_3</td>
89 * <td>CY_ASSERT_L3</td>
90 * <td>A parameter that is an enum constant</td>
91 * </tr>
92 * </table>
93 * Firmware defines which ASSERT class is enabled by defining CY_ASSERT_LEVEL.
94 * This is a compiler command line argument, similar to how the DEBUG / NDEBUG
95 * macro is passed. \n
96 * Enabling any class also enables any lower-numbered class.
97 * CY_ASSERT_CLASS_3 is the default level, and it enables asserts for all three
98 * classes. The following example shows the command-line option to enable all
99 * the assert levels:
100 * \code -D CY_ASSERT_LEVEL=CY_ASSERT_CLASS_3 \endcode
101 * \note The use of special characters, such as spaces, parenthesis, etc. must
102 * be protected with quotes.
103 *
104 * After CY_ASSERT_LEVEL is defined, firmware can use
105 * one of the three level macros to make an assertion. For example, if the
106 * parameter can vary between devices, firmware uses the L1 macro.
107 * \code CY_ASSERT_L1(clkPath < SRSS_NUM_CLKPATH); \endcode
108 * If the parameter has bounds, firmware uses L2.
109 * \code CY_ASSERT_L2(trim <= CY_CTB_TRIM_VALUE_MAX); \endcode
110 * If the parameter is an enum, firmware uses L3.
111 * \code CY_ASSERT_L3(config->LossAction <= CY_SYSCLK_CSV_ERROR_FAULT_RESET); \endcode
112 * Each check uses the appropriate level macro for the kind of parameter being checked.
113 * If a particular assert class/level is not enabled, then the assert does nothing.
114 *
115 * \section group_syslib_more_information More Information
116 * Refer to the technical reference manual (TRM).
117 *
118 * \section group_syslib_changelog Changelog
119 * <table class="doxtable">
120 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
121 * <tr>
122 * <td rowspan="2">3.40</td>
123 * <td>
124 * Newly added API \ref Cy_SysLib_GetDeviceLCS and enum \ref cy_en_syslib_lcs_mode_t
125 * </td>
126 * <td>Support of LCS added for CAT1D devices .</td>
127 * </tr>
128 * <tr>
129 * <td>Updated API \ref Cy_SysLib_SetWaitStates and added new macros.</td>
130 * <td>Enabled wait-states API for CAT1C devices.</td>
131 * </tr>
132 * <tr>
133 * <td>3.30</td>
134 * <td>Added \ref Cy_SysLib_IsDSRAMWarmBootEntry and \ref Cy_SysLib_ClearDSRAMWarmBootEntryStatus APIs.</td>
135 * <td>DEEPSLEEP-RAM support added for CAT1B Devices.</td>
136 * </tr>
137 * <tr>
138 * <td>3.20</td>
139 * <td>Updated Cy_SysLib_Delay() to perform correctly, enable Cy_SysLib_GetUniqueId() API for CAT1B,
140 * coverity fixes and documentation enhancements. \n
141 * Added CY_SECTION_INIT_CODECOPY_START and CY_SECTION_INIT_CODECOPY_END macro
142 * to move block of code from flash to sram during startup init. Currently
143 * it only supports in IAR build.</td>
144 * <td>Bug Fixes and Enhancements.</td>
145 * </tr>
146 * <tr>
147 * <td>3.10</td>
148 * <td>CAT1B, CAT1C, CAT1D devices support.<br>Added new API Cy_Syslib_SetWarmBootEntryPoint()
149 * to set the warm boot entry point address to a location read by BootROM.<br>
150 * To get the accurate delay, updated Cy_SysLib_Delay(), Cy_SysLib_DelayUs() with a calibration factor.</td>
151 * <td>Support for new devices.</td>
152 * </tr>
153 * <tr>
154 * <td>3.0</td>
155 * <td>Updated \ref Cy_SysLib_SoftResetCM4 to perform correctly when function is called multiple times.</td>
156 * <td>Fixed issue which caused IPC Message to Fail if API is called more than once.</td>
157 * </tr>
158 * <tr>
159 * <td rowspan="2">2.90</td>
160 * <td>Added new functions \ref Cy_SysLib_Rtos_Delay, \ref Cy_SysLib_Rtos_DelayUs.</td>
161 * <td>Provide user an option to overwrite delay function implementation based on target RTOS environment.</td>
162 * </tr>
163 * <tr>
164 * <td>Added new functions \ref Cy_SysLib_GetResetStatus, \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim.</td>
165 * <td>Add a possibility to manage the backup domain reset better and to store/restore the WCO trimming value.</td>
166 * </tr>
167 * <tr>
168 * <td rowspan="2">2.80</td>
169 * <td>Support for CM33.</td>
170 * <td>New devices support.</td>
171 * </tr>
172 * <tr>
173 * <td>Update \ref Cy_SysLib_GetResetReason API to read RES_CAUSE2 register as well.</td>
174 * <td>Code Enhancement/Bug Fix.</td>
175 * </tr>
176 * <tr>
177 * <td rowspan="4">2.70</td>
178 * <td>Added new macros CY_SECTION_RAMFUNC_BEGIN, CY_SECTION_RAMFUNC_END,
179 * CY_SECTION_SHAREDMEM to enable overriding of the linker section placement.</td>
180 * <td>Enhancement based on usability feedback.</td>
181 * </tr>
182 * <tr>
183 * <td>Noted that implementation of CY_ASSERT() was changed back in version 2.50,
184 * so that Cy_SysLib_AssertFailed() function is not called and user application
185 * may need to be updated.</td>
186 * <td>Documentation update.</td>
187 * </tr>
188 * <tr>
189 * <td>Removed the issue related to the malloc() failure to report error for the case when
190 * requested allocation size is bigger than the heap size.
191 * Refer to the \ref group_system_config_heap_stack_config_gcc section for the more details.
192 * Removed empty Known Issues section.
193 * <td>Documentation update and clarification.</td>
194 * </tr>
195 * <tr>
196 * <td>Fixed/Documented MISRA 2012 violations.</td>
197 * <td>MISRA 2012 compliance.</td>
198 * </tr>
199 * <tr>
200 * <td>2.60.1</td>
201 * <td>Updated the Configuration Considerations section with the information that
202 * CY_ASSERT() macro is defined in the cy_utils.h file, which is part of the
203 * <a href="https://github.com/Infineon/core-lib">Cypress Core Library (core-lib)</a>
204 * <td>Documentation update and clarification.</td>
205 * </tr>
206 * <tr>
207 * <td rowspan="2">2.60</td>
208 * <td>Updated the following functions for the PSoC 64 devices:
209 * \ref Cy_SysLib_ClearFlashCacheAndBuffer, \ref Cy_SysLib_ClearResetReason,
210 * \ref Cy_SysLib_SetWaitStates.
211 * <td>Added PSoC 64 device support.</td>
212 * </tr>
213 * <tr>
214 * <td>Minor documentation updates.</td>
215 * <td>Documentation enhancement.</td>
216 * </tr>
217 * <tr>
218 * <td>2.50.3</td>
219 * <td>Add section Known Issues
220 * <td>Documentation update and clarification.</td>
221 * </tr>
222 * <tr>
223 * <td>2.50.1</td>
224 * <td>Used the core library defines for the message codes forming.
225 * <td>Improve PDL code base.</td>
226 * </tr>
227 * <tr>
228 * <td>2.50</td>
229 * <td>Moved following macros to the core library:
230 * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32,
231 * CY_SWAP_ENDIAN64,CY_GET_REG8,CY_SET_REG8,CY_GET_REG16,CY_SET_REG16,
232 * CY_GET_REG24,CY_SET_REG24,CY_GET_REG32,CY_SET_REG32,_CLR_SET_FLD32U,
233 * CY_REG32_CLR_SET,_CLR_SET_FLD16U,CY_REG16_CLR_SET,_CLR_SET_FLD8U,
234 * CY_REG8_CLR_SET,_BOOL2FLD,_FLD2BOOL,CY_SYSLIB_DIV_ROUND,
235 * CY_SYSLIB_DIV_ROUNDUP,CY_NOINIT,CY_SECTION,CY_UNUSED,CY_NOINLINE,
236 * CY_ALIGN,CY_RAMFUNC_BEGIN,CY_RAMFUNC_END.
237 * Use at least version 1.1 of the core library: https://github.com/Infineon/core-lib.
238 * <td>Improve PDL code base.</td>
239 * </tr>
240 * <tr>
241 * <td>2.40.1</td>
242 * <td>Correct the CY_RAMFUNC_BEGIN macro for the IAR compiler.</td>
243 * <td>Removed the IAR compiler warning.</td>
244 * </tr>
245 * <tr>
246 * <td>2.40</td>
247 * <td>Added new macros CY_SYSLIB_DIV_ROUND and CY_SYSLIB_DIV_ROUNDUP to easy perform integer division with rounding.</td>
248 * <td>Improve PDL code base.</td>
249 * </tr>
250 * <tr>
251 * <td rowspan="3">2.30</td>
252 * <td>Updated implementation of the Cy_SysLib_AsmInfiniteLoop() function to be compatible with ARMC6.</td>
253 * <td>Provided support for the ARM Compiler 6.</td>
254 * </tr>
255 * <tr>
256 * <td>Minor documentation edits.</td>
257 * <td>Documentation update and clarification.</td>
258 * </tr>
259 * <tr>
260 * <td>Added new macros CY_RAMFUNC_BEGIN and CY_RAMFUNC_END for convenient placement function in RAM for all supported compilers.</td>
261 * <td>Improve user experience.</td>
262 * </tr>
263 * <tr>
264 * <td rowspan="2">2.20</td>
265 * <td>Updated implementation of the \ref Cy_SysLib_AssertFailed() function to be available in Release and Debug modes.</td>
266 * <td>Provided support for the PDL static library in Release mode.</td>
267 * </tr>
268 * <tr>
269 * <td>Minor documentation edits.</td>
270 * <td>Documentation update and clarification.</td>
271 * </tr>
272 * <tr>
273 * <td rowspan="4">2.10</td>
274 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
275 * <td>Driver library directory-structure simplification.</td>
276 * </tr>
277 * <tr>
278 * <td>Added the following macros: CY_REG32_CLR_SET, _CLR_SET_FLD16U, CY_REG16_CLR_SET, _CLR_SET_FLD8U, CY_REG8_CLR_SET</td>
279 * <td>Register access simplification.</td>
280 * </tr>
281 * <tr>
282 * <td>Removed the Cy_SysLib_GetNumHfclkResetCause API function.</td>
283 * <td>This feature is not supported by SRSS_ver1.</td>
284 * </tr>
285 * <tr>
286 * <td>Added register access layer. Use register access macros instead
287 * of direct register access using dereferenced pointers.</td>
288 * <td>Makes register access device-independent, so that the PDL does
289 * not need to be recompiled for each supported part number.</td>
290 * </tr>
291 * <tr>
292 * <td>2.0.1</td>
293 * <td>Minor documentation edits</td>
294 * <td>Documentation update and clarification</td>
295 * </tr>
296 * <tr>
297 * <td rowspan="4"> 2.0</td>
298 * <td>
299 * Added Cy_SysLib_ResetBackupDomain() API implementation. \n
300 * Added CY_NOINLINE attribute implementation. \n
301 * Added DIE_YEAR field to 64-bit unique ID return value of Cy_SysLib_GetUniqueId() API. \n
302 * Added storing of SCB->HFSR, SCB->SHCSR registers and SCB->MMFAR, SCB->BFAR addresses to Fault Handler debug structure. \n
303 * Optimized Cy_SysLib_SetWaitStates() API implementation.
304 * </td>
305 * <td>Improvements made based on usability feedback.</td>
306 * </tr>
307 * <tr>
308 * <td>Added Assertion Classes and Levels.</td>
309 * <td>For error checking, parameter validation and status returns in the PDL API.</td>
310 * </tr>
311 * <tr>
312 * <td>Applied CY_NOINIT attribute to cy_assertFileName, cy_assertLine, and cy_faultFrame global variables.</td>
313 * <td>To store debug information into a non-zero init area for future analysis.</td>
314 * </tr>
315 * <tr>
316 * <td>Removed CY_WEAK attribute implementation.</td>
317 * <td>CMSIS __WEAK attribute should be used instead.</td>
318 * </tr>
319 * <tr>
320 * <td>1.0</td>
321 * <td>Initial version</td>
322 * <td></td>
323 * </tr>
324 * </table>
325 *
326 * \defgroup group_syslib_macros Macros
327 * \defgroup group_syslib_functions Functions
328 * \defgroup group_syslib_data_structures Data Structures
329 * \defgroup group_syslib_enumerated_types Enumerated Types
330 *
331 */
332
333 #if !defined (CY_SYSLIB_H)
334 #define CY_SYSLIB_H
335
336 #include "cy_device.h"
337
338 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M4CPUSS) || defined (CY_IP_M7CPUSS) || defined(CY_IP_M55APPCPUSS)
339
340 #include <stdint.h>
341 #include <stdbool.h>
342 #include "cy_utils.h"
343 #include "cy_result.h"
344
345 #if defined(__cplusplus)
346 extern "C" {
347 #endif /* defined(__cplusplus) */
348
349 #if defined( __ICCARM__ )
350 /* Suppress the warning for multiple volatile variables in an expression. */
351 /* This is common for driver's code and the usage is not order-dependent. */
352 #pragma diag_suppress=Pa082
353 #endif /* defined( __ICCARM__ ) */
354
355 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 8.6', 3, \
356 'Coverity does not check the .S assembly files, the definition is a part of syslib assembly source file.')
357
358 /**
359 * \addtogroup group_syslib_macros
360 * \{
361 */
362
363 /******************************************************************************
364 * Macros
365 *****************************************************************************/
366
367 /** The macro for ARM CORTEX CM0P */
368 #define CY_CPU_CORTEX_M0P (__CORTEX_M == 0U) /**< CM0+ core CPU Code */
369 /** The macro for ARM CORTEX CM4 */
370 #define CY_CPU_CORTEX_M4 (__CORTEX_M == 4U) /**< CM4 core CPU Code */
371 /** The macro for ARM CORTEX CM7 */
372 #define CY_CPU_CORTEX_M7 (__CORTEX_M == 7U) /**< CM7 core CPU Code */
373 /** The macro for ARM CORTEX CM55 */
374 #define CY_CPU_CORTEX_M55 (__CORTEX_M == 55U) /**< CM55 core CPU Code */
375 /** The macro for ARM CORTEX CM33 */
376 #define CY_CPU_CORTEX_M33 (__CORTEX_M == 33U) /**< CM33 core CPU Code */
377
378 /** The macro to enable the Fault Handler */
379 #define CY_ARM_FAULT_DEBUG_ENABLED (1U)
380
381 #if !defined (CY_ARM_FAULT_DEBUG)
382 /** The macro defines if the Fault Handler is enabled. Enabled by default. */
383 #define CY_ARM_FAULT_DEBUG (CY_ARM_FAULT_DEBUG_ENABLED)
384 #endif /* CY_ARM_FAULT_DEBUG */
385
386 /** This macro is to be enabled and set appropriately for the CPU's which has
387 * branch prediction enabled, so the delay can work accurately.
388 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4.
389 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1.
390 */
391 #ifndef CY_SYSLIB_DELAY_CALIBRATION_FACTOR
392 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR 1U
393 #endif
394
395 /**
396 * \defgroup group_syslib_macros_status_codes Status codes
397 * \{
398 * Function status type codes
399 */
400 /** \cond INTERNAL */
401
402 #define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */
403 #define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */
404 #define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */
405 #define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */
406 #define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */
407 #define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */
408 #define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */
409
410 /** \endcond */
411
412 /** Get the software PDL module ID */
413 #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos))
414 #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */
415 /** \} group_syslib_macros_status_codes */
416
417 /** \} group_syslib_macros */
418
419 /**
420 * \addtogroup group_syslib_enumerated_types
421 * \{
422 */
423
424 /** The SysLib status code structure. */
425 typedef enum
426 {
427 CY_SYSLIB_SUCCESS = 0x00UL, /**< The success status code */
428 CY_SYSLIB_BAD_PARAM = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< The bad parameter status code */
429 CY_SYSLIB_TIMEOUT = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< The time out status code */
430 CY_SYSLIB_INVALID_STATE = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< The invalid state status code */
431 CY_SYSLIB_UNKNOWN = CY_SYSLIB_ID | CY_PDL_STATUS_ERROR | 0xFFUL /**< Unknown status code */
432 } cy_en_syslib_status_t;
433
434 /** The Life Cycle Stage(LCS) enum. */
435 typedef enum
436 {
437 CY_SYSLIB_LCS_VIRGIN = 0x000UL, /**< LCS Mode: VIRGIN */
438 CY_SYSLIB_LCS_SORT = 0x003UL, /**< LCS Mode: SORT */
439 CY_SYSLIB_LCS_PROVISIONED = 0x00FUL, /**< LCS Mode: PROVISIONED */
440 CY_SYSLIB_LCS_NORMAL_PROVISIONED = 0xC0FUL, /**< LCS Mode: NORMAL-PROVISIONED*/
441 CY_SYSLIB_LCS_NORMAL = 0xC03UL, /**< LCS Mode: NORMAL */
442 CY_SYSLIB_LCS_SECURE = 0xC3FUL, /**< LCS Mode: SECURE */
443 CY_SYSLIB_LCS_NORMAL_NO_SECURE = 0xCC3UL, /**< LCS Mode: NORMAL_NO_SECURE */
444 CY_SYSLIB_LCS_RMA = 0xF3FUL, /**< LCS Mode: RMA */
445 CY_SYSLIB_LCS_CORRUPTED = 0xFFFFUL, /**< LCS Mode: CORRUPTED */
446 } cy_en_syslib_lcs_mode_t;
447
448 /** \} group_syslib_enumerated_types */
449 /**
450 * \addtogroup group_syslib_data_structures
451 * \{
452 */
453
454 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
455 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
456 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55))
457 /** Configurable Fault Status Register - CFSR */
458 typedef struct
459 {
460 /** MemManage Fault Status Sub-register - MMFSR */
461 uint32_t iaccViol : 1; /**< MemManage Fault - The instruction access violation flag */
462 uint32_t daccViol : 1; /**< MemManage Fault - The data access violation flag */
463 uint32_t reserved1 : 1; /**< Reserved */
464 uint32_t mUnstkErr : 1; /**< MemManage Fault - Unstacking for a return from exception */
465 uint32_t mStkErr : 1; /**< MemManage Fault - MemManage fault on stacking for exception entry */
466 uint32_t mlspErr : 1; /**< MemManage Fault - MemManage fault occurred during floating-point lazy state preservation */
467 uint32_t reserved2 : 1; /**< Reserved */
468 uint32_t mmarValid : 1; /**< MemManage Fault - The MemManage Address register valid flag */
469 /** Bus Fault Status Sub-register - UFSR */
470 uint32_t iBusErr : 1; /**< Bus Fault - The instruction bus error */
471 uint32_t precisErr : 1; /**< Bus Fault - The precise Data bus error */
472 uint32_t imprecisErr : 1; /**< Bus Fault - The imprecise data bus error */
473 uint32_t unstkErr : 1; /**< Bus Fault - Unstacking for an exception return has caused one or more bus faults */
474 uint32_t stkErr : 1; /**< Bus Fault - Stacking for an exception entry has caused one or more bus faults */
475 uint32_t lspErr : 1; /**< Bus Fault - A bus fault occurred during the floating-point lazy state */
476 uint32_t reserved3 : 1; /**< Reserved */
477 uint32_t bfarValid : 1; /**< Bus Fault - The bus fault address register valid flag */
478 /** Usage Fault Status Sub-register - UFSR */
479 uint32_t undefInstr : 1; /**< Usage Fault - An undefined instruction */
480 uint32_t invState : 1; /**< Usage Fault - The invalid state */
481 uint32_t invPC : 1; /**< Usage Fault - An invalid PC */
482 uint32_t noCP : 1; /**< Usage Fault - No coprocessor */
483 uint32_t reserved4 : 4; /**< Reserved */
484 uint32_t unaligned : 1; /**< Usage Fault - Unaligned access */
485 uint32_t divByZero : 1; /**< Usage Fault - Divide by zero */
486 uint32_t reserved5 : 6; /**< Reserved */
487 } cy_stc_fault_cfsr_t;
488
489 /** Hard Fault Status Register - HFSR */
490 typedef struct
491 {
492 uint32_t reserved1 : 1; /**< Reserved. */
493 uint32_t vectTbl : 1; /**< HFSR - Indicates a bus fault on a vector table read during exception processing */
494 uint32_t reserved2 : 28; /**< Reserved. */
495 uint32_t forced : 1; /**< HFSR - Indicates a forced hard fault */
496 uint32_t debugEvt : 1; /**< HFSR - Reserved for the debug use. */
497 } cy_stc_fault_hfsr_t;
498
499 /** System Handler Control and State Register - SHCSR */
500 typedef struct
501 {
502 uint32_t memFaultAct : 1; /**< SHCSR - The MemManage exception active bit, reads as 1 if the exception is active */
503 uint32_t busFaultAct : 1; /**< SHCSR - The BusFault exception active bit, reads as 1 if the exception is active */
504 uint32_t reserved1 : 1; /**< Reserved. */
505 uint32_t usgFaultAct : 1; /**< SHCSR - The UsageFault exception active bit, reads as 1 if the exception is active */
506 uint32_t reserved2 : 3; /**< Reserved. */
507 uint32_t svCallAct : 1; /**< SHCSR - The SVCall active bit, reads as 1 if the SVC call is active */
508 uint32_t monitorAct : 1; /**< SHCSR - The debug monitor active bit, reads as 1 if the debug monitor is active */
509 uint32_t reserved3 : 1; /**< Reserved. */
510 uint32_t pendSVAct : 1; /**< SHCSR - The PendSV exception active bit, reads as 1 if the exception is active */
511 uint32_t sysTickAct : 1; /**< SHCSR - The SysTick exception active bit, reads as 1 if the exception is active */
512 uint32_t usgFaultPended : 1; /**< SHCSR - The UsageFault exception pending bit, reads as 1 if the exception is pending */
513 uint32_t memFaultPended : 1; /**< SHCSR - The MemManage exception pending bit, reads as 1 if the exception is pending */
514 uint32_t busFaultPended : 1; /**< SHCSR - The BusFault exception pending bit, reads as 1 if the exception is pending */
515 uint32_t svCallPended : 1; /**< SHCSR - The SVCall pending bit, reads as 1 if the exception is pending */
516 uint32_t memFaultEna : 1; /**< SHCSR - The MemManage enable bit, set to 1 to enable */
517 uint32_t busFaultEna : 1; /**< SHCSR - The BusFault enable bit, set to 1 to enable */
518 uint32_t usgFaultEna : 1; /**< SHCSR - The UsageFault enable bit, set to 1 to enable */
519 uint32_t reserved4 : 13; /**< Reserved */
520 } cy_stc_fault_shcsr_t;
521 #endif /* CY_CPU_CORTEX_M4, CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M33, CY_CPU_CORTEX_M55*/
522
523 /** The fault configuration structure. */
524 typedef struct
525 {
526 uint32_t r0; /**< R0 register content */
527 uint32_t r1; /**< R1 register content */
528 uint32_t r2; /**< R2 register content */
529 uint32_t r3; /**< R3 register content */
530 uint32_t r12; /**< R12 register content */
531 uint32_t lr; /**< LR register content */
532 uint32_t pc; /**< PC register content */
533 uint32_t psr; /**< PSR register content */
534 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
535 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55))
536 union
537 {
538 uint32_t cfsrReg; /**< CFSR register content as a word */
539 cy_stc_fault_cfsr_t cfsrBits; /**< CFSR register content as a structure */
540 } cfsr;
541 union
542 {
543 uint32_t hfsrReg; /**< HFSR register content as a word */
544 cy_stc_fault_hfsr_t hfsrBits; /**< HFSR register content as a structure */
545 } hfsr;
546 union
547 {
548 uint32_t shcsrReg; /**< SHCSR register content as a word */
549 cy_stc_fault_shcsr_t shcsrBits; /**< SHCSR register content as a structure */
550 } shcsr;
551 uint32_t mmfar; /**< MMFAR register content */
552 uint32_t bfar; /**< BFAR register content */
553 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
554 (defined (__FPU_USED ) && (__FPU_USED == 1U)))
555 uint32_t s0; /**< FPU S0 register content */
556 uint32_t s1; /**< FPU S1 register content */
557 uint32_t s2; /**< FPU S2 register content */
558 uint32_t s3; /**< FPU S3 register content */
559 uint32_t s4; /**< FPU S4 register content */
560 uint32_t s5; /**< FPU S5 register content */
561 uint32_t s6; /**< FPU S6 register content */
562 uint32_t s7; /**< FPU S7 register content */
563 uint32_t s8; /**< FPU S8 register content */
564 uint32_t s9; /**< FPU S9 register content */
565 uint32_t s10; /**< FPU S10 register content */
566 uint32_t s11; /**< FPU S11 register content */
567 uint32_t s12; /**< FPU S12 register content */
568 uint32_t s13; /**< FPU S13 register content */
569 uint32_t s14; /**< FPU S14 register content */
570 uint32_t s15; /**< FPU S15 register content */
571 uint32_t fpscr; /**< FPU FPSCR register content */
572 #endif /* __FPU_PRESENT */
573 #endif /* CY_CPU_CORTEX_M4, CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M33, CY_CPU_CORTEX_M55*/
574 } cy_stc_fault_frame_t;
575 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
576
577 /** \} group_syslib_data_structures */
578
579 /**
580 * \addtogroup group_syslib_macros
581 * \{
582 */
583
584 /** The driver major version */
585 #define CY_SYSLIB_DRV_VERSION_MAJOR 3
586
587 /** The driver minor version */
588 #define CY_SYSLIB_DRV_VERSION_MINOR 40
589
590 /** Define start of the function placed to the SRAM area by the linker */
591 #ifndef CY_SECTION_RAMFUNC_BEGIN
592 #if defined (__ICCARM__)
593 #define CY_SECTION_RAMFUNC_BEGIN CY_PRAGMA(diag_suppress = Ta023) __ramfunc
594 #else
595 #define CY_SECTION_RAMFUNC_BEGIN CY_SECTION(".cy_ramfunc")
596 #endif
597 #endif
598
599 /** Define end of the function placed to the SRAM area by the linker */
600 #ifndef CY_SECTION_RAMFUNC_END
601 #if defined (__ICCARM__)
602 #define CY_SECTION_RAMFUNC_END CY_PRAGMA(diag_default = Ta023)
603 #else
604 #define CY_SECTION_RAMFUNC_END
605 #endif
606 #endif
607
608 #if (CY_CPU_CORTEX_M7 || CY_CPU_CORTEX_M55)
609 /** Define start of the function placed to the ITCM area by the linker */
610 #ifndef CY_SECTION_ITCM_BEGIN
611 #define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm")
612 #endif
613
614 /** Define end of the function placed to the ITCM area by the linker */
615 #ifndef CY_SECTION_ITCM_END
616 #define CY_SECTION_ITCM_END
617 #endif
618
619 /** Define start of the function placed to the DTCM area by the linker */
620 #ifndef CY_SECTION_DTCM_BEGIN
621 #define CY_SECTION_DTCM_BEGIN CY_SECTION(".cy_dtcm")
622 #endif
623
624 /** Define end of the function placed to the DTCM area by the linker */
625 #ifndef CY_SECTION_DTCM_END
626 #define CY_SECTION_DTCM_END
627 #endif
628 #endif /* CY_CPU_CORTEX_M7, CY_CPU_CORTEX_M55 */
629
630 /** Define start of the code block to be copied to SRAM by the linker during init */
631 #ifndef CY_SECTION_INIT_CODECOPY_BEGIN
632 #if defined (__ICCARM__)
633 #define CY_SECTION_INIT_CODECOPY_BEGIN CY_PRAGMA(default_function_attributes = @ "code_in_RAM")
634 #else
635 #define CY_SECTION_INIT_CODECOPY_BEGIN
636 #endif
637 #endif
638
639 /** Define end of the code block to be copied to SRAM by the linker during init */
640 #ifndef CY_SECTION_INIT_CODECOPY_END
641 #if defined (__ICCARM__)
642 #define CY_SECTION_INIT_CODECOPY_END CY_PRAGMA(default_function_attributes =)
643 #else
644 #define CY_SECTION_INIT_CODECOPY_END
645 #endif
646 #endif
647
648 /** Define variable to be placed to the shared SRAM area by the linker */
649 #ifndef CY_SECTION_SHAREDMEM
650 #define CY_SECTION_SHAREDMEM CY_SECTION(".cy_sharedmem")
651 #endif
652
653 /** Define variable to be placed to the secured shared SRAM area by the linker */
654 #ifndef CY_SECTION_SHAREDMEM_SEC
655 #define CY_SECTION_SHAREDMEM_SEC CY_SECTION(".cy_sharedmem_sec")
656 #endif
657
658 /** Define start of function placed to the bootstrap area by the linker */
659 #ifndef CY_SECTION_BOOTSTRAP_FUNC_BEGIN
660 #if defined (__GNUC__)
661 #define CY_SECTION_BOOTSTRAP_FUNC_BEGIN CY_SECTION(".cy_l1func")
662 #endif
663 #endif
664
665 /** Define end of function placed to the bootstrap area by the linker */
666 #ifndef CY_SECTION_BOOTSTRAP_FUNC_END
667 #if defined (__GNUC__)
668 #define CY_SECTION_BOOTSTRAP_FUNC_END
669 #endif
670 #endif
671
672 /** Placed initialized global variable to the bootstrap data area by the linker */
673 #ifndef CY_SECTION_BOOTSTRAP_DATA
674 #if defined (__GNUC__)
675 #define CY_SECTION_BOOTSTRAP_DATA CY_SECTION(".cy_l1data")
676 #endif
677 #endif
678
679 /** Placed un-init global variable to the bootstrap bss area by the linker */
680 #ifndef CY_SECTION_BOOTSTRAP_BSS
681 #if defined (__GNUC__)
682 #define CY_SECTION_BOOTSTRAP_BSS CY_SECTION(".cy_l1bss")
683 #endif
684 #endif
685
686 typedef void (* cy_israddress)(void); /**< Type of ISR callbacks */
687 #if defined (__ICCARM__)
688 typedef union { cy_israddress __fun; void * __ptr; } cy_intvec_elem;
689 #endif /* defined (__ICCARM__) */
690
691 /* MISRA rule 6.3 recommends using specific-length typedef for the basic
692 * numerical types of signed and unsigned variants of char, float, and double.
693 */
694 typedef char char_t; /**< Specific-length typedef for the basic numerical types of char */
695 typedef float float32_t; /**< Specific-length typedef for the basic numerical types of float */
696 typedef double float64_t; /**< Specific-length typedef for the basic numerical types of double */
697
698 #if !defined(NDEBUG)
699 /** The max size of the file name which stores the ASSERT location */
700 #define CY_MAX_FILE_NAME_SIZE (24U)
701 extern CY_NOINIT char_t cy_assertFileName[CY_MAX_FILE_NAME_SIZE + 1]; /**< The assert buffer */
702 extern CY_NOINIT uint32_t cy_assertLine; /**< The assert line value */
703 #endif /* NDEBUG */
704
705 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED)
706 #define CY_R0_Pos (0U) /**< The position of the R0 content in a fault structure */
707 #define CY_R1_Pos (1U) /**< The position of the R1 content in a fault structure */
708 #define CY_R2_Pos (2U) /**< The position of the R2 content in a fault structure */
709 #define CY_R3_Pos (3U) /**< The position of the R3 content in a fault structure */
710 #define CY_R12_Pos (4U) /**< The position of the R12 content in a fault structure */
711 #define CY_LR_Pos (5U) /**< The position of the LR content in a fault structure */
712 #define CY_PC_Pos (6U) /**< The position of the PC content in a fault structure */
713 #define CY_PSR_Pos (7U) /**< The position of the PSR content in a fault structure */
714 #if (CY_CPU_CORTEX_M4 || (defined (CY_CPU_CORTEX_M7) && CY_CPU_CORTEX_M7) || \
715 (defined (CY_CPU_CORTEX_M33) && CY_CPU_CORTEX_M33) || (defined (CY_CPU_CORTEX_M55) && CY_CPU_CORTEX_M55)) && \
716 ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && (defined (__FPU_USED ) && (__FPU_USED == 1U)))
717 #define CY_FPSCR_IXC_Msk (0x00000010U) /**< The cumulative exception bit for floating-point exceptions */
718 #define CY_FPSCR_IDC_Msk (0x00000080U) /**< The cumulative exception bit for floating-point exceptions */
719 #define CY_S0_Pos (8U) /**< The position of the FPU S0 content in a fault structure */
720 #define CY_S1_Pos (9U) /**< The position of the FPU S1 content in a fault structure */
721 #define CY_S2_Pos (10U) /**< The position of the FPU S2 content in a fault structure */
722 #define CY_S3_Pos (11U) /**< The position of the FPU S3 content in a fault structure */
723 #define CY_S4_Pos (12U) /**< The position of the FPU S4 content in a fault structure */
724 #define CY_S5_Pos (13U) /**< The position of the FPU S5 content in a fault structure */
725 #define CY_S6_Pos (14U) /**< The position of the FPU S6 content in a fault structure */
726 #define CY_S7_Pos (15U) /**< The position of the FPU S7 content in a fault structure */
727 #define CY_S8_Pos (16U) /**< The position of the FPU S8 content in a fault structure */
728 #define CY_S9_Pos (17U) /**< The position of the FPU S9 content in a fault structure */
729 #define CY_S10_Pos (18U) /**< The position of the FPU S10 content in a fault structure */
730 #define CY_S11_Pos (19U) /**< The position of the FPU S11 content in a fault structure */
731 #define CY_S12_Pos (20U) /**< The position of the FPU S12 content in a fault structure */
732 #define CY_S13_Pos (21U) /**< The position of the FPU S13 content in a fault structure */
733 #define CY_S14_Pos (22U) /**< The position of the FPU S14 content in a fault structure */
734 #define CY_S15_Pos (23U) /**< The position of the FPU S15 content in a fault structure */
735 #define CY_FPSCR_Pos (24U) /**< The position of the FPU FPSCR content in a fault structure */
736 #endif /* (CY_CPU_CORTEX_M4 || CY_CPU_CORTEX_M7 || CY_CPU_CORTEX_M33 || CY_CPU_CORTEX_M55) && __FPU_PRESENT */
737
738 extern CY_NOINIT cy_stc_fault_frame_t cy_faultFrame; /**< Fault frame structure */
739 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
740
741 /**
742 * \defgroup group_syslib_macros_assert Assert Classes and Levels
743 * \{
744 * Defines for the Assert Classes and Levels
745 */
746
747 /**
748 * Class 1 - The highest class, safety-critical functions which rely on parameters that could be
749 * changed between different PSoC devices
750 */
751 #define CY_ASSERT_CLASS_1 (1U)
752
753 /** Class 2 - Functions that have fixed limits such as counter periods (16-bits/32-bits etc.) */
754 #define CY_ASSERT_CLASS_2 (2U)
755
756 /** Class 3 - Functions that accept enums as constant parameters */
757 #define CY_ASSERT_CLASS_3 (3U)
758
759 #ifndef CY_ASSERT_LEVEL
760 /** The user-definable assert level from compiler command-line argument (similarly to DEBUG / NDEBUG) */
761 #define CY_ASSERT_LEVEL CY_ASSERT_CLASS_3
762 #endif /* CY_ASSERT_LEVEL */
763
764 #if (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1)
765 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
766 #define CY_ASSERT_L2(x) do{}while(false) /**< Assert Level 2 */
767 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
768 #elif (CY_ASSERT_LEVEL == CY_ASSERT_CLASS_2)
769 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
770 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
771 #define CY_ASSERT_L3(x) do{}while(false) /**< Assert Level 3 */
772 #else /* Default is Level 3 */
773 #define CY_ASSERT_L1(x) CY_ASSERT(x) /**< Assert Level 1 */
774 #define CY_ASSERT_L2(x) CY_ASSERT(x) /**< Assert Level 2 */
775 #define CY_ASSERT_L3(x) CY_ASSERT(x) /**< Assert Level 3 */
776 #endif /* CY_ASSERT_LEVEL == CY_ASSERT_CLASS_1 */
777
778 /** \} group_syslib_macros_assert */
779
780 #ifdef CY_IP_M33SYSCPUSS
781 /*******************************************************************************
782 * Macro Name: CY_UNUSED_PARAM
783 ****************************************************************************//**
784 *
785 * Suppresses the unused parameter warning
786 *
787 * \note
788 * This macro is available for devices having M33SYSCPUSS IP.
789 *
790 *******************************************************************************/
791 #define CY_UNUSED_PARAM(a) (void)(a)
792
793 /*******************************************************************************
794 * Macro Name: CY_ARRAY_SIZE(x)
795 ****************************************************************************//**
796 *
797 * Returns the size of Array
798 *
799 * \param x Array Name
800 *
801 * \note
802 * This macro is available for devices having M33SYSCPUSS IP.
803 *
804 *******************************************************************************/
805 #define CY_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
806 #endif /* CY_IP_M33SYSCPUSS */
807
808
809 /******************************************************************************
810 * Constants
811 *****************************************************************************/
812
813 /**
814 * \defgroup group_syslib_macros_reset_cause Reset cause
815 * \{
816 * Define RESET_CAUSE mask values
817 */
818 /** A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. */
819 #define CY_SYSLIB_RESET_HWWDT (0x0001U)
820 /** The fault logging system requested a reset from its Active logic. */
821 #define CY_SYSLIB_RESET_ACT_FAULT (0x0002U)
822 /** The fault logging system requested a reset from its Deep-Sleep logic. */
823 #define CY_SYSLIB_RESET_DPSLP_FAULT (0x0004U)
824
825 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M7CPUSS)
826 /** The fault logging system requested a reset from its Test Controller or debugger asserted test. */
827 /**
828 * \note
829 * This macro is available for devices having M33SYSCPUSS IP.
830 **/
831 #define CY_SYSLIB_RESET_TC_DBGRESET (0x0008U)
832 #endif
833
834 /** The CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. */
835 #define CY_SYSLIB_RESET_SOFT (0x0010U)
836 /** The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. */
837 #define CY_SYSLIB_RESET_SWWDT0 (0x0020U)
838 /** The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. */
839 #define CY_SYSLIB_RESET_SWWDT1 (0x0040U)
840 /** The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. */
841 #define CY_SYSLIB_RESET_SWWDT2 (0x0080U)
842 /** The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. */
843 #define CY_SYSLIB_RESET_SWWDT3 (0x0100U)
844 /** The reset has occurred on a loss of high-frequency clock. */
845 #define CY_SYSLIB_RESET_CSV_LOSS_WAKEUP (0x10000U)
846 /** The reset has occurred due to frequency error of high-frequency clock. */
847 #define CY_SYSLIB_RESET_CSV_ERROR_WAKEUP (0x20000U)
848 /** The reset has occurred on a wakeup from Hibernate power mode. */
849 #define CY_SYSLIB_RESET_HIB_WAKEUP (0x80000000U)
850
851 #ifdef CY_IP_M7CPUSS
852 /**
853 * \note
854 * Below macro are available for devices having CY_IP_M7CPUSS IP.
855 **/
856 /** External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
857 #define CY_SYSLIB_RESET_XRES (0x10000U)
858 /** External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. */
859 #define CY_SYSLIB_RESET_BODVDDD (0x20000U)
860 /** External VDDA supply crossed the brown-out limit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
861 #define CY_SYSLIB_RESET_BODVDDA (0x40000U)
862 /** Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. */
863 #define CY_SYSLIB_RESET_BODVCCD (0x80000U)
864 /** Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
865 #define CY_SYSLIB_RESET_OVDVDDD (0x100000U)
866 /** Overvoltage detection on the external VDDA supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
867 #define CY_SYSLIB_RESET_OVDVDDA (0x200000U)
868 /** Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
869 #define CY_SYSLIB_RESET_OVDVCCD (0x400000U)
870 /** Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
871 #define CY_SYSLIB_RESET_OCD_ACT_LINREG (0x800000U)
872 /** Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
873 #define CY_SYSLIB_RESET_OCD_DPSLP_LINREG (0x1000000U)
874 /** Overcurrent detection from REGHC (if present). If REGHC is not present, hardware will never set this bit.This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
875 #define CY_SYSLIB_RESET_OCD_REGHC (0x2000000U)
876 /** PMIC status triggered a reset. If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. */
877 #define CY_SYSLIB_RESET_PMIC (0x4000000U)
878 /** PXRES triggered. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. */
879 #define CY_SYSLIB_RESET_PXRES (0x10000000U)
880 /** Structural reset was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. */
881 #define CY_SYSLIB_RESET_STRUCT_XRES (0x20000000U)
882 /** Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. */
883 #define CY_SYSLIB_RESET_PORVDDD (0x40000000U)
884
885 #endif
886
887
888 /** \} group_syslib_macros_reset_cause */
889
890 #ifdef CY_IP_M4CPUSS
891 /** Bit[31:24] Opcode = 0x1B (SoftReset)
892 * Bit[7:1] Type = 1 (Only CM4 reset)
893 */
894 /**
895 * \note
896 * This macro is available for devices having M4CPUSS IP.
897 **/
898 #define CY_IPC_DATA_FOR_CM4_SOFT_RESET (0x1B000002UL)
899 #endif
900
901 #if defined(CY_IP_M4CPUSS) || defined (CY_IP_M33SYSCPUSS)
902
903 /**
904 * \defgroup group_syslib_macros_unique_id Unique ID
905 * \{
906 * Unique ID fields positions
907 */
908 /**
909 * \note
910 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
911 **/
912 #define CY_UNIQUE_ID_DIE_YEAR_Pos (57U) /**< The position of the DIE_YEAR field in the silicon Unique ID */
913 /**
914 * \note
915 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
916 **/
917 #define CY_UNIQUE_ID_DIE_MINOR_Pos (56U) /**< The position of the DIE_MINOR field in the silicon Unique ID */
918 /**
919 * \note
920 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
921 **/
922 #define CY_UNIQUE_ID_DIE_SORT_Pos (48U) /**< The position of the DIE_SORT field in the silicon Unique ID */
923 /**
924 * \note
925 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
926 **/
927 #define CY_UNIQUE_ID_DIE_Y_Pos (40U) /**< The position of the DIE_Y field in the silicon Unique ID */
928 /**
929 * \note
930 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
931 **/
932 #define CY_UNIQUE_ID_DIE_X_Pos (32U) /**< The position of the DIE_X field in the silicon Unique ID */
933 /**
934 * \note
935 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
936 **/
937 #define CY_UNIQUE_ID_DIE_WAFER_Pos (24U) /**< The position of the DIE_WAFER field in the silicon Unique ID */
938 /**
939 * \note
940 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
941 **/
942 #define CY_UNIQUE_ID_DIE_LOT_2_Pos (16U) /**< The position of the DIE_LOT_2 field in the silicon Unique ID */
943 /**
944 * \note
945 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
946 **/
947 #define CY_UNIQUE_ID_DIE_LOT_1_Pos (8U) /**< The position of the DIE_LOT_1 field in the silicon Unique ID */
948 /**
949 * \note
950 * This macro is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
951 **/
952 #define CY_UNIQUE_ID_DIE_LOT_0_Pos (0U) /**< The position of the DIE_LOT_0 field in the silicon Unique ID */
953
954 /** \} group_syslib_macros_unique_id */
955 #endif
956
957 /** \} group_syslib_macros */
958
959 /******************************************************************************
960 * Function prototypes
961 ******************************************************************************/
962
963 /**
964 * \addtogroup group_syslib_functions
965 * \{
966 */
967
968 /*******************************************************************************
969 * Function Name: Cy_SysLib_Delay
970 ****************************************************************************//**
971 *
972 * The function delays by the specified number of milliseconds.
973 * By default, the number of cycles to delay is calculated based on the
974 * \ref SystemCoreClock.
975 *
976 * \param milliseconds The number of milliseconds to delay.
977 *
978 * \note The function calls \ref Cy_SysLib_DelayCycles() API to generate a delay.
979 * If the function parameter (milliseconds) is bigger than
980 * CY_DELAY_MS_OVERFLOW constant, then an additional loop runs to prevent
981 * an overflow in parameter passed to \ref Cy_SysLib_DelayCycles() API.
982 *
983 * \note The Calibration factor is to correct the delay in cases where
984 * CPU's use branch prediction, currently applicable for only CAT1C
985 * devices.
986 *
987 *******************************************************************************/
988 void Cy_SysLib_Delay(uint32_t milliseconds);
989
990
991 /*******************************************************************************
992 * Function Name: Cy_SysLib_DelayUs
993 ****************************************************************************//**
994 *
995 * The function delays by the specified number of microseconds.
996 * By default, the number of cycles to delay is calculated based on the
997 * \ref SystemCoreClock.
998 *
999 * \param microseconds The number of microseconds to delay.
1000 *
1001 * \note If the CPU frequency is a small non-integer number, the actual delay
1002 * can be up to twice as long as the nominal value. The actual delay
1003 * cannot be shorter than the nominal one.
1004 *
1005 * \note The Calibration factor is to correct the delay in cases where
1006 * CPU's use branch prediction, currently applicable for only CAT1C
1007 * devices.
1008 *
1009 *******************************************************************************/
1010 void Cy_SysLib_DelayUs(uint16_t microseconds);
1011
1012 /*******************************************************************************
1013 * Function Name: Cy_SysLib_Rtos_Delay
1014 ****************************************************************************//**
1015 *
1016 * The function is same as \ref Cy_SysLib_Delay. However, this API is declared WEAK
1017 * providing option for user to overwrite the implementation based on target RTOS.
1018 *
1019 * \param milliseconds The number of milliseconds to delay.
1020 *
1021 *******************************************************************************/
1022 void Cy_SysLib_Rtos_Delay(uint32_t milliseconds);
1023
1024
1025 /*******************************************************************************
1026 * Function Name: Cy_SysLib_Rtos_DelayUs
1027 ****************************************************************************//**
1028 *
1029 * The function is same as \ref Cy_SysLib_DelayUs. However, this API is declared WEAK
1030 * providing option for user to overwrite the implementation based on target RTOS.
1031 *
1032 * \param microseconds The number of microseconds to delay.
1033 *
1034 *******************************************************************************/
1035 void Cy_SysLib_Rtos_DelayUs(uint16_t microseconds);
1036
1037
1038 /*******************************************************************************
1039 * Function Name: Cy_SysLib_DelayCycles
1040 ****************************************************************************//**
1041 * Delays for the specified number of cycles.
1042 * The function is implemented in the assembler for each supported compiler.
1043 *
1044 * \param cycles The number of cycles to delay.
1045 *
1046 * \note While using for CAT1C devices, where the CPU supports branch prediction,
1047 * this API needs to be called as below
1048 * Cy_SysLib_DelayCycles(cycles * CY_SYSLIB_DELAY_CALIBRATION_FACTOR);
1049 * For Example:-
1050 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 1 for CM0P, CM33 and CM4.
1051 * CY_SYSLIB_DELAY_CALIBRATION_FACTOR = 2 for CM7_0 and CM7_1.
1052 *
1053 *******************************************************************************/
1054 void Cy_SysLib_DelayCycles(uint32_t cycles);
1055
1056
1057 /*******************************************************************************
1058 * Function Name: Cy_SysLib_Halt
1059 ****************************************************************************//**
1060 *
1061 * This function halts the CPU but only the CPU which calls the function.
1062 * It doesn't affect other CPUs.
1063 *
1064 * \param reason The value to be used during debugging.
1065 *
1066 * \note The function executes the BKPT instruction for halting CPU and is
1067 * intended to be used for the debug purpose. A regular use case requires
1068 * Debugger attachment before the function call.
1069 * The BKPT instruction causes the CPU to enter the Debug state. Debug
1070 * tools can use this to investigate the system state, when the
1071 * instruction at a particular address is reached.
1072 *
1073 * \note Execution of a BKPT instruction without a debugger attached produces
1074 * a fault. The fault results in the HardFault exception being taken
1075 * or causes a Lockup state if it occurs in the NMI or HardFault handler.
1076 * The default HardFault handler make a software reset if the build option
1077 * is the release mode (NDEBUG). If the build option is the debug mode,
1078 * the system will stay in the infinite loop of the
1079 * \ref Cy_SysLib_ProcessingFault() function.
1080 *
1081 *******************************************************************************/
1082 #if defined (CY_IP_M33SYSCPUSS) || defined (CY_IP_M55APPCPUSS) || defined (CY_DOXYGEN)
1083 void Cy_SysLib_Halt(uint32_t reason);
1084 #else
1085 /** \cond INTERNAL */
1086 __NO_RETURN void Cy_SysLib_Halt(uint32_t reason);
1087 /** \endcond */
1088 #endif
1089
1090
1091 /*******************************************************************************
1092 * Macro Name: Cy_SysLib_AssertFailed
1093 ****************************************************************************//**
1094 *
1095 * This function stores the ASSERT location of the file name (including path
1096 * to file) and line number in a non-zero init area for debugging. Also it calls
1097 * the \ref Cy_SysLib_Halt() function to halt the processor.
1098 *
1099 * \param file The file name of the ASSERT location.
1100 * \param line The line number of the ASSERT location.
1101 *
1102 * \note A stored file name and line number could be accessed by
1103 * cy_assertFileName and cy_assertLine global variables.
1104 * \note This function has the WEAK option, so the user can redefine
1105 * the function for a custom processing.
1106 *
1107 *******************************************************************************/
1108 void Cy_SysLib_AssertFailed(const char_t * file, uint32_t line);
1109
1110 #ifdef CY_IP_M4CPUSS
1111
1112
1113 /*******************************************************************************
1114 * Function Name: Cy_SysLib_ClearFlashCacheAndBuffer
1115 ****************************************************************************//**
1116 *
1117 * This function invalidates the flash cache and buffer. It ensures the valid
1118 * data is read from flash instead of using outdated data from the cache.
1119 * The caches' LRU structure is also reset to their default state.
1120 *
1121 * \note The operation takes a maximum of three clock cycles on the slowest of
1122 * the clk_slow and clk_fast clocks.
1123 *
1124 * \note
1125 * This API is available for devices having M4CPUSS IP.
1126 *
1127 *******************************************************************************/
1128 void Cy_SysLib_ClearFlashCacheAndBuffer(void);
1129
1130 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN)
1131 /*******************************************************************************
1132 * Function Name: Cy_SysLib_SoftResetCM4
1133 ****************************************************************************//**
1134 *
1135 * This function performs a CM4 Core software reset using the CM4_PWR_CTL
1136 * register. The register is accessed by CM0 Core by using a command transferred
1137 * to SROM API through the IPC channel. When the command is sent, the API waits
1138 * for the IPC channel release.
1139 *
1140 * \note This function should be called only when the CM4 core is in Deep
1141 * Sleep mode.
1142 * \note This function will not reset CM0+ Core.
1143 * \note This function waits for an IPC channel release state.
1144 *
1145 * \note
1146 * This API is available for devices having M4CPUSS IP.
1147 *
1148 *******************************************************************************/
1149 void Cy_SysLib_SoftResetCM4(void);
1150 #endif /* CY_CPU_CORTEX_M0P */
1151 #endif
1152
1153 #if defined(CY_IP_M4CPUSS) || (defined (CY_IP_M33SYSCPUSS) && defined(CY_IP_MXEFUSE)) || defined (CY_DOXYGEN)
1154
1155 /*******************************************************************************
1156 * Function Name: Cy_SysLib_GetUniqueId
1157 ****************************************************************************//**
1158 *
1159 * This function returns the silicon unique ID.
1160 * The ID includes Die lot[3]#, Die Wafer#, Die X, Die Y, Die Sort#, Die Minor
1161 * and Die Year.
1162 *
1163 * \return A combined 64-bit unique ID.
1164 * [63:57] - DIE_YEAR
1165 * [56:56] - DIE_MINOR
1166 * [55:48] - DIE_SORT
1167 * [47:40] - DIE_Y
1168 * [39:32] - DIE_X
1169 * [31:24] - DIE_WAFER
1170 * [23:16] - DIE_LOT[2]
1171 * [15: 8] - DIE_LOT[1]
1172 * [ 7: 0] - DIE_LOT[0]
1173 *
1174 * \note
1175 * This API is available for devices having M4CPUSS and CY_IP_M33SYSCPUSS IP.
1176 *
1177 * \note
1178 * For CY_IP_M33SYSCPUSS IP, EFUSE must be in enabled state before
1179 * calling this API.
1180 *
1181 *******************************************************************************/
1182 uint64_t Cy_SysLib_GetUniqueId(void);
1183 #endif
1184
1185 /*******************************************************************************
1186 * Function Name: Cy_SysLib_ResetBackupDomain
1187 ****************************************************************************//**
1188 *
1189 * This function resets the backup domain power to avoid the ILO glitch. The
1190 * glitch can occur when the device is reset due to POR/BOD/XRES while
1191 * the backup voltage is supplied into the system.
1192 *
1193 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1194 * when the reset is complete. After setting the register, this function
1195 * reads the register immediately for returning the result of the backup
1196 * domain reset state. The reading register is important because the Read
1197 * itself takes multiple AHB clock cycles, and the reset is actually
1198 * finishing during that time. Use \ref Cy_SysLib_GetResetStatus to check
1199 * the BACKUP->RESET before any other BACKUP register write.
1200 *
1201 * \note This function also resets the WCO trimming value - use the
1202 * \ref Cy_SysLib_GetWcoTrim and \ref Cy_SysLib_SetWcoTrim to store/restore
1203 * the WCO trimming value.
1204 *
1205 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1206 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1207 *
1208 * \funcusage
1209 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1210 *
1211 *******************************************************************************/
1212 cy_en_syslib_status_t Cy_SysLib_ResetBackupDomain(void);
1213
1214
1215 /*******************************************************************************
1216 * Function Name: Cy_SysLib_GetResetReason
1217 ****************************************************************************//**
1218 *
1219 * The function returns the cause for the latest reset(s) that occurred in
1220 * the system. The reset causes include system faults and
1221 * device reset on a wakeup from Hibernate mode. For M33SYSCPUSS IP,
1222 * the reset causes also include an HFCLK error.
1223 * The return results are consolidated reset causes from reading RES_CAUSE,
1224 * RES_CAUSE2 and PWR_HIBERNATE token registers.
1225 *
1226 * \return The cause of a system reset.
1227 * Return values to be checked as per the CPUSS IP of the device.
1228 *
1229 * | Name in M4CPUSS IP | Name in M33SYSCPUSS IP | Name in M7CPUSS IP | Value
1230 * |-------------------------------|------------------------------|----------------------------------|-------------------
1231 * | CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_HWWDT | 0x00001 (bit0)
1232 * | CY_SYSLIB_RESET_ACT_FAULT | CY_SYSLIB_RESET_ACT_FAULT | CY_SYSLIB_RESET_ACT_FAULT | 0x00002 (bit1)
1233 * | CY_SYSLIB_RESET_DPSLP_FAULT | CY_SYSLIB_RESET_DPSLP_FAULT | CY_SYSLIB_RESET_DPSLP_FAULT | 0x00004 (bit2)
1234 * | CY_SYSLIB_RESET_TC_DBGRESET | CY_SYSLIB_RESET_CSV_WCO_LOSS | CY_SYSLIB_RESET_TC_DBGRESET | 0x00008 (bit3)
1235 * | CY_SYSLIB_RESET_SOFT | CY_SYSLIB_RESET_SOFT | CY_SYSLIB_RESET_SOFT | 0x00010 (bit4)
1236 * | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT0 | 0x00020 (bit5)
1237 * | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT1 | CY_SYSLIB_RESET_SWWDT1 | 0x00040 (bit6)
1238 * | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT2 | 0x00080 (bit7)
1239 * | CY_SYSLIB_RESET_SWWDT3 | CY_SYSLIB_RESET_SWWDT3 | CY_SYSLIB_RESET_SWWDT3 | 0x00100 (bit8)
1240 * | | | | 0x00200 (bit9)
1241 * | | | | 0x00400 (bit10)
1242 * | | | | 0x00800 (bit11)
1243 * | | | | 0x01000 (bit12)
1244 * | | | | 0x02000 (bit13)
1245 * | | | | 0x04000 (bit14)
1246 * | | | | 0x08000 (bit15)
1247 * | | CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_XRES | 0x10000 (bit16)
1248 * | | CY_SYSLIB_RESET_HFCLK_ERR | CY_SYSLIB_RESET_BODVDDD | 0x20000 (bit17)
1249 * | | | CY_SYSLIB_RESET_BODVDDA | 0x40000 (bit18)
1250 * | | | CY_SYSLIB_RESET_BODVCCD | 0x80000 (bit19)
1251 * | | | CY_SYSLIB_RESET_OVDVDDD | 0x100000 (bit20)
1252 * | | | CY_SYSLIB_RESET_OVDVDDA | 0x200000 (bit21)
1253 * | | | CY_SYSLIB_RESET_OVDVCCD | 0x400000 (bit22)
1254 * | | | CY_SYSLIB_RESET_OCD_ACT_LINREG | 0x800000 (bit23)
1255 * | | | CY_SYSLIB_RESET_OCD_DPSLP_LINREG | 0x1000000 (bit24)
1256 * | | | CY_SYSLIB_RESET_OCD_REGHC | 0x2000000 (bit25)
1257 * | | | CY_SYSLIB_RESET_PMIC | 0x4000000 (bit26)
1258 * | | | | 0x8000000 (bit27)
1259 * | | | CY_SYSLIB_RESET_PXRES | 0x10000000 (bit28)
1260 * | | | CY_SYSLIB_RESET_STRUCT_XRES | 0x20000000 (bit29)
1261 * | | | CY_SYSLIB_RESET_PORVDDD | 0x40000000 (bit30)
1262 * | CY_SYSLIB_RESET_HIB_WAKEUP | CY_SYSLIB_RESET_HIB_WAKEUP | CY_SYSLIB_RESET_HIB_WAKEUP | 0x80000000 (bit31)
1263 * \note This not is available for devices having M33SYSCPUSS IP
1264 * CY_SYSLIB_RESET_CSV_WCO_LOSS, CY_SYSLIB_RESET_HFCLK_LOSS and
1265 * CY_SYSLIB_RESET_HFCLK_ERR causes of a system reset available only if
1266 * WCO CSV present in the device.
1267 *
1268 *******************************************************************************/
1269 uint32_t Cy_SysLib_GetResetReason(void);
1270
1271
1272 /*******************************************************************************
1273 * Function Name: Cy_SysLib_ClearResetReason
1274 ****************************************************************************//**
1275 *
1276 * This function clears the values of RES_CAUSE and RES_CAUSE2. Also it clears
1277 * PWR_HIBERNATE token, which indicates reset event on waking up from HIBERNATE.
1278 *
1279 *******************************************************************************/
1280 void Cy_SysLib_ClearResetReason(void);
1281
1282
1283 #if defined(CY_INIT_CODECOPY_ENABLE)
1284 CY_SECTION_INIT_CODECOPY_BEGIN
1285 #endif
1286
1287 /*******************************************************************************
1288 * Function Name: Cy_SysLib_GetResetStatus
1289 ****************************************************************************//**
1290 *
1291 * This function returns the BACKUP->RESET bit value.
1292 * It is reused by the \ref Cy_SysLib_ResetBackupDomain itself and also intended to
1293 * check for CY_SYSLIB_SUCCESS in loop after the \ref Cy_SysLib_ResetBackupDomain call.
1294 *
1295 * \note Writing 1 to BACKUP->RESET resets the backup logic. Hardware clears it
1296 * when the reset is complete. After setting the register, this function
1297 * reads the register immediately for returning the result of the backup
1298 * domain reset state. The reading register is important because the Read
1299 * itself takes multiple AHB clock cycles, and the reset is actually
1300 * finishing during that time.
1301 *
1302 * \return CY_SYSLIB_SUCCESS, if BACKUP->RESET read-back is 0.
1303 * Otherwise returns CY_SYSLIB_INVALID_STATE.
1304 *
1305 * \funcusage
1306 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_ResetBackup
1307 *
1308 *******************************************************************************/
Cy_SysLib_GetResetStatus(void)1309 __STATIC_INLINE cy_en_syslib_status_t Cy_SysLib_GetResetStatus (void)
1310 {
1311 return ((0UL == (BACKUP_RESET & BACKUP_RESET_RESET_Msk)) ? CY_SYSLIB_SUCCESS : CY_SYSLIB_INVALID_STATE);
1312 }
1313
1314 #if defined (CY_IP_MXS40SRSS)
1315 /*******************************************************************************
1316 * Function Name: Cy_SysLib_GetWcoTrim
1317 ****************************************************************************//**
1318 *
1319 * This function returns the BACKUP->TRIM bitfield value.
1320 * It is intended to store the WCO trimming value before
1321 * the \ref Cy_SysLib_ResetBackupDomain usage.
1322 *
1323 * \return The WCO trimming value.
1324 *
1325 * \funcusage
1326 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1327 *
1328 *******************************************************************************/
Cy_SysLib_GetWcoTrim(void)1329 __STATIC_INLINE uint32_t Cy_SysLib_GetWcoTrim (void)
1330 {
1331 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION == 3)
1332 return 0;
1333 #else
1334 return (BACKUP_TRIM & BACKUP_TRIM_TRIM_Msk);
1335 #endif
1336 }
1337
1338
1339 /*******************************************************************************
1340 * Function Name: Cy_SysLib_SetWcoTrim
1341 ****************************************************************************//**
1342 *
1343 * This function writes the value into the BACKUP->TRIM bitfield.
1344 * It is intended to restore the WCO trimming value after
1345 * the \ref Cy_SysLib_ResetBackupDomain usage.
1346 *
1347 * \param wcoTrim The WCO trimming value.
1348 *
1349 * \funcusage
1350 * \snippet syslib/snippet/main.c snippet_Cy_SysLib_WcoTrim
1351 *
1352 *******************************************************************************/
Cy_SysLib_SetWcoTrim(uint32_t wcoTrim)1353 __STATIC_INLINE void Cy_SysLib_SetWcoTrim (uint32_t wcoTrim)
1354 {
1355 CY_UNUSED_PARAMETER(wcoTrim);
1356 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3))
1357 BACKUP_TRIM = wcoTrim & BACKUP_TRIM_TRIM_Msk;
1358 #endif
1359 }
1360 #endif /* CY_IP_MXS40SRSS */
1361
1362 #if defined(CY_INIT_CODECOPY_ENABLE)
1363 CY_SECTION_INIT_CODECOPY_END
1364 #endif
1365
1366 #if (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) || defined(CY_DOXYGEN)
1367
1368
1369 /*******************************************************************************
1370 * Function Name: Cy_SysLib_FaultHandler
1371 ****************************************************************************//**
1372 *
1373 * This function stores the ARM Cortex registers into a non-zero init area for
1374 * debugging. This function calls Cy_SysLib_ProcessingFault() after storing all
1375 * information.
1376 *
1377 * \param faultStackAddr The address of the stack pointer, indicates the lowest
1378 * address in the fault stack frame to be stored.
1379 * \note This function stores the fault stack frame only for the first occurred
1380 * fault.
1381 * \note The PDL doesn't provide an API to analyze the stored register
1382 * values. The user has to add additional functions for the analysis,
1383 * if necessary.
1384 * \note The CY_ARM_FAULT_DEBUG macro defines if the Fault Handler is enabled.
1385 * By default it is set to CY_ARM_FAULT_DEBUG_ENABLED and enables the
1386 * Fault Handler.
1387 * If there is a necessity to save memory or have some specific custom
1388 * handler, etc. then CY_ARM_FAULT_DEBUG should be redefined as
1389 * CY_ARM_FAULT_DEBUG_DISABLED. To do this, the following definition should
1390 * be added to the compiler Command Line (through the project Build
1391 * Settings): "-D CY_ARM_FAULT_DEBUG=0".
1392 *
1393 *******************************************************************************/
1394 void Cy_SysLib_FaultHandler(uint32_t const *faultStackAddr);
1395
1396
1397 /*******************************************************************************
1398 * Function Name: Cy_SysLib_ProcessingFault
1399 ****************************************************************************//**
1400 *
1401 * This function determines how to process the current fault state. By default
1402 * in case of exception the system will stay in the infinite loop of this
1403 * function.
1404 *
1405 * \note This function has the WEAK option, so the user can redefine the function
1406 * behavior for a custom processing.
1407 * For example, the function redefinition could be constructed from fault
1408 * stack processing and NVIC_SystemReset() function call.
1409 *
1410 *******************************************************************************/
1411 void Cy_SysLib_ProcessingFault(void);
1412 #endif /* (CY_ARM_FAULT_DEBUG == CY_ARM_FAULT_DEBUG_ENABLED) */
1413
1414 /*******************************************************************************
1415 * Function Name: Cy_SysLib_SetWaitStates
1416 ****************************************************************************//**
1417 *
1418 * Sets the number of clock cycles the cache will wait for, before it samples
1419 * data coming back from ROM, SRAM, and Flash.
1420 *
1421 * Call this function before increasing the HFClk0 High Frequency clock.
1422 * Call this function optionally after lowering the HFClk0 High Frequency clock
1423 * in order to improve the CPU performance.
1424 *
1425 * Also, call this function before switching the core supply regulator voltage
1426 * (LDO or SIMO Buck) from 1.1V to 0.9V.
1427 * Call this function optionally after switching the core supply regulator
1428 * voltage from 0.9V to 1.1V in order to improve the CPU performance.
1429 *
1430 * \param ulpMode The device power mode.
1431 * true if the device should be switched to the ULP mode (nominal
1432 * voltage of the core supply regulator should be switched to 0.9V);
1433 * false if the device should be switched to the LP mode (nominal
1434 * voltage of the core supply regulator should be switched to 1.1V).
1435 *
1436 * \note Refer to the device TRM for the low power modes description.
1437 *
1438 * \param clkHfMHz The HFClk0 clock frequency in MHz. Specifying a frequency
1439 * above the supported maximum will set the wait states as for
1440 * the maximum frequency.
1441 *
1442 *******************************************************************************/
1443 void Cy_SysLib_SetWaitStates(bool ulpMode, uint32_t clkHfMHz);
1444
1445
1446 /*******************************************************************************
1447 * Function Name: Cy_SysLib_EnterCriticalSection
1448 ****************************************************************************//**
1449 *
1450 * Cy_SysLib_EnterCriticalSection disables interrupts and returns a value
1451 * indicating whether the interrupts were previously enabled.
1452 *
1453 * \return Returns the current interrupt status. Returns 0 if the interrupts
1454 * were previously enabled or 1 if the interrupts were previously
1455 * disabled.
1456 *
1457 * \note Implementation of Cy_SysLib_EnterCriticalSection manipulates the IRQ
1458 * enable bit with interrupts still enabled.
1459 *
1460 *******************************************************************************/
1461 uint32_t Cy_SysLib_EnterCriticalSection(void);
1462
1463
1464 /*******************************************************************************
1465 * Function Name: Cy_SysLib_ExitCriticalSection
1466 ****************************************************************************//**
1467 *
1468 * Re-enables the interrupts if they were enabled before
1469 * Cy_SysLib_EnterCriticalSection() was called. The argument should be the value
1470 * returned from \ref Cy_SysLib_EnterCriticalSection().
1471 *
1472 * \param savedIntrStatus Puts the saved interrupts status returned by
1473 * the \ref Cy_SysLib_EnterCriticalSection().
1474 *
1475 *******************************************************************************/
1476 void Cy_SysLib_ExitCriticalSection(uint32_t savedIntrStatus);
1477
1478
1479 /*******************************************************************************
1480 * Function Name: Cy_SysLib_GetDeviceRevision
1481 ****************************************************************************//**
1482 *
1483 * This function returns a device Revision ID.
1484 *
1485 * \return A device Revision ID.
1486 *
1487 *******************************************************************************/
1488 uint8_t Cy_SysLib_GetDeviceRevision(void);
1489
1490 /*******************************************************************************
1491 * Function Name: Cy_SysLib_GetDevice
1492 ****************************************************************************//**
1493 *
1494 * This function returns a device Family ID.
1495 *
1496 * \return A device Family ID.
1497 *
1498 *******************************************************************************/
1499 uint16_t Cy_SysLib_GetDevice(void);
1500
1501 #if defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1502 /*******************************************************************************
1503 * Function Name: Cy_SysLib_GetDeviceLCS
1504 ****************************************************************************//**
1505 *
1506 * This function returns LCS of Device.
1507 *
1508 * \return \ref cy_en_syslib_lcs_mode_t
1509 *
1510 *******************************************************************************/
1511 cy_en_syslib_lcs_mode_t Cy_SysLib_GetDeviceLCS(void);
1512 #endif /* defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) */
1513
1514 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1515 /*******************************************************************************
1516 * Function Name: Cy_Syslib_SetWarmBootEntryPoint
1517 ****************************************************************************//**
1518 *
1519 * This function will set Warm boot entry point address to a location read by
1520 * BootROM. This function is used only before entering DeepSleep-RAM and not
1521 * effective in any other sleep mode. Before entering CY_SYSPM_MODE_DEEPSLEEP_RAM,
1522 * user needs to set entry point to a function located in RAM Image using
1523 * Cy_Syslib_SetWarmBootEntryPoint(), refer Cy_SysPm_SetDeepSleepMode().
1524 *
1525 * \param entryPoint Address of the function that needs to be entered after
1526 * WARM boot.
1527 *
1528 * \param enable Enables/Disables debugging control after DS-RAM wakeup
1529 * i.e. warmboot
1530 *
1531 * \note
1532 * This API is available for CAT1B devices.
1533 *
1534 *******************************************************************************/
1535 void Cy_Syslib_SetWarmBootEntryPoint(uint32_t *entryPoint, bool enable);
1536
1537 /*******************************************************************************
1538 * Function Name: Cy_SysLib_IsDSRAMWarmBootEntry
1539 ****************************************************************************//**
1540 *
1541 * This function will return true if the system woke up(From DS-RAM) through
1542 * Warm boot, else it will return false.
1543 *
1544 * \return Warm Boot Status.
1545 *
1546 * \note
1547 * This API is available for CAT1B devices.
1548 *
1549 *******************************************************************************/
1550 bool Cy_SysLib_IsDSRAMWarmBootEntry(void);
1551
1552 /*******************************************************************************
1553 * Function Name: Cy_SysLib_ClearDSRAMWarmBootEntryStatus
1554 ****************************************************************************//**
1555 *
1556 * This function clears the Warm Boot entry Status flag.
1557 *
1558 * \note
1559 * This API is available for CAT1B devices.
1560 *
1561 *******************************************************************************/
1562 void Cy_SysLib_ClearDSRAMWarmBootEntryStatus(void);
1563 #endif
1564
1565
1566 /** \cond INTERNAL */
1567 #define CY_SYSLIB_DEVICE_REV_0A (0x21U) /**< The device TO *A Revision ID */
1568 #define CY_SYSLIB_DEVICE_PSOC6ABLE2 (0x100U) /**< The PSoC6 BLE2 device Family ID */
1569
1570 /* SILICON ID Macros */
1571 #define CY_SYSLIB_GET_SILICON_REV_ID (CY_SILICON_ID & 0xFFFFUL)
1572
1573 /* For CAT1B Devices */
1574 #define CY_SYSLIB_20829A0_SILICON_REV (0x1110UL) /**< 20829A0 SILICON ID = <Major Revision((4 bits): Family ID(12 bits)> */
1575 #define CY_SYSLIB_20829B0_SILICON_REV (0x2110UL) /**< 20829B0 SILICON ID = <Major Revision((4 bits): Family ID(12 bits)> */
1576
1577 typedef uint32_t cy_status;
1578 /** The ARM 32-bit status value for backward compatibility with the UDB components. Do not use it in your code. */
1579 typedef uint32_t cystatus;
1580 typedef uint8_t uint8; /**< Alias to uint8_t for backward compatibility */
1581 typedef uint16_t uint16; /**< Alias to uint16_t for backward compatibility */
1582 typedef uint32_t uint32; /**< Alias to uint32_t for backward compatibility */
1583 typedef int8_t int8; /**< Alias to int8_t for backward compatibility */
1584 typedef int16_t int16; /**< Alias to int16_t for backward compatibility */
1585 typedef int32_t int32; /**< Alias to int32_t for backward compatibility */
1586 typedef float float32; /**< Alias to float for backward compatibility */
1587 typedef double float64; /**< Alias to double for backward compatibility */
1588 typedef int64_t int64; /**< Alias to int64_t for backward compatibility */
1589 typedef uint64_t uint64; /**< Alias to uint64_t for backward compatibility */
1590 /* Signed or unsigned depending on the compiler selection */
1591 typedef char char8; /**< Alias to char for backward compatibility */
1592 typedef volatile uint8_t reg8; /**< Alias to uint8_t for backward compatibility */
1593 typedef volatile uint16_t reg16; /**< Alias to uint16_t for backward compatibility */
1594 typedef volatile uint32_t reg32; /**< Alias to uint32_t for backward compatibility */
1595
1596 /** The ARM 32-bit Return error / status code for backward compatibility.
1597 * Do not use them in your code.
1598 */
1599 #define CY_RET_SUCCESS (0x00U) /* Successful */
1600 #define CY_RET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1601 #define CY_RET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1602 #define CY_RET_MEMORY (0x03U) /* A memory-related failure */
1603 #define CY_RET_LOCKED (0x04U) /* A resource lock failure */
1604 #define CY_RET_EMPTY (0x05U) /* No more objects available */
1605 #define CY_RET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1606 #define CY_RET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1607 #define CY_RET_FINISHED (0x08U) /* Operation is completed */
1608 #define CY_RET_CANCELED (0x09U) /* Operation is canceled */
1609 #define CY_RET_TIMEOUT (0x10U) /* Operation timed out */
1610 #define CY_RET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1611 #define CY_RET_UNKNOWN ((cy_status) 0xFFFFFFFFU) /* Unknown failure */
1612
1613 /** ARM 32-bit Return error / status codes for backward compatibility with the UDB components.
1614 * Do not use them in your code.
1615 */
1616 #define CYRET_SUCCESS (0x00U) /* Successful */
1617 #define CYRET_BAD_PARAM (0x01U) /* One or more invalid parameters */
1618 #define CYRET_INVALID_OBJECT (0x02U) /* An invalid object specified */
1619 #define CYRET_MEMORY (0x03U) /* A memory-related failure */
1620 #define CYRET_LOCKED (0x04U) /* A resource lock failure */
1621 #define CYRET_EMPTY (0x05U) /* No more objects available */
1622 #define CYRET_BAD_DATA (0x06U) /* Bad data received (CRC or other error check) */
1623 #define CYRET_STARTED (0x07U) /* Operation started, but not necessarily completed yet */
1624 #define CYRET_FINISHED (0x08U) /* Operation is completed */
1625 #define CYRET_CANCELED (0x09U) /* Operation is canceled */
1626 #define CYRET_TIMEOUT (0x10U) /* Operation timed out */
1627 #define CYRET_INVALID_STATE (0x11U) /* Operation is not setup or is in an improper state */
1628 #define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFU) /* Unknown failure */
1629
1630 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1631 typedef void (* cyisraddress)(void);
1632 #if defined (__ICCARM__)
1633 /** A type of ISR callbacks for backward compatibility with the UDB components. Do not use it in your code. */
1634 typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
1635 #endif /* defined (__ICCARM__) */
1636
1637 /** The backward compatibility define for the CyDelay() API for the UDB components.
1638 * Do not use it in your code.
1639 */
1640 #define CyDelay Cy_SysLib_Delay
1641 /** The backward compatibility define for the CyDelayUs() API for the UDB components.
1642 * Do not use it in your code.
1643 */
1644 #define CyDelayUs Cy_SysLib_DelayUs
1645 /** The backward compatibility define for the CyDelayCycles() API for the UDB components.
1646 * Do not use it in your code.
1647 */
1648 #define CyDelayCycles Cy_SysLib_DelayCycles
1649 /** The backward compatibility define for the CyEnterCriticalSection() API for the UDB components.
1650 * Do not use it in your code.
1651 */
1652 #define CyEnterCriticalSection() ((uint8_t) Cy_SysLib_EnterCriticalSection())
1653 /** The backward compatibility define for the CyExitCriticalSection() API for the UDB components.
1654 * Do not use it in your code.
1655 */
1656 #define CyExitCriticalSection(x) (Cy_SysLib_ExitCriticalSection((uint32_t) (x)))
1657 /** \endcond */
1658
1659 /** \} group_syslib_functions */
1660 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
1661 /** \cond INTERNAL */
1662
1663 /** \endcond */
1664
1665
1666 #if defined(__cplusplus)
1667 }
1668 #endif /* defined(__cplusplus) */
1669
1670 #endif /* CY_IP_M33SYSCPUSS, CY_IP_M4CPUSS */
1671
1672 #endif /* CY_SYSLIB_H */
1673
1674 /** \} group_syslib */
1675
1676 /* [] END OF FILE */
1677
