| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_tcpwm_pwm.c | 61 …us_t Cy_TCPWM_PWM_Init(TCPWM_Type *base, uint32_t cntNum, cy_stc_tcpwm_pwm_config_t const *config) in Cy_TCPWM_PWM_Init() argument
65 if ((NULL != base) && (NULL != config)) in Cy_TCPWM_PWM_Init()
70 ((config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0UL) | in Cy_TCPWM_PWM_Init()
71 (config->enablePeriodSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk : 0UL) | in Cy_TCPWM_PWM_Init()
72 _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) | in Cy_TCPWM_PWM_Init()
73 _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->pwmAlignment) | in Cy_TCPWM_PWM_Init()
74 _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->pwmMode) | in Cy_TCPWM_PWM_Init()
76 (config->invertPWMOut | (config->invertPWMOutN << 1U))) | in Cy_TCPWM_PWM_Init()
77 (config->killMode << CY_TCPWM_PWM_CTRL_SYNC_KILL_OR_STOP_ON_KILL_POS) | in Cy_TCPWM_PWM_Init()
78 … _VAL2FLD(TCPWM_CNT_CTRL_GENERIC, ((CY_TCPWM_PWM_MODE_DEADTIME == config->pwmMode) ? in Cy_TCPWM_PWM_Init()
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| D | cy_tcpwm_counter.c | 58 cy_stc_tcpwm_counter_config_t const *config) in Cy_TCPWM_Counter_Init() argument
62 if ((NULL != base) && (NULL != config)) in Cy_TCPWM_Counter_Init()
66 … TCPWM_CNT_CTRL(base, cntNum) = (_VAL2FLD(TCPWM_CNT_CTRL_GENERIC, config->clockPrescaler) | in Cy_TCPWM_Counter_Init()
67 _VAL2FLD(TCPWM_CNT_CTRL_ONE_SHOT, config->runMode) | in Cy_TCPWM_Counter_Init()
68 … _VAL2FLD(TCPWM_CNT_CTRL_UP_DOWN_MODE, config->countDirection) | in Cy_TCPWM_Counter_Init()
69 _VAL2FLD(TCPWM_CNT_CTRL_MODE, config->compareOrCapture) | in Cy_TCPWM_Counter_Init()
70 … (config->enableCompareSwap ? TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk : 0UL)); in Cy_TCPWM_Counter_Init()
72 if (CY_TCPWM_COUNTER_COUNT_UP == config->countDirection) in Cy_TCPWM_Counter_Init()
76 else if (CY_TCPWM_COUNTER_COUNT_DOWN == config->countDirection) in Cy_TCPWM_Counter_Init()
78 TCPWM_CNT_COUNTER(base, cntNum) = config->period; in Cy_TCPWM_Counter_Init()
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| D | cy_i2s.c | 51 cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config) in Cy_I2S_Init() argument
55 if((NULL != base) && (NULL != config)) in Cy_I2S_Init()
60 uint32_t clockDiv = (uint32_t)config->clkDiv - 1U; in Cy_I2S_Init()
73 _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk) | in Cy_I2S_Init()
74 _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, config->mclkDiv) | in Cy_I2S_Init()
75 _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->mclkEn); in Cy_I2S_Init()
78 _BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk); in Cy_I2S_Init()
81 if (config->txEnabled) in Cy_I2S_Init()
83 CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); in Cy_I2S_Init()
84 CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue)); in Cy_I2S_Init()
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| D | cy_tdm.c | 28 …dm_status_t Cy_AudioTDM_TX_Init( TDM_TX_STRUCT_Type * base, cy_stc_tdm_config_tx_t const * config);
31 …dm_status_t Cy_AudioTDM_RX_Init( TDM_RX_STRUCT_Type * base, cy_stc_tdm_config_rx_t const * config);
58 cy_en_tdm_status_t Cy_AudioTDM_Init( TDM_STRUCT_Type * base, cy_stc_tdm_config_t const * config) in Cy_AudioTDM_Init() argument
62 if((NULL != base) && (NULL != config)) in Cy_AudioTDM_Init()
64 if(config->tx_config->enable) in Cy_AudioTDM_Init()
66 ret = Cy_AudioTDM_TX_Init(&(base->TDM_TX_STRUCT),(config->tx_config)); in Cy_AudioTDM_Init()
72 if(config->rx_config->enable) in Cy_AudioTDM_Init()
74 ret = Cy_AudioTDM_RX_Init(&(base->TDM_RX_STRUCT),(config->rx_config)); in Cy_AudioTDM_Init()
101 …tdm_status_t Cy_AudioTDM_TX_Init( TDM_TX_STRUCT_Type * base, cy_stc_tdm_config_tx_t const * config) in Cy_AudioTDM_TX_Init() argument
104 uint16_t clockDiv = config->clkDiv -1U; in Cy_AudioTDM_TX_Init()
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| D | cy_pdm_pcm_v2.c | 122 cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config) in Cy_PDM_PCM_Init() argument
126 if((NULL != base) && (NULL != config)) in Cy_PDM_PCM_Init()
128 CY_ASSERT_L2(CY_PDM_PCM_IS_CLK_SEL_VALID(config->clksel)); in Cy_PDM_PCM_Init()
129 CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(config->halverate)); in Cy_PDM_PCM_Init()
130 CY_ASSERT_L2(CY_PDM_PCM_IS_ROUTE_VALID(config->route)); in Cy_PDM_PCM_Init()
135 PDM_PCM_CLOCK_CTL(base) = _VAL2FLD(PDM_CLOCK_CTL_CLOCK_DIV, config->clkDiv) | in Cy_PDM_PCM_Init()
136 _VAL2FLD(PDM_CLOCK_CTL_CLOCK_SEL, config->clksel) | in Cy_PDM_PCM_Init()
137 _VAL2FLD(PDM_CLOCK_CTL_HALVE, config->halverate); in Cy_PDM_PCM_Init()
140 PDM_PCM_ROUTE_CTL(base) = _VAL2FLD(PDM_ROUTE_CTL_DATA_SEL, config->route); in Cy_PDM_PCM_Init()
142 if(config->fir0_coeff_user_value != 0U) in Cy_PDM_PCM_Init()
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| D | cy_dmac.c | 63 …criptor_Init(cy_stc_dmac_descriptor_t * descriptor, const cy_stc_dmac_descriptor_config_t * config) in Cy_DMAC_Descriptor_Init() argument
67 if ((NULL != descriptor) && (NULL != config)) in Cy_DMAC_Descriptor_Init()
69 CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(config->retrigger)); in Cy_DMAC_Descriptor_Init()
70 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->interruptType)); in Cy_DMAC_Descriptor_Init()
71 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerOutType)); in Cy_DMAC_Descriptor_Init()
72 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerInType)); in Cy_DMAC_Descriptor_Init()
73 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->srcTransferSize)); in Cy_DMAC_Descriptor_Init()
74 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->dstTransferSize)); in Cy_DMAC_Descriptor_Init()
75 CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(config->channelState)); in Cy_DMAC_Descriptor_Init()
76 CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(config->dataSize)); in Cy_DMAC_Descriptor_Init()
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| D | cy_dma.c | 102 …escriptor_Init(cy_stc_dma_descriptor_t * descriptor, const cy_stc_dma_descriptor_config_t * config) in Cy_DMA_Descriptor_Init() argument
106 if ((NULL != descriptor) && (NULL != config)) in Cy_DMA_Descriptor_Init()
108 CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(config->retrigger)); in Cy_DMA_Descriptor_Init()
109 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->interruptType)); in Cy_DMA_Descriptor_Init()
110 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerOutType)); in Cy_DMA_Descriptor_Init()
111 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerInType)); in Cy_DMA_Descriptor_Init()
112 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->srcTransferSize)); in Cy_DMA_Descriptor_Init()
113 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->dstTransferSize)); in Cy_DMA_Descriptor_Init()
114 CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState)); in Cy_DMA_Descriptor_Init()
115 CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize)); in Cy_DMA_Descriptor_Init()
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| D | cy_pdm_pcm.c | 53 cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t const * config) in Cy_PDM_PCM_Init() argument
57 if((NULL != base) && (NULL != config)) in Cy_PDM_PCM_Init()
59 CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->clkDiv)); in Cy_PDM_PCM_Init()
60 CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->mclkDiv)); in Cy_PDM_PCM_Init()
61 CY_ASSERT_L3(CY_PDM_PCM_IS_CKO_CLOCK_DIV_VALID(config->ckoDiv)); in Cy_PDM_PCM_Init()
62 CY_ASSERT_L3(CY_PDM_PCM_IS_SINC_RATE_VALID(config->sincDecRate)); in Cy_PDM_PCM_Init()
63 CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainRight)); in Cy_PDM_PCM_Init()
64 CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainLeft)); in Cy_PDM_PCM_Init()
65 CY_ASSERT_L3(CY_PDM_PCM_IS_STEP_SEL_VALID(config->softMuteFineGain)); in Cy_PDM_PCM_Init()
66 CY_ASSERT_L3(CY_PDM_PCM_IS_CH_SET_VALID(config->chanSelect)); in Cy_PDM_PCM_Init()
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| D | cy_tcpwm_quaddec.c | 58 cy_stc_tcpwm_quaddec_config_t const *config) in Cy_TCPWM_QuadDec_Init() argument
62 if ((NULL != base) && (NULL != config)) in Cy_TCPWM_QuadDec_Init()
66 if(config->resolution <= CY_TCPWM_QUADDEC_X4) in Cy_TCPWM_QuadDec_Init()
68 … TCPWM_CNT_CTRL(base, cntNum) = ( _VAL2FLD(TCPWM_CNT_CTRL_QUADRATURE_MODE, config->resolution) | in Cy_TCPWM_QuadDec_Init()
71 if (CY_TCPWM_INPUT_CREATOR != config->phiAInput) in Cy_TCPWM_QuadDec_Init()
73 … TCPWM_CNT_TR_CTRL0(base, cntNum) = (_VAL2FLD(TCPWM_CNT_TR_CTRL0_COUNT_SEL, config->phiAInput) | in Cy_TCPWM_QuadDec_Init()
74 _VAL2FLD(TCPWM_CNT_TR_CTRL0_START_SEL, config->phiBInput) | in Cy_TCPWM_QuadDec_Init()
75 _VAL2FLD(TCPWM_CNT_TR_CTRL0_RELOAD_SEL, config->indexInput) | in Cy_TCPWM_QuadDec_Init()
76 _VAL2FLD(TCPWM_CNT_TR_CTRL0_STOP_SEL, config->stopInput)); in Cy_TCPWM_QuadDec_Init()
82 _VAL2FLD(TCPWM_CNT_TR_CTRL1_RELOAD_EDGE, config->indexInputMode) | in Cy_TCPWM_QuadDec_Init()
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| D | cy_csd.c | 76 cy_en_csd_status_t Cy_CSD_Init(CSD_Type * base, cy_stc_csd_config_t const * config, cy_en_csd_key_t… in Cy_CSD_Init() argument
80 if ((NULL == base) || (CY_CSD_NONE_KEY == key) || (NULL == config) || (NULL == context)) in Cy_CSD_Init()
89 csdStatus = Cy_CSD_Configure(base, config, key, context); in Cy_CSD_Init()
224 cy_en_csd_status_t Cy_CSD_Configure(CSD_Type * base, const cy_stc_csd_config_t * config, cy_en_csd_… in Cy_CSD_Configure() argument
238 base->CONFIG = config->config; in Cy_CSD_Configure()
239 base->SPARE = config->spare; in Cy_CSD_Configure()
240 base->INTR = config->intr; in Cy_CSD_Configure()
241 base->INTR_SET = config->intrSet; in Cy_CSD_Configure()
242 base->INTR_MASK = config->intrMask; in Cy_CSD_Configure()
243 base->HSCMP = config->hscmp; in Cy_CSD_Configure()
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| D | cy_sysclk_v2.c | 2903 cy_stc_fll_manual_config_t config; in Cy_SysClk_FllConfigure() local
2907 config.outputMode = outputMode; in Cy_SysClk_FllConfigure()
2909 config.enableOutputDiv = true; in Cy_SysClk_FllConfigure()
2913 config.ccoRange = ((ccoFreq >= 150339200UL) ? CY_SYSCLK_FLL_CCO_RANGE4 : in Cy_SysClk_FllConfigure()
2921 …config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (u… in Cy_SysClk_FllConfigure()
2925 …config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uin… in Cy_SysClk_FllConfigure()
2931 … config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); in Cy_SysClk_FllConfigure()
2940 uint32_t kcco = (trimSteps[config.ccoRange] * margin[config.ccoRange]); in Cy_SysClk_FllConfigure()
2941 …B_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64_t)kcco * (uint64_t)config.refDiv); in Cy_SysClk_FllConfigure()
2948 for(config.igain = CY_SYSCLK_FLL_GAIN_IDX; config.igain != 0UL; config.igain--) in Cy_SysClk_FllConfigure()
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| D | cy_prot.c | 259 …ot_status_t Cy_Prot_ConfigMpuStruct(PROT_MPU_MPU_STRUCT_Type* base, const cy_stc_mpu_cfg_t* config) in Cy_Prot_ConfigMpuStruct() argument
266 CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->userPermission)); in Cy_Prot_ConfigMpuStruct()
267 CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->privPermission)); in Cy_Prot_ConfigMpuStruct()
268 CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize)); in Cy_Prot_ConfigMpuStruct()
270 addrReg = _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE, config->subregions) in Cy_Prot_ConfigMpuStruct()
271 …| _VAL2FLD(PROT_MPU_MPU_STRUCT_ADDR_ADDR24, (uint32_t)((uint32_t)config->address >> CY_PROT_ADDR_S… in Cy_Prot_ConfigMpuStruct()
272 attReg = ((uint32_t)config->userPermission & CY_PROT_ATT_PERMISSION_MASK) in Cy_Prot_ConfigMpuStruct()
273 …| (((uint32_t)config->privPermission & CY_PROT_ATT_PERMISSION_MASK) << CY_PROT_ATT_PRIV_PERMISSION… in Cy_Prot_ConfigMpuStruct()
274 | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_NS, !(config->secure)) in Cy_Prot_ConfigMpuStruct()
275 | _VAL2FLD(PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE, config->regionSize); in Cy_Prot_ConfigMpuStruct()
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| D | cy_smartio.c | 58 …_en_smartio_status_t Cy_SmartIO_Init(SMARTIO_PRT_Type* base, const cy_stc_smartio_config_t* config) in Cy_SmartIO_Init() argument
62 if(NULL != config) in Cy_SmartIO_Init()
64 SMARTIO_PRT_CTL(base) = _VAL2FLD(SMARTIO_PRT_CTL_BYPASS, config->bypassMask) in Cy_SmartIO_Init()
65 | _VAL2FLD(SMARTIO_PRT_CTL_CLOCK_SRC, config->clkSrc) in Cy_SmartIO_Init()
66 | _VAL2FLD(SMARTIO_PRT_CTL_HLD_OVR, config->hldOvr) in Cy_SmartIO_Init()
69 SMARTIO_PRT_SYNC_CTL(base) = _VAL2FLD(SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN, config->ioSyncEn) in Cy_SmartIO_Init()
70 | _VAL2FLD(SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN, config->chipSyncEn); in Cy_SmartIO_Init()
73 if(NULL != config->lutCfg0) in Cy_SmartIO_Init()
75 … SMARTIO_PRT_LUT_SEL(base, 0) = _VAL2FLD(SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL, config->lutCfg0->tr0) in Cy_SmartIO_Init()
76 … | _VAL2FLD(SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL, config->lutCfg0->tr1) in Cy_SmartIO_Init()
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| D | cy_tcpwm_shiftreg.c | 54 …iftReg_Init(TCPWM_Type const *base, uint32_t cntNum, cy_stc_tcpwm_shiftreg_config_t const *config) in Cy_TCPWM_ShiftReg_Init() argument
59 if ((NULL != base) && (NULL != config)) in Cy_TCPWM_ShiftReg_Init()
66 (config->enableCompare0Swap ? TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk : 0UL) | in Cy_TCPWM_ShiftReg_Init()
68 (config->invertShiftRegOut | (config->invertShiftRegOutN << 1U))) | in Cy_TCPWM_ShiftReg_Init()
69 _VAL2FLD(TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE, config->shiftRegOnDisable) | in Cy_TCPWM_ShiftReg_Init()
71 _VAL2FLD(TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED, config->buffer_swap_enable) | in Cy_TCPWM_ShiftReg_Init()
75 …(base, grp, cntNum) = _VAL2FLD(TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L, (uint8_t)config->clockPrescaler); in Cy_TCPWM_ShiftReg_Init()
77 TCPWM_GRP_CNT_CC0(base, grp, cntNum) = config->compare0; in Cy_TCPWM_ShiftReg_Init()
78 TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) = config->compareBuf0; in Cy_TCPWM_ShiftReg_Init()
80 TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) = config->tapsEnabled; in Cy_TCPWM_ShiftReg_Init()
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| D | cy_mcwdt.c | 56 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config) in Cy_MCWDT_Init() argument
60 if ((base != NULL) && (config != NULL)) in Cy_MCWDT_Init()
62 CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c0ClearOnMatch, config->c0Match)); in Cy_MCWDT_Init()
63 CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID(config->c1ClearOnMatch, config->c1Match)); in Cy_MCWDT_Init()
64 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(config->c2ToggleBit)); in Cy_MCWDT_Init()
65 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c0Mode)); in Cy_MCWDT_Init()
66 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c1Mode)); in Cy_MCWDT_Init()
67 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID((cy_en_mcwdtmode_t)config->c2Mode)); in Cy_MCWDT_Init()
69 MCWDT_MATCH(base) = _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, config->c1Match) | in Cy_MCWDT_Init()
70 … _VAL2FLD(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, config->c0Match); in Cy_MCWDT_Init()
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| D | cy_ctb.c | 292 cy_en_ctb_status_t Cy_CTB_Init(CTBM_Type *base, const cy_stc_ctb_config_t *config) in Cy_CTB_Init() argument
295 CY_ASSERT_L1(NULL != config); in Cy_CTB_Init()
299 if ((NULL == base) || (NULL == config)) in Cy_CTB_Init()
305 CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); in Cy_CTB_Init()
308 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power)); in Cy_CTB_Init()
309 CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode)); in Cy_CTB_Init()
310 CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump)); in Cy_CTB_Init()
311 CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge)); in Cy_CTB_Init()
312 CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel)); in Cy_CTB_Init()
313 CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass)); in Cy_CTB_Init()
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| D | cy_ctdac.c | 83 cy_en_ctdac_status_t Cy_CTDAC_Init(CTDAC_Type *base, const cy_stc_ctdac_config_t *config) in Cy_CTDAC_Init() argument
86 CY_ASSERT_L1(NULL != config); in Cy_CTDAC_Init()
93 if ((NULL == base) || (NULL == config)) in Cy_CTDAC_Init()
100 CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); in Cy_CTDAC_Init()
101 CY_ASSERT_L3(CY_CTDAC_FORMAT(config->formatMode)); in Cy_CTDAC_Init()
102 CY_ASSERT_L3(CY_CTDAC_UPDATE(config->updateMode)); in Cy_CTDAC_Init()
103 CY_ASSERT_L3(CY_CTDAC_DEGLITCH(config->deglitchMode)); in Cy_CTDAC_Init()
104 CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(config->outputMode)); in Cy_CTDAC_Init()
105 CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); in Cy_CTDAC_Init()
106 CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(config->deepSleep)); in Cy_CTDAC_Init()
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| D | cy_scb_spi.c | 68 cy_en_scb_spi_status_t Cy_SCB_SPI_Init(CySCB_Type *base, cy_stc_scb_spi_config_t const *config, cy_… in Cy_SCB_SPI_Init() argument
71 if ((NULL == base) || (NULL == config)) in Cy_SCB_SPI_Init()
78 CY_ASSERT_L3(CY_SCB_SPI_IS_MODE_VALID (config->spiMode)); in Cy_SCB_SPI_Init()
79 CY_ASSERT_L3(CY_SCB_SPI_IS_SUB_MODE_VALID (config->subMode)); in Cy_SCB_SPI_Init()
80 CY_ASSERT_L3(CY_SCB_SPI_IS_SCLK_MODE_VALID(config->sclkMode)); in Cy_SCB_SPI_Init()
82 CY_ASSERT_L2(CY_SCB_SPI_IS_OVERSAMPLE_VALID (config->oversample, config->spiMode)); in Cy_SCB_SPI_Init()
83 CY_ASSERT_L2(CY_SCB_SPI_IS_SS_POLARITY_VALID(config->ssPolarity)); in Cy_SCB_SPI_Init()
84 CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->rxDataWidth)); in Cy_SCB_SPI_Init()
85 CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->txDataWidth)); in Cy_SCB_SPI_Init()
86 …CY_ASSERT_L2(CY_SCB_SPI_IS_BOTH_DATA_WIDTH_VALID(config->subMode, config->rxDataWidth, config->txD… in Cy_SCB_SPI_Init()
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| D | cy_sysanalog.c | 98 cy_en_sysanalog_status_t Cy_SysAnalog_Init(const cy_stc_sysanalog_config_t * config) in Cy_SysAnalog_Init() argument
100 CY_ASSERT_L1(NULL != config); in Cy_SysAnalog_Init()
104 if (NULL != config) in Cy_SysAnalog_Init()
106 CY_ASSERT_L3(CY_SYSANALOG_DEEPSLEEP(config->deepSleep)); in Cy_SysAnalog_Init()
107 CY_ASSERT_L3(CY_SYSANALOG_VREF(config->vref)); in Cy_SysAnalog_Init()
108 CY_ASSERT_L3(CY_SYSANALOG_IZTAT(config->iztat)); in Cy_SysAnalog_Init()
112 | (uint32_t) config->iztat \ in Cy_SysAnalog_Init()
113 | (uint32_t) config->vref \ in Cy_SysAnalog_Init()
114 | (uint32_t) config->deepSleep; in Cy_SysAnalog_Init()
141 …t Cy_SysAnalog_DeepSleepInit(PASS_Type * base, const cy_stc_sysanalog_deep_sleep_config_t * config) in Cy_SysAnalog_DeepSleepInit() argument
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| D | cy_canfd.c | 262 const cy_stc_canfd_config_t *config, in Cy_CANFD_Init() argument
273 (NULL != config) && in Cy_CANFD_Init()
274 (NULL != config->bitrate) && in Cy_CANFD_Init()
275 (NULL != config->globalFilterConfig) && in Cy_CANFD_Init()
276 (NULL != config->rxFIFO0Config) && in Cy_CANFD_Init()
277 (NULL != config->rxFIFO1Config) in Cy_CANFD_Init()
281 CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(config->bitrate->prescaler)); in Cy_CANFD_Init()
282 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_1_VALID(config->bitrate->timeSegment1)); in Cy_CANFD_Init()
283 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_2_VALID(config->bitrate->timeSegment2)); in Cy_CANFD_Init()
284 CY_ASSERT_L2(CY_CANFD_IS_NOM_SYNC_JUMP_WIDTH_VALID(config->bitrate->syncJumpWidth)); in Cy_CANFD_Init()
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| D | cy_sar.c | 198 cy_en_sar_status_t Cy_SAR_Init(SAR_Type * base, const cy_stc_sar_config_t * config) in Cy_SAR_Init() argument
203 CY_ASSERT_L1(NULL != config); in Cy_SAR_Init()
205 if ((NULL != base) && (NULL != config)) in Cy_SAR_Init()
208 if (((0UL != (config->sampleCtrl & SAR_V2_SAMPLE_CTRL_AVG_MODE_Msk)) ? in Cy_SAR_Init()
209 !((0UL != (config->sampleCtrl & SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk)) != in Cy_SAR_Init()
210 (0UL != (config->sampleCtrl & SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk))) : true) && in Cy_SAR_Init()
212 ((NULL != config->fifoCfgPtr) ? !CY_PASS_V1 : true) && in Cy_SAR_Init()
214 ((CY_SAR_CLK_DEEPSLEEP == config->clock) ? !CY_PASS_V1 : true)) in Cy_SAR_Init()
223 CY_ASSERT_L2(CY_SAR_CTRL(config->ctrl)); in Cy_SAR_Init()
224 CY_ASSERT_L2(CY_SAR_SAMPLE_CTRL(config->sampleCtrl)); in Cy_SAR_Init()
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| D | cy_scb_uart.c | 266 cy_en_scb_uart_status_t Cy_SCB_UART_Init(CySCB_Type *base, cy_stc_scb_uart_config_t const *config, … in Cy_SCB_UART_Init() argument
268 if ((NULL == base) || (NULL == config)) in Cy_SCB_UART_Init()
273 CY_ASSERT_L3(CY_SCB_UART_IS_MODE_VALID (config->uartMode)); in Cy_SCB_UART_Init()
274 CY_ASSERT_L3(CY_SCB_UART_IS_STOP_BITS_VALID(config->stopBits)); in Cy_SCB_UART_Init()
275 CY_ASSERT_L3(CY_SCB_UART_IS_PARITY_VALID (config->parity)); in Cy_SCB_UART_Init()
276 CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->ctsPolarity)); in Cy_SCB_UART_Init()
277 CY_ASSERT_L3(CY_SCB_UART_IS_POLARITY_VALID (config->rtsPolarity)); in Cy_SCB_UART_Init()
279 …CY_ASSERT_L2(CY_SCB_UART_IS_OVERSAMPLE_VALID (config->oversample, config->uartMode, config->irdaE… in Cy_SCB_UART_Init()
280 CY_ASSERT_L2(CY_SCB_UART_IS_DATA_WIDTH_VALID (config->dataWidth)); in Cy_SCB_UART_Init()
281 CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_VALID (config->receiverAddress)); in Cy_SCB_UART_Init()
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| D | cy_crypto_core_trng.c | 81 void Cy_Crypto_Core_Trng_Init(CRYPTO_Type *base, cy_stc_crypto_trng_config_t *config) in Cy_Crypto_Core_Trng_Init() argument
85 if (NULL == config) in Cy_Crypto_Core_Trng_Init()
87 config = (cy_stc_crypto_trng_config_t *)&cy_trngDefaultConfig; in Cy_Crypto_Core_Trng_Init()
91 CY_ASSERT_L3(CY_CRYPTO_IS_BS_SELECT_VALID(config->monBitStreamSelect)); in Cy_Crypto_Core_Trng_Init()
100 REG_CRYPTO_TR_GARO_CTL(base) = config->garo31Poly; in Cy_Crypto_Core_Trng_Init()
101 REG_CRYPTO_TR_FIRO_CTL(base) = config->firo31Poly; in Cy_Crypto_Core_Trng_Init()
103 …REG_CRYPTO_TR_CTL0(base) = (uint32_t)(_VAL2FLD(CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV, config->sampleCloc… in Cy_Crypto_Core_Trng_Init()
104 … | _VAL2FLD(CRYPTO_TR_CTL0_RED_CLOCK_DIV, config->reducedClockDiv) in Cy_Crypto_Core_Trng_Init()
105 | _VAL2FLD(CRYPTO_TR_CTL0_INIT_DELAY, config->initDelay) in Cy_Crypto_Core_Trng_Init()
106 … | _VAL2FLD(CRYPTO_TR_CTL0_VON_NEUMANN_CORR, config->vnCorrectorEnable) in Cy_Crypto_Core_Trng_Init()
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| /hal_infineon-3.5.0/XMCLib/drivers/src/ |
| D | xmc_dsd.c | 173 void XMC_DSD_Generator_Init(XMC_DSD_t *const dsd, const XMC_DSD_GENERATOR_CONFIG_t *const config) in XMC_DSD_Generator_Init() argument
176 …XMC_ASSERT("XMC_DSD_GENERATOR_Init:NULL Pointer", (config != (XMC_DSD_GENERATOR_CONFIG_t *)NULL) ); in XMC_DSD_Generator_Init()
181 dsd ->CGCFG = config->generator_conf; in XMC_DSD_Generator_Init()
185 …DSD_STATUS_t XMC_DSD_CH_Init( XMC_DSD_CH_t *const channel, const XMC_DSD_CH_CONFIG_t *const config) in XMC_DSD_CH_Init() argument
190 XMC_ASSERT("XMC_DSD_CH_Init:NULL Pointer", (config != (XMC_DSD_CH_CONFIG_t *)NULL) ); in XMC_DSD_CH_Init()
192 if (config->filter != (XMC_DSD_CH_FILTER_CONFIG_t*)NULL) in XMC_DSD_CH_Init()
194 XMC_DSD_CH_MainFilter_Init(channel, config->filter); in XMC_DSD_CH_Init()
196 if (config->aux != (XMC_DSD_CH_AUX_FILTER_CONFIG_t*)NULL) in XMC_DSD_CH_Init()
198 XMC_DSD_CH_AuxFilter_Init(channel, config->aux); in XMC_DSD_CH_Init()
200 if (config->integrator != (XMC_DSD_CH_INTEGRATOR_CONFIG_t*)NULL) in XMC_DSD_CH_Init()
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| D | xmc_hrpwm.c | 280 void XMC_HRPWM_HRC_Init(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_CONFIG_t *const config) in XMC_HRPWM_HRC_Init() argument
285 hrc->GC = config->gc; in XMC_HRPWM_HRC_Init()
288 hrc->PL = config->psl; in XMC_HRPWM_HRC_Init()
292 …HRC_ConfigSourceSelect0(XMC_HRPWM_HRC_t *const hrc, const XMC_HRPWM_HRC_SRC_CONFIG_t *const config) in XMC_HRPWM_HRC_ConfigSourceSelect0() argument
300 hrc->GC |= ((uint32_t)config->high_res_mode) << HRPWM0_HRC_GC_HRM0_Pos; in XMC_HRPWM_HRC_ConfigSourceSelect0()
307 if(config->set_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) in XMC_HRPWM_HRC_ConfigSourceSelect0()
309 reg = ((uint32_t)config->cmp_set) << HRPWM0_HRC_GSEL_C0SS_Pos; in XMC_HRPWM_HRC_ConfigSourceSelect0()
313 if (config->clear_config == XMC_HRPWM_HRC_SRC_INPUT_CSG) in XMC_HRPWM_HRC_ConfigSourceSelect0()
315 reg |= ((uint32_t)config->cmp_clear) << HRPWM0_HRC_GSEL_C0CS_Pos; in XMC_HRPWM_HRC_ConfigSourceSelect0()
319 reg |= ((uint32_t)config->set_edge_config) << HRPWM0_HRC_GSEL_S0ES_Pos; in XMC_HRPWM_HRC_ConfigSourceSelect0()
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