TRIG_IN_MUX_1_TCPWM0_TR_OUT01 (reference) in projects: hal_infineon-3.5.0

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Searched refs:TRIG_IN_MUX_1_TCPWM0_TR_OUT01 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
D	cyw20829A0_config.h	`110 TRIG_IN_MUX_1_TCPWM0_TR_OUT01 = 0x0000010Bu, /* tcpwm[0].tr_out0[1] */ enumerator`
D	cyw20829B0_config.h	`111 TRIG_IN_MUX_1_TCPWM0_TR_OUT01 = 0x0000010Bu, /* tcpwm[0].tr_out0[1] */ enumerator`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
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