1 /***************************************************************************//**
2 * \file psoc6_01_config.h
3 *
4 * \brief
5 * PSoC6_01 device configuration header
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _PSOC6_01_CONFIG_H_
28 #define _PSOC6_01_CONFIG_H_
29 
30 /* Clock Connections */
31 typedef enum
32 {
33     PCLK_SCB0_CLOCK                 = 0x0000u,  /* scb[0].clock */
34     PCLK_SCB1_CLOCK                 = 0x0001u,  /* scb[1].clock */
35     PCLK_SCB2_CLOCK                 = 0x0002u,  /* scb[2].clock */
36     PCLK_SCB3_CLOCK                 = 0x0003u,  /* scb[3].clock */
37     PCLK_SCB4_CLOCK                 = 0x0004u,  /* scb[4].clock */
38     PCLK_SCB5_CLOCK                 = 0x0005u,  /* scb[5].clock */
39     PCLK_SCB6_CLOCK                 = 0x0006u,  /* scb[6].clock */
40     PCLK_SCB7_CLOCK                 = 0x0007u,  /* scb[7].clock */
41     PCLK_SCB8_CLOCK                 = 0x0008u,  /* scb[8].clock */
42     PCLK_UDB_CLOCKS0                = 0x0009u,  /* udb.clocks[0] */
43     PCLK_UDB_CLOCKS1                = 0x000Au,  /* udb.clocks[1] */
44     PCLK_UDB_CLOCKS2                = 0x000Bu,  /* udb.clocks[2] */
45     PCLK_UDB_CLOCKS3                = 0x000Cu,  /* udb.clocks[3] */
46     PCLK_UDB_CLOCKS4                = 0x000Du,  /* udb.clocks[4] */
47     PCLK_UDB_CLOCKS5                = 0x000Eu,  /* udb.clocks[5] */
48     PCLK_UDB_CLOCKS6                = 0x000Fu,  /* udb.clocks[6] */
49     PCLK_UDB_CLOCKS7                = 0x0010u,  /* udb.clocks[7] */
50     PCLK_SMARTIO8_CLOCK             = 0x0011u,  /* smartio[8].clock */
51     PCLK_SMARTIO9_CLOCK             = 0x0012u,  /* smartio[9].clock */
52     PCLK_TCPWM0_CLOCKS0             = 0x0013u,  /* tcpwm[0].clocks[0] */
53     PCLK_TCPWM0_CLOCKS1             = 0x0014u,  /* tcpwm[0].clocks[1] */
54     PCLK_TCPWM0_CLOCKS2             = 0x0015u,  /* tcpwm[0].clocks[2] */
55     PCLK_TCPWM0_CLOCKS3             = 0x0016u,  /* tcpwm[0].clocks[3] */
56     PCLK_TCPWM0_CLOCKS4             = 0x0017u,  /* tcpwm[0].clocks[4] */
57     PCLK_TCPWM0_CLOCKS5             = 0x0018u,  /* tcpwm[0].clocks[5] */
58     PCLK_TCPWM0_CLOCKS6             = 0x0019u,  /* tcpwm[0].clocks[6] */
59     PCLK_TCPWM0_CLOCKS7             = 0x001Au,  /* tcpwm[0].clocks[7] */
60     PCLK_TCPWM1_CLOCKS0             = 0x001Bu,  /* tcpwm[1].clocks[0] */
61     PCLK_TCPWM1_CLOCKS1             = 0x001Cu,  /* tcpwm[1].clocks[1] */
62     PCLK_TCPWM1_CLOCKS2             = 0x001Du,  /* tcpwm[1].clocks[2] */
63     PCLK_TCPWM1_CLOCKS3             = 0x001Eu,  /* tcpwm[1].clocks[3] */
64     PCLK_TCPWM1_CLOCKS4             = 0x001Fu,  /* tcpwm[1].clocks[4] */
65     PCLK_TCPWM1_CLOCKS5             = 0x0020u,  /* tcpwm[1].clocks[5] */
66     PCLK_TCPWM1_CLOCKS6             = 0x0021u,  /* tcpwm[1].clocks[6] */
67     PCLK_TCPWM1_CLOCKS7             = 0x0022u,  /* tcpwm[1].clocks[7] */
68     PCLK_TCPWM1_CLOCKS8             = 0x0023u,  /* tcpwm[1].clocks[8] */
69     PCLK_TCPWM1_CLOCKS9             = 0x0024u,  /* tcpwm[1].clocks[9] */
70     PCLK_TCPWM1_CLOCKS10            = 0x0025u,  /* tcpwm[1].clocks[10] */
71     PCLK_TCPWM1_CLOCKS11            = 0x0026u,  /* tcpwm[1].clocks[11] */
72     PCLK_TCPWM1_CLOCKS12            = 0x0027u,  /* tcpwm[1].clocks[12] */
73     PCLK_TCPWM1_CLOCKS13            = 0x0028u,  /* tcpwm[1].clocks[13] */
74     PCLK_TCPWM1_CLOCKS14            = 0x0029u,  /* tcpwm[1].clocks[14] */
75     PCLK_TCPWM1_CLOCKS15            = 0x002Au,  /* tcpwm[1].clocks[15] */
76     PCLK_TCPWM1_CLOCKS16            = 0x002Bu,  /* tcpwm[1].clocks[16] */
77     PCLK_TCPWM1_CLOCKS17            = 0x002Cu,  /* tcpwm[1].clocks[17] */
78     PCLK_TCPWM1_CLOCKS18            = 0x002Du,  /* tcpwm[1].clocks[18] */
79     PCLK_TCPWM1_CLOCKS19            = 0x002Eu,  /* tcpwm[1].clocks[19] */
80     PCLK_TCPWM1_CLOCKS20            = 0x002Fu,  /* tcpwm[1].clocks[20] */
81     PCLK_TCPWM1_CLOCKS21            = 0x0030u,  /* tcpwm[1].clocks[21] */
82     PCLK_TCPWM1_CLOCKS22            = 0x0031u,  /* tcpwm[1].clocks[22] */
83     PCLK_TCPWM1_CLOCKS23            = 0x0032u,  /* tcpwm[1].clocks[23] */
84     PCLK_CSD_CLOCK                  = 0x0033u,  /* csd.clock */
85     PCLK_LCD_CLOCK                  = 0x0034u,  /* lcd.clock */
86     PCLK_PROFILE_CLOCK_PROFILE      = 0x0035u,  /* profile.clock_profile */
87     PCLK_CPUSS_CLOCK_TRACE_IN       = 0x0036u,  /* cpuss.clock_trace_in */
88     PCLK_PASS_CLOCK_CTDAC           = 0x0037u,  /* pass.clock_ctdac */
89     PCLK_PASS_CLOCK_PUMP_PERI       = 0x0038u,  /* pass.clock_pump_peri */
90     PCLK_PASS_CLOCK_SAR             = 0x0039u,  /* pass.clock_sar */
91     PCLK_USB_CLOCK_DEV_BRS          = 0x003Au   /* usb.clock_dev_brs */
92 } en_clk_dst_t;
93 
94 /* Trigger Group */
95 /* This section contains the enums related to the Trigger multiplexer (TrigMux) driver.
96 * Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details.
97 */
98 /* Trigger Group Inputs */
99 /* Trigger Input Group 0 - DMA Request Assignments */
100 typedef enum
101 {
102     TRIG0_IN_CPUSS_ZERO             = 0x00000000u, /* cpuss.zero */
103     TRIG0_IN_TR_GROUP10_OUTPUT0     = 0x00000001u, /* tr_group[10].output[0] */
104     TRIG0_IN_TR_GROUP10_OUTPUT1     = 0x00000002u, /* tr_group[10].output[1] */
105     TRIG0_IN_TR_GROUP10_OUTPUT2     = 0x00000003u, /* tr_group[10].output[2] */
106     TRIG0_IN_TR_GROUP10_OUTPUT3     = 0x00000004u, /* tr_group[10].output[3] */
107     TRIG0_IN_TR_GROUP10_OUTPUT4     = 0x00000005u, /* tr_group[10].output[4] */
108     TRIG0_IN_TR_GROUP10_OUTPUT5     = 0x00000006u, /* tr_group[10].output[5] */
109     TRIG0_IN_TR_GROUP10_OUTPUT6     = 0x00000007u, /* tr_group[10].output[6] */
110     TRIG0_IN_TR_GROUP10_OUTPUT7     = 0x00000008u, /* tr_group[10].output[7] */
111     TRIG0_IN_TR_GROUP11_OUTPUT0     = 0x00000009u, /* tr_group[11].output[0] */
112     TRIG0_IN_TR_GROUP11_OUTPUT1     = 0x0000000Au, /* tr_group[11].output[1] */
113     TRIG0_IN_TR_GROUP11_OUTPUT2     = 0x0000000Bu, /* tr_group[11].output[2] */
114     TRIG0_IN_TR_GROUP11_OUTPUT3     = 0x0000000Cu, /* tr_group[11].output[3] */
115     TRIG0_IN_TR_GROUP11_OUTPUT4     = 0x0000000Du, /* tr_group[11].output[4] */
116     TRIG0_IN_TR_GROUP11_OUTPUT5     = 0x0000000Eu, /* tr_group[11].output[5] */
117     TRIG0_IN_TR_GROUP11_OUTPUT6     = 0x0000000Fu, /* tr_group[11].output[6] */
118     TRIG0_IN_TR_GROUP11_OUTPUT7     = 0x00000010u, /* tr_group[11].output[7] */
119     TRIG0_IN_TR_GROUP11_OUTPUT8     = 0x00000011u, /* tr_group[11].output[8] */
120     TRIG0_IN_TR_GROUP11_OUTPUT9     = 0x00000012u, /* tr_group[11].output[9] */
121     TRIG0_IN_TR_GROUP11_OUTPUT10    = 0x00000013u, /* tr_group[11].output[10] */
122     TRIG0_IN_TR_GROUP11_OUTPUT11    = 0x00000014u, /* tr_group[11].output[11] */
123     TRIG0_IN_TR_GROUP11_OUTPUT12    = 0x00000015u, /* tr_group[11].output[12] */
124     TRIG0_IN_TR_GROUP11_OUTPUT13    = 0x00000016u, /* tr_group[11].output[13] */
125     TRIG0_IN_TR_GROUP11_OUTPUT14    = 0x00000017u, /* tr_group[11].output[14] */
126     TRIG0_IN_TR_GROUP11_OUTPUT15    = 0x00000018u, /* tr_group[11].output[15] */
127     TRIG0_IN_TR_GROUP12_OUTPUT8     = 0x00000019u, /* tr_group[12].output[8] */
128     TRIG0_IN_TR_GROUP12_OUTPUT9     = 0x0000001Au, /* tr_group[12].output[9] */
129     TRIG0_IN_TR_GROUP13_OUTPUT0     = 0x0000001Bu, /* tr_group[13].output[0] */
130     TRIG0_IN_TR_GROUP13_OUTPUT1     = 0x0000001Cu, /* tr_group[13].output[1] */
131     TRIG0_IN_TR_GROUP13_OUTPUT2     = 0x0000001Du, /* tr_group[13].output[2] */
132     TRIG0_IN_TR_GROUP13_OUTPUT3     = 0x0000001Eu, /* tr_group[13].output[3] */
133     TRIG0_IN_TR_GROUP13_OUTPUT4     = 0x0000001Fu, /* tr_group[13].output[4] */
134     TRIG0_IN_TR_GROUP13_OUTPUT5     = 0x00000020u, /* tr_group[13].output[5] */
135     TRIG0_IN_TR_GROUP13_OUTPUT6     = 0x00000021u, /* tr_group[13].output[6] */
136     TRIG0_IN_TR_GROUP13_OUTPUT7     = 0x00000022u, /* tr_group[13].output[7] */
137     TRIG0_IN_TR_GROUP13_OUTPUT8     = 0x00000023u, /* tr_group[13].output[8] */
138     TRIG0_IN_TR_GROUP13_OUTPUT9     = 0x00000024u, /* tr_group[13].output[9] */
139     TRIG0_IN_TR_GROUP13_OUTPUT10    = 0x00000025u, /* tr_group[13].output[10] */
140     TRIG0_IN_TR_GROUP13_OUTPUT11    = 0x00000026u, /* tr_group[13].output[11] */
141     TRIG0_IN_TR_GROUP13_OUTPUT12    = 0x00000027u, /* tr_group[13].output[12] */
142     TRIG0_IN_TR_GROUP13_OUTPUT13    = 0x00000028u, /* tr_group[13].output[13] */
143     TRIG0_IN_TR_GROUP13_OUTPUT14    = 0x00000029u, /* tr_group[13].output[14] */
144     TRIG0_IN_TR_GROUP13_OUTPUT15    = 0x0000002Au, /* tr_group[13].output[15] */
145     TRIG0_IN_TR_GROUP14_OUTPUT0     = 0x0000002Bu, /* tr_group[14].output[0] */
146     TRIG0_IN_TR_GROUP14_OUTPUT1     = 0x0000002Cu, /* tr_group[14].output[1] */
147     TRIG0_IN_TR_GROUP14_OUTPUT2     = 0x0000002Du, /* tr_group[14].output[2] */
148     TRIG0_IN_TR_GROUP14_OUTPUT3     = 0x0000002Eu, /* tr_group[14].output[3] */
149     TRIG0_IN_TR_GROUP14_OUTPUT4     = 0x0000002Fu, /* tr_group[14].output[4] */
150     TRIG0_IN_TR_GROUP14_OUTPUT5     = 0x00000030u, /* tr_group[14].output[5] */
151     TRIG0_IN_TR_GROUP14_OUTPUT6     = 0x00000031u, /* tr_group[14].output[6] */
152     TRIG0_IN_TR_GROUP14_OUTPUT7     = 0x00000032u /* tr_group[14].output[7] */
153 } en_trig_input_grp0_t;
154 
155 /* Trigger Input Group 1 - DMA Request Assignments */
156 typedef enum
157 {
158     TRIG1_IN_CPUSS_ZERO             = 0x00000100u, /* cpuss.zero */
159     TRIG1_IN_TR_GROUP10_OUTPUT0     = 0x00000101u, /* tr_group[10].output[0] */
160     TRIG1_IN_TR_GROUP10_OUTPUT1     = 0x00000102u, /* tr_group[10].output[1] */
161     TRIG1_IN_TR_GROUP10_OUTPUT2     = 0x00000103u, /* tr_group[10].output[2] */
162     TRIG1_IN_TR_GROUP10_OUTPUT3     = 0x00000104u, /* tr_group[10].output[3] */
163     TRIG1_IN_TR_GROUP10_OUTPUT4     = 0x00000105u, /* tr_group[10].output[4] */
164     TRIG1_IN_TR_GROUP10_OUTPUT5     = 0x00000106u, /* tr_group[10].output[5] */
165     TRIG1_IN_TR_GROUP10_OUTPUT6     = 0x00000107u, /* tr_group[10].output[6] */
166     TRIG1_IN_TR_GROUP10_OUTPUT7     = 0x00000108u, /* tr_group[10].output[7] */
167     TRIG1_IN_TR_GROUP11_OUTPUT0     = 0x00000109u, /* tr_group[11].output[0] */
168     TRIG1_IN_TR_GROUP11_OUTPUT1     = 0x0000010Au, /* tr_group[11].output[1] */
169     TRIG1_IN_TR_GROUP11_OUTPUT2     = 0x0000010Bu, /* tr_group[11].output[2] */
170     TRIG1_IN_TR_GROUP11_OUTPUT3     = 0x0000010Cu, /* tr_group[11].output[3] */
171     TRIG1_IN_TR_GROUP11_OUTPUT4     = 0x0000010Du, /* tr_group[11].output[4] */
172     TRIG1_IN_TR_GROUP11_OUTPUT5     = 0x0000010Eu, /* tr_group[11].output[5] */
173     TRIG1_IN_TR_GROUP11_OUTPUT6     = 0x0000010Fu, /* tr_group[11].output[6] */
174     TRIG1_IN_TR_GROUP11_OUTPUT7     = 0x00000110u, /* tr_group[11].output[7] */
175     TRIG1_IN_TR_GROUP11_OUTPUT8     = 0x00000111u, /* tr_group[11].output[8] */
176     TRIG1_IN_TR_GROUP11_OUTPUT9     = 0x00000112u, /* tr_group[11].output[9] */
177     TRIG1_IN_TR_GROUP11_OUTPUT10    = 0x00000113u, /* tr_group[11].output[10] */
178     TRIG1_IN_TR_GROUP11_OUTPUT11    = 0x00000114u, /* tr_group[11].output[11] */
179     TRIG1_IN_TR_GROUP11_OUTPUT12    = 0x00000115u, /* tr_group[11].output[12] */
180     TRIG1_IN_TR_GROUP11_OUTPUT13    = 0x00000116u, /* tr_group[11].output[13] */
181     TRIG1_IN_TR_GROUP11_OUTPUT14    = 0x00000117u, /* tr_group[11].output[14] */
182     TRIG1_IN_TR_GROUP11_OUTPUT15    = 0x00000118u, /* tr_group[11].output[15] */
183     TRIG1_IN_TR_GROUP12_OUTPUT8     = 0x00000119u, /* tr_group[12].output[8] */
184     TRIG1_IN_TR_GROUP12_OUTPUT9     = 0x0000011Au, /* tr_group[12].output[9] */
185     TRIG1_IN_TR_GROUP13_OUTPUT0     = 0x0000011Bu, /* tr_group[13].output[0] */
186     TRIG1_IN_TR_GROUP13_OUTPUT1     = 0x0000011Cu, /* tr_group[13].output[1] */
187     TRIG1_IN_TR_GROUP13_OUTPUT2     = 0x0000011Du, /* tr_group[13].output[2] */
188     TRIG1_IN_TR_GROUP13_OUTPUT3     = 0x0000011Eu, /* tr_group[13].output[3] */
189     TRIG1_IN_TR_GROUP13_OUTPUT4     = 0x0000011Fu, /* tr_group[13].output[4] */
190     TRIG1_IN_TR_GROUP13_OUTPUT5     = 0x00000120u, /* tr_group[13].output[5] */
191     TRIG1_IN_TR_GROUP13_OUTPUT6     = 0x00000121u, /* tr_group[13].output[6] */
192     TRIG1_IN_TR_GROUP13_OUTPUT7     = 0x00000122u, /* tr_group[13].output[7] */
193     TRIG1_IN_TR_GROUP13_OUTPUT8     = 0x00000123u, /* tr_group[13].output[8] */
194     TRIG1_IN_TR_GROUP13_OUTPUT9     = 0x00000124u, /* tr_group[13].output[9] */
195     TRIG1_IN_TR_GROUP13_OUTPUT10    = 0x00000125u, /* tr_group[13].output[10] */
196     TRIG1_IN_TR_GROUP13_OUTPUT11    = 0x00000126u, /* tr_group[13].output[11] */
197     TRIG1_IN_TR_GROUP13_OUTPUT12    = 0x00000127u, /* tr_group[13].output[12] */
198     TRIG1_IN_TR_GROUP13_OUTPUT13    = 0x00000128u, /* tr_group[13].output[13] */
199     TRIG1_IN_TR_GROUP13_OUTPUT14    = 0x00000129u, /* tr_group[13].output[14] */
200     TRIG1_IN_TR_GROUP13_OUTPUT15    = 0x0000012Au, /* tr_group[13].output[15] */
201     TRIG1_IN_TR_GROUP14_OUTPUT0     = 0x0000012Bu, /* tr_group[14].output[0] */
202     TRIG1_IN_TR_GROUP14_OUTPUT1     = 0x0000012Cu, /* tr_group[14].output[1] */
203     TRIG1_IN_TR_GROUP14_OUTPUT2     = 0x0000012Du, /* tr_group[14].output[2] */
204     TRIG1_IN_TR_GROUP14_OUTPUT3     = 0x0000012Eu, /* tr_group[14].output[3] */
205     TRIG1_IN_TR_GROUP14_OUTPUT4     = 0x0000012Fu, /* tr_group[14].output[4] */
206     TRIG1_IN_TR_GROUP14_OUTPUT5     = 0x00000130u, /* tr_group[14].output[5] */
207     TRIG1_IN_TR_GROUP14_OUTPUT6     = 0x00000131u, /* tr_group[14].output[6] */
208     TRIG1_IN_TR_GROUP14_OUTPUT7     = 0x00000132u /* tr_group[14].output[7] */
209 } en_trig_input_grp1_t;
210 
211 /* Trigger Input Group 2 - TCPWM trigger inputs */
212 typedef enum
213 {
214     TRIG2_IN_CPUSS_ZERO             = 0x00000200u, /* cpuss.zero */
215     TRIG2_IN_TR_GROUP10_OUTPUT0     = 0x00000201u, /* tr_group[10].output[0] */
216     TRIG2_IN_TR_GROUP10_OUTPUT1     = 0x00000202u, /* tr_group[10].output[1] */
217     TRIG2_IN_TR_GROUP10_OUTPUT2     = 0x00000203u, /* tr_group[10].output[2] */
218     TRIG2_IN_TR_GROUP10_OUTPUT3     = 0x00000204u, /* tr_group[10].output[3] */
219     TRIG2_IN_TR_GROUP10_OUTPUT4     = 0x00000205u, /* tr_group[10].output[4] */
220     TRIG2_IN_TR_GROUP10_OUTPUT5     = 0x00000206u, /* tr_group[10].output[5] */
221     TRIG2_IN_TR_GROUP10_OUTPUT6     = 0x00000207u, /* tr_group[10].output[6] */
222     TRIG2_IN_TR_GROUP10_OUTPUT7     = 0x00000208u, /* tr_group[10].output[7] */
223     TRIG2_IN_TR_GROUP11_OUTPUT0     = 0x00000209u, /* tr_group[11].output[0] */
224     TRIG2_IN_TR_GROUP11_OUTPUT1     = 0x0000020Au, /* tr_group[11].output[1] */
225     TRIG2_IN_TR_GROUP11_OUTPUT2     = 0x0000020Bu, /* tr_group[11].output[2] */
226     TRIG2_IN_TR_GROUP11_OUTPUT3     = 0x0000020Cu, /* tr_group[11].output[3] */
227     TRIG2_IN_TR_GROUP11_OUTPUT4     = 0x0000020Du, /* tr_group[11].output[4] */
228     TRIG2_IN_TR_GROUP11_OUTPUT5     = 0x0000020Eu, /* tr_group[11].output[5] */
229     TRIG2_IN_TR_GROUP11_OUTPUT6     = 0x0000020Fu, /* tr_group[11].output[6] */
230     TRIG2_IN_TR_GROUP11_OUTPUT7     = 0x00000210u, /* tr_group[11].output[7] */
231     TRIG2_IN_TR_GROUP11_OUTPUT8     = 0x00000211u, /* tr_group[11].output[8] */
232     TRIG2_IN_TR_GROUP11_OUTPUT9     = 0x00000212u, /* tr_group[11].output[9] */
233     TRIG2_IN_TR_GROUP11_OUTPUT10    = 0x00000213u, /* tr_group[11].output[10] */
234     TRIG2_IN_TR_GROUP11_OUTPUT11    = 0x00000214u, /* tr_group[11].output[11] */
235     TRIG2_IN_TR_GROUP11_OUTPUT12    = 0x00000215u, /* tr_group[11].output[12] */
236     TRIG2_IN_TR_GROUP11_OUTPUT13    = 0x00000216u, /* tr_group[11].output[13] */
237     TRIG2_IN_TR_GROUP11_OUTPUT14    = 0x00000217u, /* tr_group[11].output[14] */
238     TRIG2_IN_TR_GROUP11_OUTPUT15    = 0x00000218u, /* tr_group[11].output[15] */
239     TRIG2_IN_TR_GROUP12_OUTPUT0     = 0x00000219u, /* tr_group[12].output[0] */
240     TRIG2_IN_TR_GROUP12_OUTPUT1     = 0x0000021Au, /* tr_group[12].output[1] */
241     TRIG2_IN_TR_GROUP12_OUTPUT2     = 0x0000021Bu, /* tr_group[12].output[2] */
242     TRIG2_IN_TR_GROUP12_OUTPUT3     = 0x0000021Cu, /* tr_group[12].output[3] */
243     TRIG2_IN_TR_GROUP12_OUTPUT4     = 0x0000021Du, /* tr_group[12].output[4] */
244     TRIG2_IN_TR_GROUP12_OUTPUT5     = 0x0000021Eu, /* tr_group[12].output[5] */
245     TRIG2_IN_TR_GROUP12_OUTPUT6     = 0x0000021Fu, /* tr_group[12].output[6] */
246     TRIG2_IN_TR_GROUP12_OUTPUT7     = 0x00000220u, /* tr_group[12].output[7] */
247     TRIG2_IN_TR_GROUP13_OUTPUT16    = 0x00000221u, /* tr_group[13].output[16] */
248     TRIG2_IN_TR_GROUP13_OUTPUT17    = 0x00000222u, /* tr_group[13].output[17] */
249     TRIG2_IN_TR_GROUP14_OUTPUT8     = 0x00000223u, /* tr_group[14].output[8] */
250     TRIG2_IN_TR_GROUP14_OUTPUT9     = 0x00000224u, /* tr_group[14].output[9] */
251     TRIG2_IN_TR_GROUP14_OUTPUT10    = 0x00000225u, /* tr_group[14].output[10] */
252     TRIG2_IN_TR_GROUP14_OUTPUT11    = 0x00000226u, /* tr_group[14].output[11] */
253     TRIG2_IN_TR_GROUP14_OUTPUT12    = 0x00000227u, /* tr_group[14].output[12] */
254     TRIG2_IN_TR_GROUP14_OUTPUT13    = 0x00000228u, /* tr_group[14].output[13] */
255     TRIG2_IN_TR_GROUP14_OUTPUT14    = 0x00000229u, /* tr_group[14].output[14] */
256     TRIG2_IN_TR_GROUP14_OUTPUT15    = 0x0000022Au /* tr_group[14].output[15] */
257 } en_trig_input_grp2_t;
258 
259 /* Trigger Input Group 3 - TCPWM trigger inputs */
260 typedef enum
261 {
262     TRIG3_IN_CPUSS_ZERO             = 0x00000300u, /* cpuss.zero */
263     TRIG3_IN_TR_GROUP10_OUTPUT0     = 0x00000301u, /* tr_group[10].output[0] */
264     TRIG3_IN_TR_GROUP10_OUTPUT1     = 0x00000302u, /* tr_group[10].output[1] */
265     TRIG3_IN_TR_GROUP10_OUTPUT2     = 0x00000303u, /* tr_group[10].output[2] */
266     TRIG3_IN_TR_GROUP10_OUTPUT3     = 0x00000304u, /* tr_group[10].output[3] */
267     TRIG3_IN_TR_GROUP10_OUTPUT4     = 0x00000305u, /* tr_group[10].output[4] */
268     TRIG3_IN_TR_GROUP10_OUTPUT5     = 0x00000306u, /* tr_group[10].output[5] */
269     TRIG3_IN_TR_GROUP10_OUTPUT6     = 0x00000307u, /* tr_group[10].output[6] */
270     TRIG3_IN_TR_GROUP10_OUTPUT7     = 0x00000308u, /* tr_group[10].output[7] */
271     TRIG3_IN_TR_GROUP11_OUTPUT0     = 0x00000309u, /* tr_group[11].output[0] */
272     TRIG3_IN_TR_GROUP11_OUTPUT1     = 0x0000030Au, /* tr_group[11].output[1] */
273     TRIG3_IN_TR_GROUP11_OUTPUT2     = 0x0000030Bu, /* tr_group[11].output[2] */
274     TRIG3_IN_TR_GROUP11_OUTPUT3     = 0x0000030Cu, /* tr_group[11].output[3] */
275     TRIG3_IN_TR_GROUP11_OUTPUT4     = 0x0000030Du, /* tr_group[11].output[4] */
276     TRIG3_IN_TR_GROUP11_OUTPUT5     = 0x0000030Eu, /* tr_group[11].output[5] */
277     TRIG3_IN_TR_GROUP11_OUTPUT6     = 0x0000030Fu, /* tr_group[11].output[6] */
278     TRIG3_IN_TR_GROUP11_OUTPUT7     = 0x00000310u, /* tr_group[11].output[7] */
279     TRIG3_IN_TR_GROUP11_OUTPUT8     = 0x00000311u, /* tr_group[11].output[8] */
280     TRIG3_IN_TR_GROUP11_OUTPUT9     = 0x00000312u, /* tr_group[11].output[9] */
281     TRIG3_IN_TR_GROUP11_OUTPUT10    = 0x00000313u, /* tr_group[11].output[10] */
282     TRIG3_IN_TR_GROUP11_OUTPUT11    = 0x00000314u, /* tr_group[11].output[11] */
283     TRIG3_IN_TR_GROUP11_OUTPUT12    = 0x00000315u, /* tr_group[11].output[12] */
284     TRIG3_IN_TR_GROUP11_OUTPUT13    = 0x00000316u, /* tr_group[11].output[13] */
285     TRIG3_IN_TR_GROUP11_OUTPUT14    = 0x00000317u, /* tr_group[11].output[14] */
286     TRIG3_IN_TR_GROUP11_OUTPUT15    = 0x00000318u, /* tr_group[11].output[15] */
287     TRIG3_IN_TR_GROUP12_OUTPUT0     = 0x00000319u, /* tr_group[12].output[0] */
288     TRIG3_IN_TR_GROUP12_OUTPUT1     = 0x0000031Au, /* tr_group[12].output[1] */
289     TRIG3_IN_TR_GROUP12_OUTPUT2     = 0x0000031Bu, /* tr_group[12].output[2] */
290     TRIG3_IN_TR_GROUP12_OUTPUT3     = 0x0000031Cu, /* tr_group[12].output[3] */
291     TRIG3_IN_TR_GROUP12_OUTPUT4     = 0x0000031Du, /* tr_group[12].output[4] */
292     TRIG3_IN_TR_GROUP12_OUTPUT5     = 0x0000031Eu, /* tr_group[12].output[5] */
293     TRIG3_IN_TR_GROUP12_OUTPUT6     = 0x0000031Fu, /* tr_group[12].output[6] */
294     TRIG3_IN_TR_GROUP12_OUTPUT7     = 0x00000320u, /* tr_group[12].output[7] */
295     TRIG3_IN_TR_GROUP13_OUTPUT16    = 0x00000321u, /* tr_group[13].output[16] */
296     TRIG3_IN_TR_GROUP13_OUTPUT17    = 0x00000322u, /* tr_group[13].output[17] */
297     TRIG3_IN_TR_GROUP14_OUTPUT8     = 0x00000323u, /* tr_group[14].output[8] */
298     TRIG3_IN_TR_GROUP14_OUTPUT9     = 0x00000324u, /* tr_group[14].output[9] */
299     TRIG3_IN_TR_GROUP14_OUTPUT10    = 0x00000325u, /* tr_group[14].output[10] */
300     TRIG3_IN_TR_GROUP14_OUTPUT11    = 0x00000326u, /* tr_group[14].output[11] */
301     TRIG3_IN_TR_GROUP14_OUTPUT12    = 0x00000327u, /* tr_group[14].output[12] */
302     TRIG3_IN_TR_GROUP14_OUTPUT13    = 0x00000328u, /* tr_group[14].output[13] */
303     TRIG3_IN_TR_GROUP14_OUTPUT14    = 0x00000329u, /* tr_group[14].output[14] */
304     TRIG3_IN_TR_GROUP14_OUTPUT15    = 0x0000032Au /* tr_group[14].output[15] */
305 } en_trig_input_grp3_t;
306 
307 /* Trigger Input Group 4 - PROFILE trigger multiplexer */
308 typedef enum
309 {
310     TRIG4_IN_CPUSS_ZERO             = 0x00000400u, /* cpuss.zero */
311     TRIG4_IN_TR_GROUP10_OUTPUT0     = 0x00000401u, /* tr_group[10].output[0] */
312     TRIG4_IN_TR_GROUP10_OUTPUT1     = 0x00000402u, /* tr_group[10].output[1] */
313     TRIG4_IN_TR_GROUP10_OUTPUT2     = 0x00000403u, /* tr_group[10].output[2] */
314     TRIG4_IN_TR_GROUP10_OUTPUT3     = 0x00000404u, /* tr_group[10].output[3] */
315     TRIG4_IN_TR_GROUP10_OUTPUT4     = 0x00000405u, /* tr_group[10].output[4] */
316     TRIG4_IN_TR_GROUP10_OUTPUT5     = 0x00000406u, /* tr_group[10].output[5] */
317     TRIG4_IN_TR_GROUP10_OUTPUT6     = 0x00000407u, /* tr_group[10].output[6] */
318     TRIG4_IN_TR_GROUP10_OUTPUT7     = 0x00000408u, /* tr_group[10].output[7] */
319     TRIG4_IN_TR_GROUP11_OUTPUT0     = 0x00000409u, /* tr_group[11].output[0] */
320     TRIG4_IN_TR_GROUP11_OUTPUT1     = 0x0000040Au, /* tr_group[11].output[1] */
321     TRIG4_IN_TR_GROUP11_OUTPUT2     = 0x0000040Bu, /* tr_group[11].output[2] */
322     TRIG4_IN_TR_GROUP11_OUTPUT3     = 0x0000040Cu, /* tr_group[11].output[3] */
323     TRIG4_IN_TR_GROUP11_OUTPUT4     = 0x0000040Du, /* tr_group[11].output[4] */
324     TRIG4_IN_TR_GROUP11_OUTPUT5     = 0x0000040Eu, /* tr_group[11].output[5] */
325     TRIG4_IN_TR_GROUP11_OUTPUT6     = 0x0000040Fu, /* tr_group[11].output[6] */
326     TRIG4_IN_TR_GROUP11_OUTPUT7     = 0x00000410u, /* tr_group[11].output[7] */
327     TRIG4_IN_TR_GROUP11_OUTPUT8     = 0x00000411u, /* tr_group[11].output[8] */
328     TRIG4_IN_TR_GROUP11_OUTPUT9     = 0x00000412u, /* tr_group[11].output[9] */
329     TRIG4_IN_TR_GROUP11_OUTPUT10    = 0x00000413u, /* tr_group[11].output[10] */
330     TRIG4_IN_TR_GROUP11_OUTPUT11    = 0x00000414u, /* tr_group[11].output[11] */
331     TRIG4_IN_TR_GROUP11_OUTPUT12    = 0x00000415u, /* tr_group[11].output[12] */
332     TRIG4_IN_TR_GROUP11_OUTPUT13    = 0x00000416u, /* tr_group[11].output[13] */
333     TRIG4_IN_TR_GROUP11_OUTPUT14    = 0x00000417u, /* tr_group[11].output[14] */
334     TRIG4_IN_TR_GROUP11_OUTPUT15    = 0x00000418u, /* tr_group[11].output[15] */
335     TRIG4_IN_TR_GROUP12_OUTPUT0     = 0x00000419u, /* tr_group[12].output[0] */
336     TRIG4_IN_TR_GROUP12_OUTPUT1     = 0x0000041Au, /* tr_group[12].output[1] */
337     TRIG4_IN_TR_GROUP12_OUTPUT2     = 0x0000041Bu, /* tr_group[12].output[2] */
338     TRIG4_IN_TR_GROUP12_OUTPUT3     = 0x0000041Cu, /* tr_group[12].output[3] */
339     TRIG4_IN_TR_GROUP12_OUTPUT4     = 0x0000041Du, /* tr_group[12].output[4] */
340     TRIG4_IN_TR_GROUP12_OUTPUT5     = 0x0000041Eu, /* tr_group[12].output[5] */
341     TRIG4_IN_TR_GROUP12_OUTPUT6     = 0x0000041Fu, /* tr_group[12].output[6] */
342     TRIG4_IN_TR_GROUP12_OUTPUT7     = 0x00000420u, /* tr_group[12].output[7] */
343     TRIG4_IN_TR_GROUP13_OUTPUT16    = 0x00000421u, /* tr_group[13].output[16] */
344     TRIG4_IN_TR_GROUP13_OUTPUT17    = 0x00000422u, /* tr_group[13].output[17] */
345     TRIG4_IN_TR_GROUP14_OUTPUT8     = 0x00000423u, /* tr_group[14].output[8] */
346     TRIG4_IN_TR_GROUP14_OUTPUT9     = 0x00000424u, /* tr_group[14].output[9] */
347     TRIG4_IN_TR_GROUP14_OUTPUT10    = 0x00000425u, /* tr_group[14].output[10] */
348     TRIG4_IN_TR_GROUP14_OUTPUT11    = 0x00000426u, /* tr_group[14].output[11] */
349     TRIG4_IN_TR_GROUP14_OUTPUT12    = 0x00000427u, /* tr_group[14].output[12] */
350     TRIG4_IN_TR_GROUP14_OUTPUT13    = 0x00000428u, /* tr_group[14].output[13] */
351     TRIG4_IN_TR_GROUP14_OUTPUT14    = 0x00000429u, /* tr_group[14].output[14] */
352     TRIG4_IN_TR_GROUP14_OUTPUT15    = 0x0000042Au /* tr_group[14].output[15] */
353 } en_trig_input_grp4_t;
354 
355 /* Trigger Input Group 5 - CPUSS.CTI trigger multiplexer */
356 typedef enum
357 {
358     TRIG5_IN_CPUSS_ZERO             = 0x00000500u, /* cpuss.zero */
359     TRIG5_IN_TR_GROUP10_OUTPUT0     = 0x00000501u, /* tr_group[10].output[0] */
360     TRIG5_IN_TR_GROUP10_OUTPUT1     = 0x00000502u, /* tr_group[10].output[1] */
361     TRIG5_IN_TR_GROUP10_OUTPUT2     = 0x00000503u, /* tr_group[10].output[2] */
362     TRIG5_IN_TR_GROUP10_OUTPUT3     = 0x00000504u, /* tr_group[10].output[3] */
363     TRIG5_IN_TR_GROUP10_OUTPUT4     = 0x00000505u, /* tr_group[10].output[4] */
364     TRIG5_IN_TR_GROUP10_OUTPUT5     = 0x00000506u, /* tr_group[10].output[5] */
365     TRIG5_IN_TR_GROUP10_OUTPUT6     = 0x00000507u, /* tr_group[10].output[6] */
366     TRIG5_IN_TR_GROUP10_OUTPUT7     = 0x00000508u, /* tr_group[10].output[7] */
367     TRIG5_IN_TR_GROUP11_OUTPUT0     = 0x00000509u, /* tr_group[11].output[0] */
368     TRIG5_IN_TR_GROUP11_OUTPUT1     = 0x0000050Au, /* tr_group[11].output[1] */
369     TRIG5_IN_TR_GROUP11_OUTPUT2     = 0x0000050Bu, /* tr_group[11].output[2] */
370     TRIG5_IN_TR_GROUP11_OUTPUT3     = 0x0000050Cu, /* tr_group[11].output[3] */
371     TRIG5_IN_TR_GROUP11_OUTPUT4     = 0x0000050Du, /* tr_group[11].output[4] */
372     TRIG5_IN_TR_GROUP11_OUTPUT5     = 0x0000050Eu, /* tr_group[11].output[5] */
373     TRIG5_IN_TR_GROUP11_OUTPUT6     = 0x0000050Fu, /* tr_group[11].output[6] */
374     TRIG5_IN_TR_GROUP11_OUTPUT7     = 0x00000510u, /* tr_group[11].output[7] */
375     TRIG5_IN_TR_GROUP11_OUTPUT8     = 0x00000511u, /* tr_group[11].output[8] */
376     TRIG5_IN_TR_GROUP11_OUTPUT9     = 0x00000512u, /* tr_group[11].output[9] */
377     TRIG5_IN_TR_GROUP11_OUTPUT10    = 0x00000513u, /* tr_group[11].output[10] */
378     TRIG5_IN_TR_GROUP11_OUTPUT11    = 0x00000514u, /* tr_group[11].output[11] */
379     TRIG5_IN_TR_GROUP11_OUTPUT12    = 0x00000515u, /* tr_group[11].output[12] */
380     TRIG5_IN_TR_GROUP11_OUTPUT13    = 0x00000516u, /* tr_group[11].output[13] */
381     TRIG5_IN_TR_GROUP11_OUTPUT14    = 0x00000517u, /* tr_group[11].output[14] */
382     TRIG5_IN_TR_GROUP11_OUTPUT15    = 0x00000518u, /* tr_group[11].output[15] */
383     TRIG5_IN_TR_GROUP12_OUTPUT0     = 0x00000519u, /* tr_group[12].output[0] */
384     TRIG5_IN_TR_GROUP12_OUTPUT1     = 0x0000051Au, /* tr_group[12].output[1] */
385     TRIG5_IN_TR_GROUP12_OUTPUT2     = 0x0000051Bu, /* tr_group[12].output[2] */
386     TRIG5_IN_TR_GROUP12_OUTPUT3     = 0x0000051Cu, /* tr_group[12].output[3] */
387     TRIG5_IN_TR_GROUP12_OUTPUT4     = 0x0000051Du, /* tr_group[12].output[4] */
388     TRIG5_IN_TR_GROUP12_OUTPUT5     = 0x0000051Eu, /* tr_group[12].output[5] */
389     TRIG5_IN_TR_GROUP12_OUTPUT6     = 0x0000051Fu, /* tr_group[12].output[6] */
390     TRIG5_IN_TR_GROUP12_OUTPUT7     = 0x00000520u, /* tr_group[12].output[7] */
391     TRIG5_IN_TR_GROUP13_OUTPUT16    = 0x00000521u, /* tr_group[13].output[16] */
392     TRIG5_IN_TR_GROUP13_OUTPUT17    = 0x00000522u, /* tr_group[13].output[17] */
393     TRIG5_IN_TR_GROUP14_OUTPUT8     = 0x00000523u, /* tr_group[14].output[8] */
394     TRIG5_IN_TR_GROUP14_OUTPUT9     = 0x00000524u, /* tr_group[14].output[9] */
395     TRIG5_IN_TR_GROUP14_OUTPUT10    = 0x00000525u, /* tr_group[14].output[10] */
396     TRIG5_IN_TR_GROUP14_OUTPUT11    = 0x00000526u, /* tr_group[14].output[11] */
397     TRIG5_IN_TR_GROUP14_OUTPUT12    = 0x00000527u, /* tr_group[14].output[12] */
398     TRIG5_IN_TR_GROUP14_OUTPUT13    = 0x00000528u, /* tr_group[14].output[13] */
399     TRIG5_IN_TR_GROUP14_OUTPUT14    = 0x00000529u, /* tr_group[14].output[14] */
400     TRIG5_IN_TR_GROUP14_OUTPUT15    = 0x0000052Au /* tr_group[14].output[15] */
401 } en_trig_input_grp5_t;
402 
403 /* Trigger Input Group 6 - PASS trigger multiplexer */
404 typedef enum
405 {
406     TRIG6_IN_CPUSS_ZERO             = 0x00000600u, /* cpuss.zero */
407     TRIG6_IN_TR_GROUP10_OUTPUT0     = 0x00000601u, /* tr_group[10].output[0] */
408     TRIG6_IN_TR_GROUP10_OUTPUT1     = 0x00000602u, /* tr_group[10].output[1] */
409     TRIG6_IN_TR_GROUP10_OUTPUT2     = 0x00000603u, /* tr_group[10].output[2] */
410     TRIG6_IN_TR_GROUP10_OUTPUT3     = 0x00000604u, /* tr_group[10].output[3] */
411     TRIG6_IN_TR_GROUP10_OUTPUT4     = 0x00000605u, /* tr_group[10].output[4] */
412     TRIG6_IN_TR_GROUP10_OUTPUT5     = 0x00000606u, /* tr_group[10].output[5] */
413     TRIG6_IN_TR_GROUP10_OUTPUT6     = 0x00000607u, /* tr_group[10].output[6] */
414     TRIG6_IN_TR_GROUP10_OUTPUT7     = 0x00000608u, /* tr_group[10].output[7] */
415     TRIG6_IN_TR_GROUP11_OUTPUT0     = 0x00000609u, /* tr_group[11].output[0] */
416     TRIG6_IN_TR_GROUP11_OUTPUT1     = 0x0000060Au, /* tr_group[11].output[1] */
417     TRIG6_IN_TR_GROUP11_OUTPUT2     = 0x0000060Bu, /* tr_group[11].output[2] */
418     TRIG6_IN_TR_GROUP11_OUTPUT3     = 0x0000060Cu, /* tr_group[11].output[3] */
419     TRIG6_IN_TR_GROUP11_OUTPUT4     = 0x0000060Du, /* tr_group[11].output[4] */
420     TRIG6_IN_TR_GROUP11_OUTPUT5     = 0x0000060Eu, /* tr_group[11].output[5] */
421     TRIG6_IN_TR_GROUP11_OUTPUT6     = 0x0000060Fu, /* tr_group[11].output[6] */
422     TRIG6_IN_TR_GROUP11_OUTPUT7     = 0x00000610u, /* tr_group[11].output[7] */
423     TRIG6_IN_TR_GROUP11_OUTPUT8     = 0x00000611u, /* tr_group[11].output[8] */
424     TRIG6_IN_TR_GROUP11_OUTPUT9     = 0x00000612u, /* tr_group[11].output[9] */
425     TRIG6_IN_TR_GROUP11_OUTPUT10    = 0x00000613u, /* tr_group[11].output[10] */
426     TRIG6_IN_TR_GROUP11_OUTPUT11    = 0x00000614u, /* tr_group[11].output[11] */
427     TRIG6_IN_TR_GROUP11_OUTPUT12    = 0x00000615u, /* tr_group[11].output[12] */
428     TRIG6_IN_TR_GROUP11_OUTPUT13    = 0x00000616u, /* tr_group[11].output[13] */
429     TRIG6_IN_TR_GROUP11_OUTPUT14    = 0x00000617u, /* tr_group[11].output[14] */
430     TRIG6_IN_TR_GROUP11_OUTPUT15    = 0x00000618u, /* tr_group[11].output[15] */
431     TRIG6_IN_TR_GROUP12_OUTPUT0     = 0x00000619u, /* tr_group[12].output[0] */
432     TRIG6_IN_TR_GROUP12_OUTPUT1     = 0x0000061Au, /* tr_group[12].output[1] */
433     TRIG6_IN_TR_GROUP12_OUTPUT2     = 0x0000061Bu, /* tr_group[12].output[2] */
434     TRIG6_IN_TR_GROUP12_OUTPUT3     = 0x0000061Cu, /* tr_group[12].output[3] */
435     TRIG6_IN_TR_GROUP12_OUTPUT4     = 0x0000061Du, /* tr_group[12].output[4] */
436     TRIG6_IN_TR_GROUP12_OUTPUT5     = 0x0000061Eu, /* tr_group[12].output[5] */
437     TRIG6_IN_TR_GROUP12_OUTPUT6     = 0x0000061Fu, /* tr_group[12].output[6] */
438     TRIG6_IN_TR_GROUP12_OUTPUT7     = 0x00000620u, /* tr_group[12].output[7] */
439     TRIG6_IN_TR_GROUP13_OUTPUT16    = 0x00000621u, /* tr_group[13].output[16] */
440     TRIG6_IN_TR_GROUP13_OUTPUT17    = 0x00000622u, /* tr_group[13].output[17] */
441     TRIG6_IN_TR_GROUP14_OUTPUT8     = 0x00000623u, /* tr_group[14].output[8] */
442     TRIG6_IN_TR_GROUP14_OUTPUT9     = 0x00000624u, /* tr_group[14].output[9] */
443     TRIG6_IN_TR_GROUP14_OUTPUT10    = 0x00000625u, /* tr_group[14].output[10] */
444     TRIG6_IN_TR_GROUP14_OUTPUT11    = 0x00000626u, /* tr_group[14].output[11] */
445     TRIG6_IN_TR_GROUP14_OUTPUT12    = 0x00000627u, /* tr_group[14].output[12] */
446     TRIG6_IN_TR_GROUP14_OUTPUT13    = 0x00000628u, /* tr_group[14].output[13] */
447     TRIG6_IN_TR_GROUP14_OUTPUT14    = 0x00000629u, /* tr_group[14].output[14] */
448     TRIG6_IN_TR_GROUP14_OUTPUT15    = 0x0000062Au /* tr_group[14].output[15] */
449 } en_trig_input_grp6_t;
450 
451 /* Trigger Input Group 7 - UDB general purpose trigger multiplexer */
452 typedef enum
453 {
454     TRIG7_IN_CPUSS_ZERO             = 0x00000700u, /* cpuss.zero */
455     TRIG7_IN_TR_GROUP10_OUTPUT0     = 0x00000701u, /* tr_group[10].output[0] */
456     TRIG7_IN_TR_GROUP10_OUTPUT1     = 0x00000702u, /* tr_group[10].output[1] */
457     TRIG7_IN_TR_GROUP10_OUTPUT2     = 0x00000703u, /* tr_group[10].output[2] */
458     TRIG7_IN_TR_GROUP10_OUTPUT3     = 0x00000704u, /* tr_group[10].output[3] */
459     TRIG7_IN_TR_GROUP10_OUTPUT4     = 0x00000705u, /* tr_group[10].output[4] */
460     TRIG7_IN_TR_GROUP10_OUTPUT5     = 0x00000706u, /* tr_group[10].output[5] */
461     TRIG7_IN_TR_GROUP10_OUTPUT6     = 0x00000707u, /* tr_group[10].output[6] */
462     TRIG7_IN_TR_GROUP10_OUTPUT7     = 0x00000708u, /* tr_group[10].output[7] */
463     TRIG7_IN_TR_GROUP11_OUTPUT0     = 0x00000709u, /* tr_group[11].output[0] */
464     TRIG7_IN_TR_GROUP11_OUTPUT1     = 0x0000070Au, /* tr_group[11].output[1] */
465     TRIG7_IN_TR_GROUP11_OUTPUT2     = 0x0000070Bu, /* tr_group[11].output[2] */
466     TRIG7_IN_TR_GROUP11_OUTPUT3     = 0x0000070Cu, /* tr_group[11].output[3] */
467     TRIG7_IN_TR_GROUP11_OUTPUT4     = 0x0000070Du, /* tr_group[11].output[4] */
468     TRIG7_IN_TR_GROUP11_OUTPUT5     = 0x0000070Eu, /* tr_group[11].output[5] */
469     TRIG7_IN_TR_GROUP11_OUTPUT6     = 0x0000070Fu, /* tr_group[11].output[6] */
470     TRIG7_IN_TR_GROUP11_OUTPUT7     = 0x00000710u, /* tr_group[11].output[7] */
471     TRIG7_IN_TR_GROUP11_OUTPUT8     = 0x00000711u, /* tr_group[11].output[8] */
472     TRIG7_IN_TR_GROUP11_OUTPUT9     = 0x00000712u, /* tr_group[11].output[9] */
473     TRIG7_IN_TR_GROUP11_OUTPUT10    = 0x00000713u, /* tr_group[11].output[10] */
474     TRIG7_IN_TR_GROUP11_OUTPUT11    = 0x00000714u, /* tr_group[11].output[11] */
475     TRIG7_IN_TR_GROUP11_OUTPUT12    = 0x00000715u, /* tr_group[11].output[12] */
476     TRIG7_IN_TR_GROUP11_OUTPUT13    = 0x00000716u, /* tr_group[11].output[13] */
477     TRIG7_IN_TR_GROUP11_OUTPUT14    = 0x00000717u, /* tr_group[11].output[14] */
478     TRIG7_IN_TR_GROUP11_OUTPUT15    = 0x00000718u, /* tr_group[11].output[15] */
479     TRIG7_IN_TR_GROUP12_OUTPUT0     = 0x00000719u, /* tr_group[12].output[0] */
480     TRIG7_IN_TR_GROUP12_OUTPUT1     = 0x0000071Au, /* tr_group[12].output[1] */
481     TRIG7_IN_TR_GROUP12_OUTPUT2     = 0x0000071Bu, /* tr_group[12].output[2] */
482     TRIG7_IN_TR_GROUP12_OUTPUT3     = 0x0000071Cu, /* tr_group[12].output[3] */
483     TRIG7_IN_TR_GROUP12_OUTPUT4     = 0x0000071Du, /* tr_group[12].output[4] */
484     TRIG7_IN_TR_GROUP12_OUTPUT5     = 0x0000071Eu, /* tr_group[12].output[5] */
485     TRIG7_IN_TR_GROUP12_OUTPUT6     = 0x0000071Fu, /* tr_group[12].output[6] */
486     TRIG7_IN_TR_GROUP12_OUTPUT7     = 0x00000720u, /* tr_group[12].output[7] */
487     TRIG7_IN_TR_GROUP13_OUTPUT16    = 0x00000721u, /* tr_group[13].output[16] */
488     TRIG7_IN_TR_GROUP13_OUTPUT17    = 0x00000722u, /* tr_group[13].output[17] */
489     TRIG7_IN_TR_GROUP14_OUTPUT8     = 0x00000723u, /* tr_group[14].output[8] */
490     TRIG7_IN_TR_GROUP14_OUTPUT9     = 0x00000724u, /* tr_group[14].output[9] */
491     TRIG7_IN_TR_GROUP14_OUTPUT10    = 0x00000725u, /* tr_group[14].output[10] */
492     TRIG7_IN_TR_GROUP14_OUTPUT11    = 0x00000726u, /* tr_group[14].output[11] */
493     TRIG7_IN_TR_GROUP14_OUTPUT12    = 0x00000727u, /* tr_group[14].output[12] */
494     TRIG7_IN_TR_GROUP14_OUTPUT13    = 0x00000728u, /* tr_group[14].output[13] */
495     TRIG7_IN_TR_GROUP14_OUTPUT14    = 0x00000729u, /* tr_group[14].output[14] */
496     TRIG7_IN_TR_GROUP14_OUTPUT15    = 0x0000072Au /* tr_group[14].output[15] */
497 } en_trig_input_grp7_t;
498 
499 /* Trigger Input Group 8 - Trigger multiplexer to pins */
500 typedef enum
501 {
502     TRIG8_IN_CPUSS_ZERO             = 0x00000800u, /* cpuss.zero */
503     TRIG8_IN_TR_GROUP10_OUTPUT0     = 0x00000801u, /* tr_group[10].output[0] */
504     TRIG8_IN_TR_GROUP10_OUTPUT1     = 0x00000802u, /* tr_group[10].output[1] */
505     TRIG8_IN_TR_GROUP10_OUTPUT2     = 0x00000803u, /* tr_group[10].output[2] */
506     TRIG8_IN_TR_GROUP10_OUTPUT3     = 0x00000804u, /* tr_group[10].output[3] */
507     TRIG8_IN_TR_GROUP10_OUTPUT4     = 0x00000805u, /* tr_group[10].output[4] */
508     TRIG8_IN_TR_GROUP10_OUTPUT5     = 0x00000806u, /* tr_group[10].output[5] */
509     TRIG8_IN_TR_GROUP10_OUTPUT6     = 0x00000807u, /* tr_group[10].output[6] */
510     TRIG8_IN_TR_GROUP10_OUTPUT7     = 0x00000808u, /* tr_group[10].output[7] */
511     TRIG8_IN_TR_GROUP11_OUTPUT0     = 0x00000809u, /* tr_group[11].output[0] */
512     TRIG8_IN_TR_GROUP11_OUTPUT1     = 0x0000080Au, /* tr_group[11].output[1] */
513     TRIG8_IN_TR_GROUP11_OUTPUT2     = 0x0000080Bu, /* tr_group[11].output[2] */
514     TRIG8_IN_TR_GROUP11_OUTPUT3     = 0x0000080Cu, /* tr_group[11].output[3] */
515     TRIG8_IN_TR_GROUP11_OUTPUT4     = 0x0000080Du, /* tr_group[11].output[4] */
516     TRIG8_IN_TR_GROUP11_OUTPUT5     = 0x0000080Eu, /* tr_group[11].output[5] */
517     TRIG8_IN_TR_GROUP11_OUTPUT6     = 0x0000080Fu, /* tr_group[11].output[6] */
518     TRIG8_IN_TR_GROUP11_OUTPUT7     = 0x00000810u, /* tr_group[11].output[7] */
519     TRIG8_IN_TR_GROUP11_OUTPUT8     = 0x00000811u, /* tr_group[11].output[8] */
520     TRIG8_IN_TR_GROUP11_OUTPUT9     = 0x00000812u, /* tr_group[11].output[9] */
521     TRIG8_IN_TR_GROUP11_OUTPUT10    = 0x00000813u, /* tr_group[11].output[10] */
522     TRIG8_IN_TR_GROUP11_OUTPUT11    = 0x00000814u, /* tr_group[11].output[11] */
523     TRIG8_IN_TR_GROUP11_OUTPUT12    = 0x00000815u, /* tr_group[11].output[12] */
524     TRIG8_IN_TR_GROUP11_OUTPUT13    = 0x00000816u, /* tr_group[11].output[13] */
525     TRIG8_IN_TR_GROUP11_OUTPUT14    = 0x00000817u, /* tr_group[11].output[14] */
526     TRIG8_IN_TR_GROUP11_OUTPUT15    = 0x00000818u, /* tr_group[11].output[15] */
527     TRIG8_IN_TR_GROUP12_OUTPUT0     = 0x00000819u, /* tr_group[12].output[0] */
528     TRIG8_IN_TR_GROUP12_OUTPUT1     = 0x0000081Au, /* tr_group[12].output[1] */
529     TRIG8_IN_TR_GROUP12_OUTPUT2     = 0x0000081Bu, /* tr_group[12].output[2] */
530     TRIG8_IN_TR_GROUP12_OUTPUT3     = 0x0000081Cu, /* tr_group[12].output[3] */
531     TRIG8_IN_TR_GROUP12_OUTPUT4     = 0x0000081Du, /* tr_group[12].output[4] */
532     TRIG8_IN_TR_GROUP12_OUTPUT5     = 0x0000081Eu, /* tr_group[12].output[5] */
533     TRIG8_IN_TR_GROUP12_OUTPUT6     = 0x0000081Fu, /* tr_group[12].output[6] */
534     TRIG8_IN_TR_GROUP12_OUTPUT7     = 0x00000820u, /* tr_group[12].output[7] */
535     TRIG8_IN_TR_GROUP13_OUTPUT16    = 0x00000821u, /* tr_group[13].output[16] */
536     TRIG8_IN_TR_GROUP13_OUTPUT17    = 0x00000822u, /* tr_group[13].output[17] */
537     TRIG8_IN_TR_GROUP14_OUTPUT8     = 0x00000823u, /* tr_group[14].output[8] */
538     TRIG8_IN_TR_GROUP14_OUTPUT9     = 0x00000824u, /* tr_group[14].output[9] */
539     TRIG8_IN_TR_GROUP14_OUTPUT10    = 0x00000825u, /* tr_group[14].output[10] */
540     TRIG8_IN_TR_GROUP14_OUTPUT11    = 0x00000826u, /* tr_group[14].output[11] */
541     TRIG8_IN_TR_GROUP14_OUTPUT12    = 0x00000827u, /* tr_group[14].output[12] */
542     TRIG8_IN_TR_GROUP14_OUTPUT13    = 0x00000828u, /* tr_group[14].output[13] */
543     TRIG8_IN_TR_GROUP14_OUTPUT14    = 0x00000829u, /* tr_group[14].output[14] */
544     TRIG8_IN_TR_GROUP14_OUTPUT15    = 0x0000082Au /* tr_group[14].output[15] */
545 } en_trig_input_grp8_t;
546 
547 /* Trigger Input Group 9 - Feedback mux to USB DMA interface */
548 typedef enum
549 {
550     TRIG9_IN_CPUSS_ZERO             = 0x00000900u, /* cpuss.zero */
551     TRIG9_IN_CPUSS_DW0_TR_OUT0      = 0x00000901u, /* cpuss.dw0_tr_out[0] */
552     TRIG9_IN_CPUSS_DW0_TR_OUT1      = 0x00000902u, /* cpuss.dw0_tr_out[1] */
553     TRIG9_IN_CPUSS_DW0_TR_OUT2      = 0x00000903u, /* cpuss.dw0_tr_out[2] */
554     TRIG9_IN_CPUSS_DW0_TR_OUT3      = 0x00000904u, /* cpuss.dw0_tr_out[3] */
555     TRIG9_IN_CPUSS_DW0_TR_OUT4      = 0x00000905u, /* cpuss.dw0_tr_out[4] */
556     TRIG9_IN_CPUSS_DW0_TR_OUT5      = 0x00000906u, /* cpuss.dw0_tr_out[5] */
557     TRIG9_IN_CPUSS_DW0_TR_OUT6      = 0x00000907u, /* cpuss.dw0_tr_out[6] */
558     TRIG9_IN_CPUSS_DW0_TR_OUT7      = 0x00000908u, /* cpuss.dw0_tr_out[7] */
559     TRIG9_IN_CPUSS_DW0_TR_OUT8      = 0x00000909u, /* cpuss.dw0_tr_out[8] */
560     TRIG9_IN_CPUSS_DW0_TR_OUT9      = 0x0000090Au, /* cpuss.dw0_tr_out[9] */
561     TRIG9_IN_CPUSS_DW0_TR_OUT10     = 0x0000090Bu, /* cpuss.dw0_tr_out[10] */
562     TRIG9_IN_CPUSS_DW0_TR_OUT11     = 0x0000090Cu, /* cpuss.dw0_tr_out[11] */
563     TRIG9_IN_CPUSS_DW0_TR_OUT12     = 0x0000090Du, /* cpuss.dw0_tr_out[12] */
564     TRIG9_IN_CPUSS_DW0_TR_OUT13     = 0x0000090Eu, /* cpuss.dw0_tr_out[13] */
565     TRIG9_IN_CPUSS_DW0_TR_OUT14     = 0x0000090Fu, /* cpuss.dw0_tr_out[14] */
566     TRIG9_IN_CPUSS_DW0_TR_OUT15     = 0x00000910u, /* cpuss.dw0_tr_out[15] */
567     TRIG9_IN_CPUSS_DW1_TR_OUT0      = 0x00000911u, /* cpuss.dw1_tr_out[0] */
568     TRIG9_IN_CPUSS_DW1_TR_OUT1      = 0x00000912u, /* cpuss.dw1_tr_out[1] */
569     TRIG9_IN_CPUSS_DW1_TR_OUT2      = 0x00000913u, /* cpuss.dw1_tr_out[2] */
570     TRIG9_IN_CPUSS_DW1_TR_OUT3      = 0x00000914u, /* cpuss.dw1_tr_out[3] */
571     TRIG9_IN_CPUSS_DW1_TR_OUT4      = 0x00000915u, /* cpuss.dw1_tr_out[4] */
572     TRIG9_IN_CPUSS_DW1_TR_OUT5      = 0x00000916u, /* cpuss.dw1_tr_out[5] */
573     TRIG9_IN_CPUSS_DW1_TR_OUT6      = 0x00000917u, /* cpuss.dw1_tr_out[6] */
574     TRIG9_IN_CPUSS_DW1_TR_OUT7      = 0x00000918u, /* cpuss.dw1_tr_out[7] */
575     TRIG9_IN_CPUSS_DW1_TR_OUT8      = 0x00000919u, /* cpuss.dw1_tr_out[8] */
576     TRIG9_IN_CPUSS_DW1_TR_OUT9      = 0x0000091Au, /* cpuss.dw1_tr_out[9] */
577     TRIG9_IN_CPUSS_DW1_TR_OUT10     = 0x0000091Bu, /* cpuss.dw1_tr_out[10] */
578     TRIG9_IN_CPUSS_DW1_TR_OUT11     = 0x0000091Cu, /* cpuss.dw1_tr_out[11] */
579     TRIG9_IN_CPUSS_DW1_TR_OUT12     = 0x0000091Du, /* cpuss.dw1_tr_out[12] */
580     TRIG9_IN_CPUSS_DW1_TR_OUT13     = 0x0000091Eu, /* cpuss.dw1_tr_out[13] */
581     TRIG9_IN_CPUSS_DW1_TR_OUT14     = 0x0000091Fu, /* cpuss.dw1_tr_out[14] */
582     TRIG9_IN_CPUSS_DW1_TR_OUT15     = 0x00000920u /* cpuss.dw1_tr_out[15] */
583 } en_trig_input_grp9_t;
584 
585 /* Trigger Input Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
586 typedef enum
587 {
588     TRIG10_IN_CPUSS_ZERO            = 0x00000A00u, /* cpuss.zero */
589     TRIG10_IN_CPUSS_DW0_TR_OUT0     = 0x00000A01u, /* cpuss.dw0_tr_out[0] */
590     TRIG10_IN_CPUSS_DW0_TR_OUT1     = 0x00000A02u, /* cpuss.dw0_tr_out[1] */
591     TRIG10_IN_CPUSS_DW0_TR_OUT2     = 0x00000A03u, /* cpuss.dw0_tr_out[2] */
592     TRIG10_IN_CPUSS_DW0_TR_OUT3     = 0x00000A04u, /* cpuss.dw0_tr_out[3] */
593     TRIG10_IN_CPUSS_DW0_TR_OUT4     = 0x00000A05u, /* cpuss.dw0_tr_out[4] */
594     TRIG10_IN_CPUSS_DW0_TR_OUT5     = 0x00000A06u, /* cpuss.dw0_tr_out[5] */
595     TRIG10_IN_CPUSS_DW0_TR_OUT6     = 0x00000A07u, /* cpuss.dw0_tr_out[6] */
596     TRIG10_IN_CPUSS_DW0_TR_OUT7     = 0x00000A08u, /* cpuss.dw0_tr_out[7] */
597     TRIG10_IN_CPUSS_DW0_TR_OUT8     = 0x00000A09u, /* cpuss.dw0_tr_out[8] */
598     TRIG10_IN_CPUSS_DW0_TR_OUT9     = 0x00000A0Au, /* cpuss.dw0_tr_out[9] */
599     TRIG10_IN_CPUSS_DW0_TR_OUT10    = 0x00000A0Bu, /* cpuss.dw0_tr_out[10] */
600     TRIG10_IN_CPUSS_DW0_TR_OUT11    = 0x00000A0Cu, /* cpuss.dw0_tr_out[11] */
601     TRIG10_IN_CPUSS_DW0_TR_OUT12    = 0x00000A0Du, /* cpuss.dw0_tr_out[12] */
602     TRIG10_IN_CPUSS_DW0_TR_OUT13    = 0x00000A0Eu, /* cpuss.dw0_tr_out[13] */
603     TRIG10_IN_CPUSS_DW0_TR_OUT14    = 0x00000A0Fu, /* cpuss.dw0_tr_out[14] */
604     TRIG10_IN_CPUSS_DW0_TR_OUT15    = 0x00000A10u, /* cpuss.dw0_tr_out[15] */
605     TRIG10_IN_CPUSS_DW1_TR_OUT0     = 0x00000A11u, /* cpuss.dw1_tr_out[0] */
606     TRIG10_IN_CPUSS_DW1_TR_OUT1     = 0x00000A12u, /* cpuss.dw1_tr_out[1] */
607     TRIG10_IN_CPUSS_DW1_TR_OUT2     = 0x00000A13u, /* cpuss.dw1_tr_out[2] */
608     TRIG10_IN_CPUSS_DW1_TR_OUT3     = 0x00000A14u, /* cpuss.dw1_tr_out[3] */
609     TRIG10_IN_CPUSS_DW1_TR_OUT4     = 0x00000A15u, /* cpuss.dw1_tr_out[4] */
610     TRIG10_IN_CPUSS_DW1_TR_OUT5     = 0x00000A16u, /* cpuss.dw1_tr_out[5] */
611     TRIG10_IN_CPUSS_DW1_TR_OUT6     = 0x00000A17u, /* cpuss.dw1_tr_out[6] */
612     TRIG10_IN_CPUSS_DW1_TR_OUT7     = 0x00000A18u, /* cpuss.dw1_tr_out[7] */
613     TRIG10_IN_CPUSS_DW1_TR_OUT8     = 0x00000A19u, /* cpuss.dw1_tr_out[8] */
614     TRIG10_IN_CPUSS_DW1_TR_OUT9     = 0x00000A1Au, /* cpuss.dw1_tr_out[9] */
615     TRIG10_IN_CPUSS_DW1_TR_OUT10    = 0x00000A1Bu, /* cpuss.dw1_tr_out[10] */
616     TRIG10_IN_CPUSS_DW1_TR_OUT11    = 0x00000A1Cu, /* cpuss.dw1_tr_out[11] */
617     TRIG10_IN_CPUSS_DW1_TR_OUT12    = 0x00000A1Du, /* cpuss.dw1_tr_out[12] */
618     TRIG10_IN_CPUSS_DW1_TR_OUT13    = 0x00000A1Eu, /* cpuss.dw1_tr_out[13] */
619     TRIG10_IN_CPUSS_DW1_TR_OUT14    = 0x00000A1Fu, /* cpuss.dw1_tr_out[14] */
620     TRIG10_IN_CPUSS_DW1_TR_OUT15    = 0x00000A20u /* cpuss.dw1_tr_out[15] */
621 } en_trig_input_grp10_t;
622 
623 /* Trigger Input Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
624 typedef enum
625 {
626     TRIG11_IN_CPUSS_ZERO            = 0x00000B00u, /* cpuss.zero */
627     TRIG11_IN_TCPWM0_TR_OVERFLOW0   = 0x00000B01u, /* tcpwm[0].tr_overflow[0] */
628     TRIG11_IN_TCPWM0_TR_OVERFLOW1   = 0x00000B02u, /* tcpwm[0].tr_overflow[1] */
629     TRIG11_IN_TCPWM0_TR_OVERFLOW2   = 0x00000B03u, /* tcpwm[0].tr_overflow[2] */
630     TRIG11_IN_TCPWM0_TR_OVERFLOW3   = 0x00000B04u, /* tcpwm[0].tr_overflow[3] */
631     TRIG11_IN_TCPWM0_TR_OVERFLOW4   = 0x00000B05u, /* tcpwm[0].tr_overflow[4] */
632     TRIG11_IN_TCPWM0_TR_OVERFLOW5   = 0x00000B06u, /* tcpwm[0].tr_overflow[5] */
633     TRIG11_IN_TCPWM0_TR_OVERFLOW6   = 0x00000B07u, /* tcpwm[0].tr_overflow[6] */
634     TRIG11_IN_TCPWM0_TR_OVERFLOW7   = 0x00000B08u, /* tcpwm[0].tr_overflow[7] */
635     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH0 = 0x00000B09u, /* tcpwm[0].tr_compare_match[0] */
636     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH1 = 0x00000B0Au, /* tcpwm[0].tr_compare_match[1] */
637     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH2 = 0x00000B0Bu, /* tcpwm[0].tr_compare_match[2] */
638     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH3 = 0x00000B0Cu, /* tcpwm[0].tr_compare_match[3] */
639     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH4 = 0x00000B0Du, /* tcpwm[0].tr_compare_match[4] */
640     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH5 = 0x00000B0Eu, /* tcpwm[0].tr_compare_match[5] */
641     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH6 = 0x00000B0Fu, /* tcpwm[0].tr_compare_match[6] */
642     TRIG11_IN_TCPWM0_TR_COMPARE_MATCH7 = 0x00000B10u, /* tcpwm[0].tr_compare_match[7] */
643     TRIG11_IN_TCPWM0_TR_UNDERFLOW0  = 0x00000B11u, /* tcpwm[0].tr_underflow[0] */
644     TRIG11_IN_TCPWM0_TR_UNDERFLOW1  = 0x00000B12u, /* tcpwm[0].tr_underflow[1] */
645     TRIG11_IN_TCPWM0_TR_UNDERFLOW2  = 0x00000B13u, /* tcpwm[0].tr_underflow[2] */
646     TRIG11_IN_TCPWM0_TR_UNDERFLOW3  = 0x00000B14u, /* tcpwm[0].tr_underflow[3] */
647     TRIG11_IN_TCPWM0_TR_UNDERFLOW4  = 0x00000B15u, /* tcpwm[0].tr_underflow[4] */
648     TRIG11_IN_TCPWM0_TR_UNDERFLOW5  = 0x00000B16u, /* tcpwm[0].tr_underflow[5] */
649     TRIG11_IN_TCPWM0_TR_UNDERFLOW6  = 0x00000B17u, /* tcpwm[0].tr_underflow[6] */
650     TRIG11_IN_TCPWM0_TR_UNDERFLOW7  = 0x00000B18u, /* tcpwm[0].tr_underflow[7] */
651     TRIG11_IN_TCPWM1_TR_OVERFLOW0   = 0x00000B19u, /* tcpwm[1].tr_overflow[0] */
652     TRIG11_IN_TCPWM1_TR_OVERFLOW1   = 0x00000B1Au, /* tcpwm[1].tr_overflow[1] */
653     TRIG11_IN_TCPWM1_TR_OVERFLOW2   = 0x00000B1Bu, /* tcpwm[1].tr_overflow[2] */
654     TRIG11_IN_TCPWM1_TR_OVERFLOW3   = 0x00000B1Cu, /* tcpwm[1].tr_overflow[3] */
655     TRIG11_IN_TCPWM1_TR_OVERFLOW4   = 0x00000B1Du, /* tcpwm[1].tr_overflow[4] */
656     TRIG11_IN_TCPWM1_TR_OVERFLOW5   = 0x00000B1Eu, /* tcpwm[1].tr_overflow[5] */
657     TRIG11_IN_TCPWM1_TR_OVERFLOW6   = 0x00000B1Fu, /* tcpwm[1].tr_overflow[6] */
658     TRIG11_IN_TCPWM1_TR_OVERFLOW7   = 0x00000B20u, /* tcpwm[1].tr_overflow[7] */
659     TRIG11_IN_TCPWM1_TR_OVERFLOW8   = 0x00000B21u, /* tcpwm[1].tr_overflow[8] */
660     TRIG11_IN_TCPWM1_TR_OVERFLOW9   = 0x00000B22u, /* tcpwm[1].tr_overflow[9] */
661     TRIG11_IN_TCPWM1_TR_OVERFLOW10  = 0x00000B23u, /* tcpwm[1].tr_overflow[10] */
662     TRIG11_IN_TCPWM1_TR_OVERFLOW11  = 0x00000B24u, /* tcpwm[1].tr_overflow[11] */
663     TRIG11_IN_TCPWM1_TR_OVERFLOW12  = 0x00000B25u, /* tcpwm[1].tr_overflow[12] */
664     TRIG11_IN_TCPWM1_TR_OVERFLOW13  = 0x00000B26u, /* tcpwm[1].tr_overflow[13] */
665     TRIG11_IN_TCPWM1_TR_OVERFLOW14  = 0x00000B27u, /* tcpwm[1].tr_overflow[14] */
666     TRIG11_IN_TCPWM1_TR_OVERFLOW15  = 0x00000B28u, /* tcpwm[1].tr_overflow[15] */
667     TRIG11_IN_TCPWM1_TR_OVERFLOW16  = 0x00000B29u, /* tcpwm[1].tr_overflow[16] */
668     TRIG11_IN_TCPWM1_TR_OVERFLOW17  = 0x00000B2Au, /* tcpwm[1].tr_overflow[17] */
669     TRIG11_IN_TCPWM1_TR_OVERFLOW18  = 0x00000B2Bu, /* tcpwm[1].tr_overflow[18] */
670     TRIG11_IN_TCPWM1_TR_OVERFLOW19  = 0x00000B2Cu, /* tcpwm[1].tr_overflow[19] */
671     TRIG11_IN_TCPWM1_TR_OVERFLOW20  = 0x00000B2Du, /* tcpwm[1].tr_overflow[20] */
672     TRIG11_IN_TCPWM1_TR_OVERFLOW21  = 0x00000B2Eu, /* tcpwm[1].tr_overflow[21] */
673     TRIG11_IN_TCPWM1_TR_OVERFLOW22  = 0x00000B2Fu, /* tcpwm[1].tr_overflow[22] */
674     TRIG11_IN_TCPWM1_TR_OVERFLOW23  = 0x00000B30u, /* tcpwm[1].tr_overflow[23] */
675     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH0 = 0x00000B31u, /* tcpwm[1].tr_compare_match[0] */
676     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH1 = 0x00000B32u, /* tcpwm[1].tr_compare_match[1] */
677     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH2 = 0x00000B33u, /* tcpwm[1].tr_compare_match[2] */
678     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH3 = 0x00000B34u, /* tcpwm[1].tr_compare_match[3] */
679     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH4 = 0x00000B35u, /* tcpwm[1].tr_compare_match[4] */
680     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH5 = 0x00000B36u, /* tcpwm[1].tr_compare_match[5] */
681     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH6 = 0x00000B37u, /* tcpwm[1].tr_compare_match[6] */
682     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH7 = 0x00000B38u, /* tcpwm[1].tr_compare_match[7] */
683     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH8 = 0x00000B39u, /* tcpwm[1].tr_compare_match[8] */
684     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH9 = 0x00000B3Au, /* tcpwm[1].tr_compare_match[9] */
685     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH10 = 0x00000B3Bu, /* tcpwm[1].tr_compare_match[10] */
686     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH11 = 0x00000B3Cu, /* tcpwm[1].tr_compare_match[11] */
687     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH12 = 0x00000B3Du, /* tcpwm[1].tr_compare_match[12] */
688     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH13 = 0x00000B3Eu, /* tcpwm[1].tr_compare_match[13] */
689     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH14 = 0x00000B3Fu, /* tcpwm[1].tr_compare_match[14] */
690     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH15 = 0x00000B40u, /* tcpwm[1].tr_compare_match[15] */
691     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH16 = 0x00000B41u, /* tcpwm[1].tr_compare_match[16] */
692     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH17 = 0x00000B42u, /* tcpwm[1].tr_compare_match[17] */
693     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH18 = 0x00000B43u, /* tcpwm[1].tr_compare_match[18] */
694     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH19 = 0x00000B44u, /* tcpwm[1].tr_compare_match[19] */
695     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH20 = 0x00000B45u, /* tcpwm[1].tr_compare_match[20] */
696     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH21 = 0x00000B46u, /* tcpwm[1].tr_compare_match[21] */
697     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH22 = 0x00000B47u, /* tcpwm[1].tr_compare_match[22] */
698     TRIG11_IN_TCPWM1_TR_COMPARE_MATCH23 = 0x00000B48u, /* tcpwm[1].tr_compare_match[23] */
699     TRIG11_IN_TCPWM1_TR_UNDERFLOW0  = 0x00000B49u, /* tcpwm[1].tr_underflow[0] */
700     TRIG11_IN_TCPWM1_TR_UNDERFLOW1  = 0x00000B4Au, /* tcpwm[1].tr_underflow[1] */
701     TRIG11_IN_TCPWM1_TR_UNDERFLOW2  = 0x00000B4Bu, /* tcpwm[1].tr_underflow[2] */
702     TRIG11_IN_TCPWM1_TR_UNDERFLOW3  = 0x00000B4Cu, /* tcpwm[1].tr_underflow[3] */
703     TRIG11_IN_TCPWM1_TR_UNDERFLOW4  = 0x00000B4Du, /* tcpwm[1].tr_underflow[4] */
704     TRIG11_IN_TCPWM1_TR_UNDERFLOW5  = 0x00000B4Eu, /* tcpwm[1].tr_underflow[5] */
705     TRIG11_IN_TCPWM1_TR_UNDERFLOW6  = 0x00000B4Fu, /* tcpwm[1].tr_underflow[6] */
706     TRIG11_IN_TCPWM1_TR_UNDERFLOW7  = 0x00000B50u, /* tcpwm[1].tr_underflow[7] */
707     TRIG11_IN_TCPWM1_TR_UNDERFLOW8  = 0x00000B51u, /* tcpwm[1].tr_underflow[8] */
708     TRIG11_IN_TCPWM1_TR_UNDERFLOW9  = 0x00000B52u, /* tcpwm[1].tr_underflow[9] */
709     TRIG11_IN_TCPWM1_TR_UNDERFLOW10 = 0x00000B53u, /* tcpwm[1].tr_underflow[10] */
710     TRIG11_IN_TCPWM1_TR_UNDERFLOW11 = 0x00000B54u, /* tcpwm[1].tr_underflow[11] */
711     TRIG11_IN_TCPWM1_TR_UNDERFLOW12 = 0x00000B55u, /* tcpwm[1].tr_underflow[12] */
712     TRIG11_IN_TCPWM1_TR_UNDERFLOW13 = 0x00000B56u, /* tcpwm[1].tr_underflow[13] */
713     TRIG11_IN_TCPWM1_TR_UNDERFLOW14 = 0x00000B57u, /* tcpwm[1].tr_underflow[14] */
714     TRIG11_IN_TCPWM1_TR_UNDERFLOW15 = 0x00000B58u, /* tcpwm[1].tr_underflow[15] */
715     TRIG11_IN_TCPWM1_TR_UNDERFLOW16 = 0x00000B59u, /* tcpwm[1].tr_underflow[16] */
716     TRIG11_IN_TCPWM1_TR_UNDERFLOW17 = 0x00000B5Au, /* tcpwm[1].tr_underflow[17] */
717     TRIG11_IN_TCPWM1_TR_UNDERFLOW18 = 0x00000B5Bu, /* tcpwm[1].tr_underflow[18] */
718     TRIG11_IN_TCPWM1_TR_UNDERFLOW19 = 0x00000B5Cu, /* tcpwm[1].tr_underflow[19] */
719     TRIG11_IN_TCPWM1_TR_UNDERFLOW20 = 0x00000B5Du, /* tcpwm[1].tr_underflow[20] */
720     TRIG11_IN_TCPWM1_TR_UNDERFLOW21 = 0x00000B5Eu, /* tcpwm[1].tr_underflow[21] */
721     TRIG11_IN_TCPWM1_TR_UNDERFLOW22 = 0x00000B5Fu, /* tcpwm[1].tr_underflow[22] */
722     TRIG11_IN_TCPWM1_TR_UNDERFLOW23 = 0x00000B60u /* tcpwm[1].tr_underflow[23] */
723 } en_trig_input_grp11_t;
724 
725 /* Trigger Input Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
726 typedef enum
727 {
728     TRIG12_IN_CPUSS_ZERO            = 0x00000C00u, /* cpuss.zero */
729     TRIG12_IN_PERI_TR_IO_INPUT0     = 0x00000C01u, /* peri.tr_io_input[0] */
730     TRIG12_IN_PERI_TR_IO_INPUT1     = 0x00000C02u, /* peri.tr_io_input[1] */
731     TRIG12_IN_PERI_TR_IO_INPUT2     = 0x00000C03u, /* peri.tr_io_input[2] */
732     TRIG12_IN_PERI_TR_IO_INPUT3     = 0x00000C04u, /* peri.tr_io_input[3] */
733     TRIG12_IN_PERI_TR_IO_INPUT4     = 0x00000C05u, /* peri.tr_io_input[4] */
734     TRIG12_IN_PERI_TR_IO_INPUT5     = 0x00000C06u, /* peri.tr_io_input[5] */
735     TRIG12_IN_PERI_TR_IO_INPUT6     = 0x00000C07u, /* peri.tr_io_input[6] */
736     TRIG12_IN_PERI_TR_IO_INPUT7     = 0x00000C08u, /* peri.tr_io_input[7] */
737     TRIG12_IN_PERI_TR_IO_INPUT8     = 0x00000C09u, /* peri.tr_io_input[8] */
738     TRIG12_IN_PERI_TR_IO_INPUT9     = 0x00000C0Au, /* peri.tr_io_input[9] */
739     TRIG12_IN_PERI_TR_IO_INPUT10    = 0x00000C0Bu, /* peri.tr_io_input[10] */
740     TRIG12_IN_PERI_TR_IO_INPUT11    = 0x00000C0Cu, /* peri.tr_io_input[11] */
741     TRIG12_IN_PERI_TR_IO_INPUT12    = 0x00000C0Du, /* peri.tr_io_input[12] */
742     TRIG12_IN_PERI_TR_IO_INPUT13    = 0x00000C0Eu, /* peri.tr_io_input[13] */
743     TRIG12_IN_PERI_TR_IO_INPUT14    = 0x00000C0Fu, /* peri.tr_io_input[14] */
744     TRIG12_IN_PERI_TR_IO_INPUT15    = 0x00000C10u, /* peri.tr_io_input[15] */
745     TRIG12_IN_PERI_TR_IO_INPUT16    = 0x00000C11u, /* peri.tr_io_input[16] */
746     TRIG12_IN_PERI_TR_IO_INPUT17    = 0x00000C12u, /* peri.tr_io_input[17] */
747     TRIG12_IN_PERI_TR_IO_INPUT18    = 0x00000C13u, /* peri.tr_io_input[18] */
748     TRIG12_IN_PERI_TR_IO_INPUT19    = 0x00000C14u, /* peri.tr_io_input[19] */
749     TRIG12_IN_PERI_TR_IO_INPUT20    = 0x00000C15u, /* peri.tr_io_input[20] */
750     TRIG12_IN_PERI_TR_IO_INPUT21    = 0x00000C16u, /* peri.tr_io_input[21] */
751     TRIG12_IN_PERI_TR_IO_INPUT22    = 0x00000C17u, /* peri.tr_io_input[22] */
752     TRIG12_IN_PERI_TR_IO_INPUT23    = 0x00000C18u, /* peri.tr_io_input[23] */
753     TRIG12_IN_PERI_TR_IO_INPUT24    = 0x00000C19u, /* peri.tr_io_input[24] */
754     TRIG12_IN_PERI_TR_IO_INPUT25    = 0x00000C1Au, /* peri.tr_io_input[25] */
755     TRIG12_IN_PERI_TR_IO_INPUT26    = 0x00000C1Bu, /* peri.tr_io_input[26] */
756     TRIG12_IN_PERI_TR_IO_INPUT27    = 0x00000C1Cu /* peri.tr_io_input[27] */
757 } en_trig_input_grp12_t;
758 
759 /* Trigger Input Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
760 typedef enum
761 {
762     TRIG13_IN_CPUSS_ZERO            = 0x00000D00u, /* cpuss.zero */
763     TRIG13_IN_SCB0_TR_TX_REQ        = 0x00000D01u, /* scb[0].tr_tx_req */
764     TRIG13_IN_SCB0_TR_RX_REQ        = 0x00000D02u, /* scb[0].tr_rx_req */
765     TRIG13_IN_SCB1_TR_TX_REQ        = 0x00000D03u, /* scb[1].tr_tx_req */
766     TRIG13_IN_SCB1_TR_RX_REQ        = 0x00000D04u, /* scb[1].tr_rx_req */
767     TRIG13_IN_SCB2_TR_TX_REQ        = 0x00000D05u, /* scb[2].tr_tx_req */
768     TRIG13_IN_SCB2_TR_RX_REQ        = 0x00000D06u, /* scb[2].tr_rx_req */
769     TRIG13_IN_SCB3_TR_TX_REQ        = 0x00000D07u, /* scb[3].tr_tx_req */
770     TRIG13_IN_SCB3_TR_RX_REQ        = 0x00000D08u, /* scb[3].tr_rx_req */
771     TRIG13_IN_SCB4_TR_TX_REQ        = 0x00000D09u, /* scb[4].tr_tx_req */
772     TRIG13_IN_SCB4_TR_RX_REQ        = 0x00000D0Au, /* scb[4].tr_rx_req */
773     TRIG13_IN_SCB5_TR_TX_REQ        = 0x00000D0Bu, /* scb[5].tr_tx_req */
774     TRIG13_IN_SCB5_TR_RX_REQ        = 0x00000D0Cu, /* scb[5].tr_rx_req */
775     TRIG13_IN_SCB6_TR_TX_REQ        = 0x00000D0Du, /* scb[6].tr_tx_req */
776     TRIG13_IN_SCB6_TR_RX_REQ        = 0x00000D0Eu, /* scb[6].tr_rx_req */
777     TRIG13_IN_SCB7_TR_TX_REQ        = 0x00000D0Fu, /* scb[7].tr_tx_req */
778     TRIG13_IN_SCB7_TR_RX_REQ        = 0x00000D10u, /* scb[7].tr_rx_req */
779     TRIG13_IN_SCB8_TR_TX_REQ        = 0x00000D11u, /* scb[8].tr_tx_req */
780     TRIG13_IN_SCB8_TR_RX_REQ        = 0x00000D12u, /* scb[8].tr_rx_req */
781     TRIG13_IN_AUDIOSS_TR_PDM_RX_REQ = 0x00000D13u, /* audioss.tr_pdm_rx_req */
782     TRIG13_IN_AUDIOSS_TR_I2S_TX_REQ = 0x00000D14u, /* audioss.tr_i2s_tx_req */
783     TRIG13_IN_AUDIOSS_TR_I2S_RX_REQ = 0x00000D15u, /* audioss.tr_i2s_rx_req */
784     TRIG13_IN_SMIF_TR_TX_REQ        = 0x00000D16u, /* smif.tr_tx_req */
785     TRIG13_IN_SMIF_TR_RX_REQ        = 0x00000D17u, /* smif.tr_rx_req */
786     TRIG13_IN_USB_DMA_REQ0          = 0x00000D18u, /* usb.dma_req[0] */
787     TRIG13_IN_USB_DMA_REQ1          = 0x00000D19u, /* usb.dma_req[1] */
788     TRIG13_IN_USB_DMA_REQ2          = 0x00000D1Au, /* usb.dma_req[2] */
789     TRIG13_IN_USB_DMA_REQ3          = 0x00000D1Bu, /* usb.dma_req[3] */
790     TRIG13_IN_USB_DMA_REQ4          = 0x00000D1Cu, /* usb.dma_req[4] */
791     TRIG13_IN_USB_DMA_REQ5          = 0x00000D1Du, /* usb.dma_req[5] */
792     TRIG13_IN_USB_DMA_REQ6          = 0x00000D1Eu, /* usb.dma_req[6] */
793     TRIG13_IN_USB_DMA_REQ7          = 0x00000D1Fu, /* usb.dma_req[7] */
794     TRIG13_IN_CSD_TR_ADC_DONE       = 0x00000D20u, /* csd.tr_adc_done */
795     TRIG13_IN_CSD_DSI_SENSE_OUT     = 0x00000D21u /* csd.dsi_sense_out */
796 } en_trig_input_grp13_t;
797 
798 /* Trigger Input Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
799 typedef enum
800 {
801     TRIG14_IN_CPUSS_ZERO            = 0x00000E00u, /* cpuss.zero */
802     TRIG14_IN_UDB_TR_UDB0           = 0x00000E01u, /* udb.tr_udb[0] */
803     TRIG14_IN_UDB_TR_UDB1           = 0x00000E02u, /* udb.tr_udb[1] */
804     TRIG14_IN_UDB_TR_UDB2           = 0x00000E03u, /* udb.tr_udb[2] */
805     TRIG14_IN_UDB_TR_UDB3           = 0x00000E04u, /* udb.tr_udb[3] */
806     TRIG14_IN_UDB_TR_UDB4           = 0x00000E05u, /* udb.tr_udb[4] */
807     TRIG14_IN_UDB_TR_UDB5           = 0x00000E06u, /* udb.tr_udb[5] */
808     TRIG14_IN_UDB_TR_UDB6           = 0x00000E07u, /* udb.tr_udb[6] */
809     TRIG14_IN_UDB_TR_UDB7           = 0x00000E08u, /* udb.tr_udb[7] */
810     TRIG14_IN_UDB_TR_UDB8           = 0x00000E09u, /* udb.tr_udb[8] */
811     TRIG14_IN_UDB_TR_UDB9           = 0x00000E0Au, /* udb.tr_udb[9] */
812     TRIG14_IN_UDB_TR_UDB10          = 0x00000E0Bu, /* udb.tr_udb[10] */
813     TRIG14_IN_UDB_TR_UDB11          = 0x00000E0Cu, /* udb.tr_udb[11] */
814     TRIG14_IN_UDB_TR_UDB12          = 0x00000E0Du, /* udb.tr_udb[12] */
815     TRIG14_IN_UDB_TR_UDB13          = 0x00000E0Eu, /* udb.tr_udb[13] */
816     TRIG14_IN_UDB_TR_UDB14          = 0x00000E0Fu, /* udb.tr_udb[14] */
817     TRIG14_IN_UDB_TR_UDB15          = 0x00000E10u, /* udb.tr_udb[15] */
818     TRIG14_IN_UDB_DSI_OUT_TR0       = 0x00000E11u, /* udb.dsi_out_tr[0] */
819     TRIG14_IN_UDB_DSI_OUT_TR1       = 0x00000E12u, /* udb.dsi_out_tr[1] */
820     TRIG14_IN_CPUSS_CTI_TR_OUT0     = 0x00000E13u, /* cpuss.cti_tr_out[0] */
821     TRIG14_IN_CPUSS_CTI_TR_OUT1     = 0x00000E14u, /* cpuss.cti_tr_out[1] */
822     TRIG14_IN_PASS_TR_SAR_OUT       = 0x00000E15u, /* pass.tr_sar_out */
823     TRIG14_IN_PASS_TR_CTDAC_EMPTY   = 0x00000E16u, /* pass.tr_ctdac_empty */
824     TRIG14_IN_PASS_DSI_CTB_CMP0     = 0x00000E17u, /* pass.dsi_ctb_cmp0 */
825     TRIG14_IN_PASS_DSI_CTB_CMP1     = 0x00000E18u, /* pass.dsi_ctb_cmp1 */
826     TRIG14_IN_LPCOMP_DSI_COMP0      = 0x00000E19u, /* lpcomp.dsi_comp0 */
827     TRIG14_IN_LPCOMP_DSI_COMP1      = 0x00000E1Au, /* lpcomp.dsi_comp1 */
828     TRIG14_IN_SCB0_TR_I2C_SCL_FILTERED = 0x00000E1Bu, /* scb[0].tr_i2c_scl_filtered */
829     TRIG14_IN_SCB1_TR_I2C_SCL_FILTERED = 0x00000E1Cu, /* scb[1].tr_i2c_scl_filtered */
830     TRIG14_IN_SCB2_TR_I2C_SCL_FILTERED = 0x00000E1Du, /* scb[2].tr_i2c_scl_filtered */
831     TRIG14_IN_SCB3_TR_I2C_SCL_FILTERED = 0x00000E1Eu, /* scb[3].tr_i2c_scl_filtered */
832     TRIG14_IN_SCB4_TR_I2C_SCL_FILTERED = 0x00000E1Fu, /* scb[4].tr_i2c_scl_filtered */
833     TRIG14_IN_SCB5_TR_I2C_SCL_FILTERED = 0x00000E20u, /* scb[5].tr_i2c_scl_filtered */
834     TRIG14_IN_SCB6_TR_I2C_SCL_FILTERED = 0x00000E21u, /* scb[6].tr_i2c_scl_filtered */
835     TRIG14_IN_SCB7_TR_I2C_SCL_FILTERED = 0x00000E22u, /* scb[7].tr_i2c_scl_filtered */
836     TRIG14_IN_SCB8_TR_I2C_SCL_FILTERED = 0x00000E23u, /* scb[8].tr_i2c_scl_filtered */
837     TRIG14_IN_CPUSS_TR_FAULT0       = 0x00000E24u, /* cpuss.tr_fault[0] */
838     TRIG14_IN_CPUSS_TR_FAULT1       = 0x00000E25u /* cpuss.tr_fault[1] */
839 } en_trig_input_grp14_t;
840 
841 /* Trigger Group Outputs */
842 /* Trigger Output Group 0 - DMA Request Assignments */
843 typedef enum
844 {
845     TRIG0_OUT_CPUSS_DW0_TR_IN0      = 0x40000000u, /* cpuss.dw0_tr_in[0] */
846     TRIG0_OUT_CPUSS_DW0_TR_IN1      = 0x40000001u, /* cpuss.dw0_tr_in[1] */
847     TRIG0_OUT_CPUSS_DW0_TR_IN2      = 0x40000002u, /* cpuss.dw0_tr_in[2] */
848     TRIG0_OUT_CPUSS_DW0_TR_IN3      = 0x40000003u, /* cpuss.dw0_tr_in[3] */
849     TRIG0_OUT_CPUSS_DW0_TR_IN4      = 0x40000004u, /* cpuss.dw0_tr_in[4] */
850     TRIG0_OUT_CPUSS_DW0_TR_IN5      = 0x40000005u, /* cpuss.dw0_tr_in[5] */
851     TRIG0_OUT_CPUSS_DW0_TR_IN6      = 0x40000006u, /* cpuss.dw0_tr_in[6] */
852     TRIG0_OUT_CPUSS_DW0_TR_IN7      = 0x40000007u, /* cpuss.dw0_tr_in[7] */
853     TRIG0_OUT_CPUSS_DW0_TR_IN8      = 0x40000008u, /* cpuss.dw0_tr_in[8] */
854     TRIG0_OUT_CPUSS_DW0_TR_IN9      = 0x40000009u, /* cpuss.dw0_tr_in[9] */
855     TRIG0_OUT_CPUSS_DW0_TR_IN10     = 0x4000000Au, /* cpuss.dw0_tr_in[10] */
856     TRIG0_OUT_CPUSS_DW0_TR_IN11     = 0x4000000Bu, /* cpuss.dw0_tr_in[11] */
857     TRIG0_OUT_CPUSS_DW0_TR_IN12     = 0x4000000Cu, /* cpuss.dw0_tr_in[12] */
858     TRIG0_OUT_CPUSS_DW0_TR_IN13     = 0x4000000Du, /* cpuss.dw0_tr_in[13] */
859     TRIG0_OUT_CPUSS_DW0_TR_IN14     = 0x4000000Eu, /* cpuss.dw0_tr_in[14] */
860     TRIG0_OUT_CPUSS_DW0_TR_IN15     = 0x4000000Fu /* cpuss.dw0_tr_in[15] */
861 } en_trig_output_grp0_t;
862 
863 /* Trigger Output Group 1 - DMA Request Assignments */
864 typedef enum
865 {
866     TRIG1_OUT_CPUSS_DW1_TR_IN0      = 0x40000100u, /* cpuss.dw1_tr_in[0] */
867     TRIG1_OUT_CPUSS_DW1_TR_IN1      = 0x40000101u, /* cpuss.dw1_tr_in[1] */
868     TRIG1_OUT_CPUSS_DW1_TR_IN2      = 0x40000102u, /* cpuss.dw1_tr_in[2] */
869     TRIG1_OUT_CPUSS_DW1_TR_IN3      = 0x40000103u, /* cpuss.dw1_tr_in[3] */
870     TRIG1_OUT_CPUSS_DW1_TR_IN4      = 0x40000104u, /* cpuss.dw1_tr_in[4] */
871     TRIG1_OUT_CPUSS_DW1_TR_IN5      = 0x40000105u, /* cpuss.dw1_tr_in[5] */
872     TRIG1_OUT_CPUSS_DW1_TR_IN6      = 0x40000106u, /* cpuss.dw1_tr_in[6] */
873     TRIG1_OUT_CPUSS_DW1_TR_IN7      = 0x40000107u, /* cpuss.dw1_tr_in[7] */
874     TRIG1_OUT_CPUSS_DW1_TR_IN8      = 0x40000108u, /* cpuss.dw1_tr_in[8] */
875     TRIG1_OUT_CPUSS_DW1_TR_IN9      = 0x40000109u, /* cpuss.dw1_tr_in[9] */
876     TRIG1_OUT_CPUSS_DW1_TR_IN10     = 0x4000010Au, /* cpuss.dw1_tr_in[10] */
877     TRIG1_OUT_CPUSS_DW1_TR_IN11     = 0x4000010Bu, /* cpuss.dw1_tr_in[11] */
878     TRIG1_OUT_CPUSS_DW1_TR_IN12     = 0x4000010Cu, /* cpuss.dw1_tr_in[12] */
879     TRIG1_OUT_CPUSS_DW1_TR_IN13     = 0x4000010Du, /* cpuss.dw1_tr_in[13] */
880     TRIG1_OUT_CPUSS_DW1_TR_IN14     = 0x4000010Eu, /* cpuss.dw1_tr_in[14] */
881     TRIG1_OUT_CPUSS_DW1_TR_IN15     = 0x4000010Fu /* cpuss.dw1_tr_in[15] */
882 } en_trig_output_grp1_t;
883 
884 /* Trigger Output Group 2 - TCPWM trigger inputs */
885 typedef enum
886 {
887     TRIG2_OUT_TCPWM0_TR_IN0         = 0x40000200u, /* tcpwm[0].tr_in[0] */
888     TRIG2_OUT_TCPWM0_TR_IN1         = 0x40000201u, /* tcpwm[0].tr_in[1] */
889     TRIG2_OUT_TCPWM0_TR_IN2         = 0x40000202u, /* tcpwm[0].tr_in[2] */
890     TRIG2_OUT_TCPWM0_TR_IN3         = 0x40000203u, /* tcpwm[0].tr_in[3] */
891     TRIG2_OUT_TCPWM0_TR_IN4         = 0x40000204u, /* tcpwm[0].tr_in[4] */
892     TRIG2_OUT_TCPWM0_TR_IN5         = 0x40000205u, /* tcpwm[0].tr_in[5] */
893     TRIG2_OUT_TCPWM0_TR_IN6         = 0x40000206u, /* tcpwm[0].tr_in[6] */
894     TRIG2_OUT_TCPWM0_TR_IN7         = 0x40000207u, /* tcpwm[0].tr_in[7] */
895     TRIG2_OUT_TCPWM0_TR_IN8         = 0x40000208u, /* tcpwm[0].tr_in[8] */
896     TRIG2_OUT_TCPWM0_TR_IN9         = 0x40000209u, /* tcpwm[0].tr_in[9] */
897     TRIG2_OUT_TCPWM0_TR_IN10        = 0x4000020Au, /* tcpwm[0].tr_in[10] */
898     TRIG2_OUT_TCPWM0_TR_IN11        = 0x4000020Bu, /* tcpwm[0].tr_in[11] */
899     TRIG2_OUT_TCPWM0_TR_IN12        = 0x4000020Cu, /* tcpwm[0].tr_in[12] */
900     TRIG2_OUT_TCPWM0_TR_IN13        = 0x4000020Du /* tcpwm[0].tr_in[13] */
901 } en_trig_output_grp2_t;
902 
903 /* Trigger Output Group 3 - TCPWM trigger inputs */
904 typedef enum
905 {
906     TRIG3_OUT_TCPWM1_TR_IN0         = 0x40000300u, /* tcpwm[1].tr_in[0] */
907     TRIG3_OUT_TCPWM1_TR_IN1         = 0x40000301u, /* tcpwm[1].tr_in[1] */
908     TRIG3_OUT_TCPWM1_TR_IN2         = 0x40000302u, /* tcpwm[1].tr_in[2] */
909     TRIG3_OUT_TCPWM1_TR_IN3         = 0x40000303u, /* tcpwm[1].tr_in[3] */
910     TRIG3_OUT_TCPWM1_TR_IN4         = 0x40000304u, /* tcpwm[1].tr_in[4] */
911     TRIG3_OUT_TCPWM1_TR_IN5         = 0x40000305u, /* tcpwm[1].tr_in[5] */
912     TRIG3_OUT_TCPWM1_TR_IN6         = 0x40000306u, /* tcpwm[1].tr_in[6] */
913     TRIG3_OUT_TCPWM1_TR_IN7         = 0x40000307u, /* tcpwm[1].tr_in[7] */
914     TRIG3_OUT_TCPWM1_TR_IN8         = 0x40000308u, /* tcpwm[1].tr_in[8] */
915     TRIG3_OUT_TCPWM1_TR_IN9         = 0x40000309u, /* tcpwm[1].tr_in[9] */
916     TRIG3_OUT_TCPWM1_TR_IN10        = 0x4000030Au, /* tcpwm[1].tr_in[10] */
917     TRIG3_OUT_TCPWM1_TR_IN11        = 0x4000030Bu, /* tcpwm[1].tr_in[11] */
918     TRIG3_OUT_TCPWM1_TR_IN12        = 0x4000030Cu, /* tcpwm[1].tr_in[12] */
919     TRIG3_OUT_TCPWM1_TR_IN13        = 0x4000030Du /* tcpwm[1].tr_in[13] */
920 } en_trig_output_grp3_t;
921 
922 /* Trigger Output Group 4 - PROFILE trigger multiplexer */
923 typedef enum
924 {
925     TRIG4_OUT_PROFILE_TR_START      = 0x40000400u, /* profile.tr_start */
926     TRIG4_OUT_PROFILE_TR_STOP       = 0x40000401u /* profile.tr_stop */
927 } en_trig_output_grp4_t;
928 
929 /* Trigger Output Group 5 - CPUSS.CTI trigger multiplexer */
930 typedef enum
931 {
932     TRIG5_OUT_CPUSS_CTI_TR_IN0      = 0x40000500u, /* cpuss.cti_tr_in[0] */
933     TRIG5_OUT_CPUSS_CTI_TR_IN1      = 0x40000501u /* cpuss.cti_tr_in[1] */
934 } en_trig_output_grp5_t;
935 
936 /* Trigger Output Group 6 - PASS trigger multiplexer */
937 typedef enum
938 {
939     TRIG6_OUT_PASS_TR_SAR_IN        = 0x40000600u /* pass.tr_sar_in */
940 } en_trig_output_grp6_t;
941 
942 /* Trigger Output Group 7 - UDB general purpose trigger multiplexer */
943 typedef enum
944 {
945     TRIG7_OUT_UDB_TR_IN0            = 0x40000700u, /* udb.tr_in[0] */
946     TRIG7_OUT_UDB_TR_IN1            = 0x40000701u /* udb.tr_in[1] */
947 } en_trig_output_grp7_t;
948 
949 /* Trigger Output Group 8 - Trigger multiplexer to pins */
950 typedef enum
951 {
952     TRIG8_OUT_PERI_TR_IO_OUTPUT0    = 0x40000800u, /* peri.tr_io_output[0] */
953     TRIG8_OUT_PERI_TR_IO_OUTPUT1    = 0x40000801u /* peri.tr_io_output[1] */
954 } en_trig_output_grp8_t;
955 
956 /* Trigger Output Group 9 - Feedback mux to USB DMA interface */
957 typedef enum
958 {
959     TRIG9_OUT_USB_DMA_BURSTEND0     = 0x40000900u, /* usb.dma_burstend[0] */
960     TRIG9_OUT_USB_DMA_BURSTEND1     = 0x40000901u, /* usb.dma_burstend[1] */
961     TRIG9_OUT_USB_DMA_BURSTEND2     = 0x40000902u, /* usb.dma_burstend[2] */
962     TRIG9_OUT_USB_DMA_BURSTEND3     = 0x40000903u, /* usb.dma_burstend[3] */
963     TRIG9_OUT_USB_DMA_BURSTEND4     = 0x40000904u, /* usb.dma_burstend[4] */
964     TRIG9_OUT_USB_DMA_BURSTEND5     = 0x40000905u, /* usb.dma_burstend[5] */
965     TRIG9_OUT_USB_DMA_BURSTEND6     = 0x40000906u, /* usb.dma_burstend[6] */
966     TRIG9_OUT_USB_DMA_BURSTEND7     = 0x40000907u /* usb.dma_burstend[7] */
967 } en_trig_output_grp9_t;
968 
969 /* Trigger Output Group 10 - Reduces 32 datawire output triggers to 8 signals, used by all except USB */
970 typedef enum
971 {
972     TRIG10_OUT_UDB_TR_DW_ACK0       = 0x40000A00u, /* udb.tr_dw_ack[0] */
973     TRIG10_OUT_TR_GROUP0_INPUT1     = 0x40000A00u, /* tr_group[0].input[1] */
974     TRIG10_OUT_TR_GROUP1_INPUT1     = 0x40000A00u, /* tr_group[1].input[1] */
975     TRIG10_OUT_TR_GROUP2_INPUT1     = 0x40000A00u, /* tr_group[2].input[1] */
976     TRIG10_OUT_TR_GROUP3_INPUT1     = 0x40000A00u, /* tr_group[3].input[1] */
977     TRIG10_OUT_TR_GROUP4_INPUT1     = 0x40000A00u, /* tr_group[4].input[1] */
978     TRIG10_OUT_TR_GROUP5_INPUT1     = 0x40000A00u, /* tr_group[5].input[1] */
979     TRIG10_OUT_TR_GROUP6_INPUT1     = 0x40000A00u, /* tr_group[6].input[1] */
980     TRIG10_OUT_TR_GROUP7_INPUT1     = 0x40000A00u, /* tr_group[7].input[1] */
981     TRIG10_OUT_TR_GROUP8_INPUT1     = 0x40000A00u, /* tr_group[8].input[1] */
982     TRIG10_OUT_UDB_TR_DW_ACK1       = 0x40000A01u, /* udb.tr_dw_ack[1] */
983     TRIG10_OUT_TR_GROUP0_INPUT2     = 0x40000A01u, /* tr_group[0].input[2] */
984     TRIG10_OUT_TR_GROUP1_INPUT2     = 0x40000A01u, /* tr_group[1].input[2] */
985     TRIG10_OUT_TR_GROUP2_INPUT2     = 0x40000A01u, /* tr_group[2].input[2] */
986     TRIG10_OUT_TR_GROUP3_INPUT2     = 0x40000A01u, /* tr_group[3].input[2] */
987     TRIG10_OUT_TR_GROUP4_INPUT2     = 0x40000A01u, /* tr_group[4].input[2] */
988     TRIG10_OUT_TR_GROUP5_INPUT2     = 0x40000A01u, /* tr_group[5].input[2] */
989     TRIG10_OUT_TR_GROUP6_INPUT2     = 0x40000A01u, /* tr_group[6].input[2] */
990     TRIG10_OUT_TR_GROUP7_INPUT2     = 0x40000A01u, /* tr_group[7].input[2] */
991     TRIG10_OUT_TR_GROUP8_INPUT2     = 0x40000A01u, /* tr_group[8].input[2] */
992     TRIG10_OUT_UDB_TR_DW_ACK2       = 0x40000A02u, /* udb.tr_dw_ack[2] */
993     TRIG10_OUT_TR_GROUP0_INPUT3     = 0x40000A02u, /* tr_group[0].input[3] */
994     TRIG10_OUT_TR_GROUP1_INPUT3     = 0x40000A02u, /* tr_group[1].input[3] */
995     TRIG10_OUT_TR_GROUP2_INPUT3     = 0x40000A02u, /* tr_group[2].input[3] */
996     TRIG10_OUT_TR_GROUP3_INPUT3     = 0x40000A02u, /* tr_group[3].input[3] */
997     TRIG10_OUT_TR_GROUP4_INPUT3     = 0x40000A02u, /* tr_group[4].input[3] */
998     TRIG10_OUT_TR_GROUP5_INPUT3     = 0x40000A02u, /* tr_group[5].input[3] */
999     TRIG10_OUT_TR_GROUP6_INPUT3     = 0x40000A02u, /* tr_group[6].input[3] */
1000     TRIG10_OUT_TR_GROUP7_INPUT3     = 0x40000A02u, /* tr_group[7].input[3] */
1001     TRIG10_OUT_TR_GROUP8_INPUT3     = 0x40000A02u, /* tr_group[8].input[3] */
1002     TRIG10_OUT_UDB_TR_DW_ACK3       = 0x40000A03u, /* udb.tr_dw_ack[3] */
1003     TRIG10_OUT_TR_GROUP0_INPUT4     = 0x40000A03u, /* tr_group[0].input[4] */
1004     TRIG10_OUT_TR_GROUP1_INPUT4     = 0x40000A03u, /* tr_group[1].input[4] */
1005     TRIG10_OUT_TR_GROUP2_INPUT4     = 0x40000A03u, /* tr_group[2].input[4] */
1006     TRIG10_OUT_TR_GROUP3_INPUT4     = 0x40000A03u, /* tr_group[3].input[4] */
1007     TRIG10_OUT_TR_GROUP4_INPUT4     = 0x40000A03u, /* tr_group[4].input[4] */
1008     TRIG10_OUT_TR_GROUP5_INPUT4     = 0x40000A03u, /* tr_group[5].input[4] */
1009     TRIG10_OUT_TR_GROUP6_INPUT4     = 0x40000A03u, /* tr_group[6].input[4] */
1010     TRIG10_OUT_TR_GROUP7_INPUT4     = 0x40000A03u, /* tr_group[7].input[4] */
1011     TRIG10_OUT_TR_GROUP8_INPUT4     = 0x40000A03u, /* tr_group[8].input[4] */
1012     TRIG10_OUT_UDB_TR_DW_ACK4       = 0x40000A04u, /* udb.tr_dw_ack[4] */
1013     TRIG10_OUT_TR_GROUP0_INPUT5     = 0x40000A04u, /* tr_group[0].input[5] */
1014     TRIG10_OUT_TR_GROUP1_INPUT5     = 0x40000A04u, /* tr_group[1].input[5] */
1015     TRIG10_OUT_TR_GROUP2_INPUT5     = 0x40000A04u, /* tr_group[2].input[5] */
1016     TRIG10_OUT_TR_GROUP3_INPUT5     = 0x40000A04u, /* tr_group[3].input[5] */
1017     TRIG10_OUT_TR_GROUP4_INPUT5     = 0x40000A04u, /* tr_group[4].input[5] */
1018     TRIG10_OUT_TR_GROUP5_INPUT5     = 0x40000A04u, /* tr_group[5].input[5] */
1019     TRIG10_OUT_TR_GROUP6_INPUT5     = 0x40000A04u, /* tr_group[6].input[5] */
1020     TRIG10_OUT_TR_GROUP7_INPUT5     = 0x40000A04u, /* tr_group[7].input[5] */
1021     TRIG10_OUT_TR_GROUP8_INPUT5     = 0x40000A04u, /* tr_group[8].input[5] */
1022     TRIG10_OUT_UDB_TR_DW_ACK5       = 0x40000A05u, /* udb.tr_dw_ack[5] */
1023     TRIG10_OUT_TR_GROUP0_INPUT6     = 0x40000A05u, /* tr_group[0].input[6] */
1024     TRIG10_OUT_TR_GROUP1_INPUT6     = 0x40000A05u, /* tr_group[1].input[6] */
1025     TRIG10_OUT_TR_GROUP2_INPUT6     = 0x40000A05u, /* tr_group[2].input[6] */
1026     TRIG10_OUT_TR_GROUP3_INPUT6     = 0x40000A05u, /* tr_group[3].input[6] */
1027     TRIG10_OUT_TR_GROUP4_INPUT6     = 0x40000A05u, /* tr_group[4].input[6] */
1028     TRIG10_OUT_TR_GROUP5_INPUT6     = 0x40000A05u, /* tr_group[5].input[6] */
1029     TRIG10_OUT_TR_GROUP6_INPUT6     = 0x40000A05u, /* tr_group[6].input[6] */
1030     TRIG10_OUT_TR_GROUP7_INPUT6     = 0x40000A05u, /* tr_group[7].input[6] */
1031     TRIG10_OUT_TR_GROUP8_INPUT6     = 0x40000A05u, /* tr_group[8].input[6] */
1032     TRIG10_OUT_UDB_TR_DW_ACK6       = 0x40000A06u, /* udb.tr_dw_ack[6] */
1033     TRIG10_OUT_TR_GROUP0_INPUT7     = 0x40000A06u, /* tr_group[0].input[7] */
1034     TRIG10_OUT_TR_GROUP1_INPUT7     = 0x40000A06u, /* tr_group[1].input[7] */
1035     TRIG10_OUT_TR_GROUP2_INPUT7     = 0x40000A06u, /* tr_group[2].input[7] */
1036     TRIG10_OUT_TR_GROUP3_INPUT7     = 0x40000A06u, /* tr_group[3].input[7] */
1037     TRIG10_OUT_TR_GROUP4_INPUT7     = 0x40000A06u, /* tr_group[4].input[7] */
1038     TRIG10_OUT_TR_GROUP5_INPUT7     = 0x40000A06u, /* tr_group[5].input[7] */
1039     TRIG10_OUT_TR_GROUP6_INPUT7     = 0x40000A06u, /* tr_group[6].input[7] */
1040     TRIG10_OUT_TR_GROUP7_INPUT7     = 0x40000A06u, /* tr_group[7].input[7] */
1041     TRIG10_OUT_TR_GROUP8_INPUT7     = 0x40000A06u, /* tr_group[8].input[7] */
1042     TRIG10_OUT_UDB_TR_DW_ACK7       = 0x40000A07u, /* udb.tr_dw_ack[7] */
1043     TRIG10_OUT_TR_GROUP0_INPUT8     = 0x40000A07u, /* tr_group[0].input[8] */
1044     TRIG10_OUT_TR_GROUP1_INPUT8     = 0x40000A07u, /* tr_group[1].input[8] */
1045     TRIG10_OUT_TR_GROUP2_INPUT8     = 0x40000A07u, /* tr_group[2].input[8] */
1046     TRIG10_OUT_TR_GROUP3_INPUT8     = 0x40000A07u, /* tr_group[3].input[8] */
1047     TRIG10_OUT_TR_GROUP4_INPUT8     = 0x40000A07u, /* tr_group[4].input[8] */
1048     TRIG10_OUT_TR_GROUP5_INPUT8     = 0x40000A07u, /* tr_group[5].input[8] */
1049     TRIG10_OUT_TR_GROUP6_INPUT8     = 0x40000A07u, /* tr_group[6].input[8] */
1050     TRIG10_OUT_TR_GROUP7_INPUT8     = 0x40000A07u, /* tr_group[7].input[8] */
1051     TRIG10_OUT_TR_GROUP8_INPUT8     = 0x40000A07u /* tr_group[8].input[8] */
1052 } en_trig_output_grp10_t;
1053 
1054 /* Trigger Output Group 11 - Reduces 96 tcpwm output triggers to 16 signals, used by all sinks */
1055 typedef enum
1056 {
1057     TRIG11_OUT_TR_GROUP0_INPUT9     = 0x40000B00u, /* tr_group[0].input[9] */
1058     TRIG11_OUT_TR_GROUP1_INPUT9     = 0x40000B00u, /* tr_group[1].input[9] */
1059     TRIG11_OUT_TR_GROUP2_INPUT9     = 0x40000B00u, /* tr_group[2].input[9] */
1060     TRIG11_OUT_TR_GROUP3_INPUT9     = 0x40000B00u, /* tr_group[3].input[9] */
1061     TRIG11_OUT_TR_GROUP4_INPUT9     = 0x40000B00u, /* tr_group[4].input[9] */
1062     TRIG11_OUT_TR_GROUP5_INPUT9     = 0x40000B00u, /* tr_group[5].input[9] */
1063     TRIG11_OUT_TR_GROUP6_INPUT9     = 0x40000B00u, /* tr_group[6].input[9] */
1064     TRIG11_OUT_TR_GROUP7_INPUT9     = 0x40000B00u, /* tr_group[7].input[9] */
1065     TRIG11_OUT_TR_GROUP8_INPUT9     = 0x40000B00u, /* tr_group[8].input[9] */
1066     TRIG11_OUT_TR_GROUP0_INPUT10    = 0x40000B01u, /* tr_group[0].input[10] */
1067     TRIG11_OUT_TR_GROUP1_INPUT10    = 0x40000B01u, /* tr_group[1].input[10] */
1068     TRIG11_OUT_TR_GROUP2_INPUT10    = 0x40000B01u, /* tr_group[2].input[10] */
1069     TRIG11_OUT_TR_GROUP3_INPUT10    = 0x40000B01u, /* tr_group[3].input[10] */
1070     TRIG11_OUT_TR_GROUP4_INPUT10    = 0x40000B01u, /* tr_group[4].input[10] */
1071     TRIG11_OUT_TR_GROUP5_INPUT10    = 0x40000B01u, /* tr_group[5].input[10] */
1072     TRIG11_OUT_TR_GROUP6_INPUT10    = 0x40000B01u, /* tr_group[6].input[10] */
1073     TRIG11_OUT_TR_GROUP7_INPUT10    = 0x40000B01u, /* tr_group[7].input[10] */
1074     TRIG11_OUT_TR_GROUP8_INPUT10    = 0x40000B01u, /* tr_group[8].input[10] */
1075     TRIG11_OUT_TR_GROUP0_INPUT11    = 0x40000B02u, /* tr_group[0].input[11] */
1076     TRIG11_OUT_TR_GROUP1_INPUT11    = 0x40000B02u, /* tr_group[1].input[11] */
1077     TRIG11_OUT_TR_GROUP2_INPUT11    = 0x40000B02u, /* tr_group[2].input[11] */
1078     TRIG11_OUT_TR_GROUP3_INPUT11    = 0x40000B02u, /* tr_group[3].input[11] */
1079     TRIG11_OUT_TR_GROUP4_INPUT11    = 0x40000B02u, /* tr_group[4].input[11] */
1080     TRIG11_OUT_TR_GROUP5_INPUT11    = 0x40000B02u, /* tr_group[5].input[11] */
1081     TRIG11_OUT_TR_GROUP6_INPUT11    = 0x40000B02u, /* tr_group[6].input[11] */
1082     TRIG11_OUT_TR_GROUP7_INPUT11    = 0x40000B02u, /* tr_group[7].input[11] */
1083     TRIG11_OUT_TR_GROUP8_INPUT11    = 0x40000B02u, /* tr_group[8].input[11] */
1084     TRIG11_OUT_TR_GROUP0_INPUT12    = 0x40000B03u, /* tr_group[0].input[12] */
1085     TRIG11_OUT_TR_GROUP1_INPUT12    = 0x40000B03u, /* tr_group[1].input[12] */
1086     TRIG11_OUT_TR_GROUP2_INPUT12    = 0x40000B03u, /* tr_group[2].input[12] */
1087     TRIG11_OUT_TR_GROUP3_INPUT12    = 0x40000B03u, /* tr_group[3].input[12] */
1088     TRIG11_OUT_TR_GROUP4_INPUT12    = 0x40000B03u, /* tr_group[4].input[12] */
1089     TRIG11_OUT_TR_GROUP5_INPUT12    = 0x40000B03u, /* tr_group[5].input[12] */
1090     TRIG11_OUT_TR_GROUP6_INPUT12    = 0x40000B03u, /* tr_group[6].input[12] */
1091     TRIG11_OUT_TR_GROUP7_INPUT12    = 0x40000B03u, /* tr_group[7].input[12] */
1092     TRIG11_OUT_TR_GROUP8_INPUT12    = 0x40000B03u, /* tr_group[8].input[12] */
1093     TRIG11_OUT_TR_GROUP0_INPUT13    = 0x40000B04u, /* tr_group[0].input[13] */
1094     TRIG11_OUT_TR_GROUP1_INPUT13    = 0x40000B04u, /* tr_group[1].input[13] */
1095     TRIG11_OUT_TR_GROUP2_INPUT13    = 0x40000B04u, /* tr_group[2].input[13] */
1096     TRIG11_OUT_TR_GROUP3_INPUT13    = 0x40000B04u, /* tr_group[3].input[13] */
1097     TRIG11_OUT_TR_GROUP4_INPUT13    = 0x40000B04u, /* tr_group[4].input[13] */
1098     TRIG11_OUT_TR_GROUP5_INPUT13    = 0x40000B04u, /* tr_group[5].input[13] */
1099     TRIG11_OUT_TR_GROUP6_INPUT13    = 0x40000B04u, /* tr_group[6].input[13] */
1100     TRIG11_OUT_TR_GROUP7_INPUT13    = 0x40000B04u, /* tr_group[7].input[13] */
1101     TRIG11_OUT_TR_GROUP8_INPUT13    = 0x40000B04u, /* tr_group[8].input[13] */
1102     TRIG11_OUT_TR_GROUP0_INPUT14    = 0x40000B05u, /* tr_group[0].input[14] */
1103     TRIG11_OUT_TR_GROUP1_INPUT14    = 0x40000B05u, /* tr_group[1].input[14] */
1104     TRIG11_OUT_TR_GROUP2_INPUT14    = 0x40000B05u, /* tr_group[2].input[14] */
1105     TRIG11_OUT_TR_GROUP3_INPUT14    = 0x40000B05u, /* tr_group[3].input[14] */
1106     TRIG11_OUT_TR_GROUP4_INPUT14    = 0x40000B05u, /* tr_group[4].input[14] */
1107     TRIG11_OUT_TR_GROUP5_INPUT14    = 0x40000B05u, /* tr_group[5].input[14] */
1108     TRIG11_OUT_TR_GROUP6_INPUT14    = 0x40000B05u, /* tr_group[6].input[14] */
1109     TRIG11_OUT_TR_GROUP7_INPUT14    = 0x40000B05u, /* tr_group[7].input[14] */
1110     TRIG11_OUT_TR_GROUP8_INPUT14    = 0x40000B05u, /* tr_group[8].input[14] */
1111     TRIG11_OUT_TR_GROUP0_INPUT15    = 0x40000B06u, /* tr_group[0].input[15] */
1112     TRIG11_OUT_TR_GROUP1_INPUT15    = 0x40000B06u, /* tr_group[1].input[15] */
1113     TRIG11_OUT_TR_GROUP2_INPUT15    = 0x40000B06u, /* tr_group[2].input[15] */
1114     TRIG11_OUT_TR_GROUP3_INPUT15    = 0x40000B06u, /* tr_group[3].input[15] */
1115     TRIG11_OUT_TR_GROUP4_INPUT15    = 0x40000B06u, /* tr_group[4].input[15] */
1116     TRIG11_OUT_TR_GROUP5_INPUT15    = 0x40000B06u, /* tr_group[5].input[15] */
1117     TRIG11_OUT_TR_GROUP6_INPUT15    = 0x40000B06u, /* tr_group[6].input[15] */
1118     TRIG11_OUT_TR_GROUP7_INPUT15    = 0x40000B06u, /* tr_group[7].input[15] */
1119     TRIG11_OUT_TR_GROUP8_INPUT15    = 0x40000B06u, /* tr_group[8].input[15] */
1120     TRIG11_OUT_TR_GROUP0_INPUT16    = 0x40000B07u, /* tr_group[0].input[16] */
1121     TRIG11_OUT_TR_GROUP1_INPUT16    = 0x40000B07u, /* tr_group[1].input[16] */
1122     TRIG11_OUT_TR_GROUP2_INPUT16    = 0x40000B07u, /* tr_group[2].input[16] */
1123     TRIG11_OUT_TR_GROUP3_INPUT16    = 0x40000B07u, /* tr_group[3].input[16] */
1124     TRIG11_OUT_TR_GROUP4_INPUT16    = 0x40000B07u, /* tr_group[4].input[16] */
1125     TRIG11_OUT_TR_GROUP5_INPUT16    = 0x40000B07u, /* tr_group[5].input[16] */
1126     TRIG11_OUT_TR_GROUP6_INPUT16    = 0x40000B07u, /* tr_group[6].input[16] */
1127     TRIG11_OUT_TR_GROUP7_INPUT16    = 0x40000B07u, /* tr_group[7].input[16] */
1128     TRIG11_OUT_TR_GROUP8_INPUT16    = 0x40000B07u, /* tr_group[8].input[16] */
1129     TRIG11_OUT_TR_GROUP0_INPUT17    = 0x40000B08u, /* tr_group[0].input[17] */
1130     TRIG11_OUT_TR_GROUP1_INPUT17    = 0x40000B08u, /* tr_group[1].input[17] */
1131     TRIG11_OUT_TR_GROUP2_INPUT17    = 0x40000B08u, /* tr_group[2].input[17] */
1132     TRIG11_OUT_TR_GROUP3_INPUT17    = 0x40000B08u, /* tr_group[3].input[17] */
1133     TRIG11_OUT_TR_GROUP4_INPUT17    = 0x40000B08u, /* tr_group[4].input[17] */
1134     TRIG11_OUT_TR_GROUP5_INPUT17    = 0x40000B08u, /* tr_group[5].input[17] */
1135     TRIG11_OUT_TR_GROUP6_INPUT17    = 0x40000B08u, /* tr_group[6].input[17] */
1136     TRIG11_OUT_TR_GROUP7_INPUT17    = 0x40000B08u, /* tr_group[7].input[17] */
1137     TRIG11_OUT_TR_GROUP8_INPUT17    = 0x40000B08u, /* tr_group[8].input[17] */
1138     TRIG11_OUT_TR_GROUP0_INPUT18    = 0x40000B09u, /* tr_group[0].input[18] */
1139     TRIG11_OUT_TR_GROUP1_INPUT18    = 0x40000B09u, /* tr_group[1].input[18] */
1140     TRIG11_OUT_TR_GROUP2_INPUT18    = 0x40000B09u, /* tr_group[2].input[18] */
1141     TRIG11_OUT_TR_GROUP3_INPUT18    = 0x40000B09u, /* tr_group[3].input[18] */
1142     TRIG11_OUT_TR_GROUP4_INPUT18    = 0x40000B09u, /* tr_group[4].input[18] */
1143     TRIG11_OUT_TR_GROUP5_INPUT18    = 0x40000B09u, /* tr_group[5].input[18] */
1144     TRIG11_OUT_TR_GROUP6_INPUT18    = 0x40000B09u, /* tr_group[6].input[18] */
1145     TRIG11_OUT_TR_GROUP7_INPUT18    = 0x40000B09u, /* tr_group[7].input[18] */
1146     TRIG11_OUT_TR_GROUP8_INPUT18    = 0x40000B09u, /* tr_group[8].input[18] */
1147     TRIG11_OUT_TR_GROUP0_INPUT19    = 0x40000B0Au, /* tr_group[0].input[19] */
1148     TRIG11_OUT_TR_GROUP1_INPUT19    = 0x40000B0Au, /* tr_group[1].input[19] */
1149     TRIG11_OUT_TR_GROUP2_INPUT19    = 0x40000B0Au, /* tr_group[2].input[19] */
1150     TRIG11_OUT_TR_GROUP3_INPUT19    = 0x40000B0Au, /* tr_group[3].input[19] */
1151     TRIG11_OUT_TR_GROUP4_INPUT19    = 0x40000B0Au, /* tr_group[4].input[19] */
1152     TRIG11_OUT_TR_GROUP5_INPUT19    = 0x40000B0Au, /* tr_group[5].input[19] */
1153     TRIG11_OUT_TR_GROUP6_INPUT19    = 0x40000B0Au, /* tr_group[6].input[19] */
1154     TRIG11_OUT_TR_GROUP7_INPUT19    = 0x40000B0Au, /* tr_group[7].input[19] */
1155     TRIG11_OUT_TR_GROUP8_INPUT19    = 0x40000B0Au, /* tr_group[8].input[19] */
1156     TRIG11_OUT_TR_GROUP0_INPUT20    = 0x40000B0Bu, /* tr_group[0].input[20] */
1157     TRIG11_OUT_TR_GROUP1_INPUT20    = 0x40000B0Bu, /* tr_group[1].input[20] */
1158     TRIG11_OUT_TR_GROUP2_INPUT20    = 0x40000B0Bu, /* tr_group[2].input[20] */
1159     TRIG11_OUT_TR_GROUP3_INPUT20    = 0x40000B0Bu, /* tr_group[3].input[20] */
1160     TRIG11_OUT_TR_GROUP4_INPUT20    = 0x40000B0Bu, /* tr_group[4].input[20] */
1161     TRIG11_OUT_TR_GROUP5_INPUT20    = 0x40000B0Bu, /* tr_group[5].input[20] */
1162     TRIG11_OUT_TR_GROUP6_INPUT20    = 0x40000B0Bu, /* tr_group[6].input[20] */
1163     TRIG11_OUT_TR_GROUP7_INPUT20    = 0x40000B0Bu, /* tr_group[7].input[20] */
1164     TRIG11_OUT_TR_GROUP8_INPUT20    = 0x40000B0Bu, /* tr_group[8].input[20] */
1165     TRIG11_OUT_TR_GROUP0_INPUT21    = 0x40000B0Cu, /* tr_group[0].input[21] */
1166     TRIG11_OUT_TR_GROUP1_INPUT21    = 0x40000B0Cu, /* tr_group[1].input[21] */
1167     TRIG11_OUT_TR_GROUP2_INPUT21    = 0x40000B0Cu, /* tr_group[2].input[21] */
1168     TRIG11_OUT_TR_GROUP3_INPUT21    = 0x40000B0Cu, /* tr_group[3].input[21] */
1169     TRIG11_OUT_TR_GROUP4_INPUT21    = 0x40000B0Cu, /* tr_group[4].input[21] */
1170     TRIG11_OUT_TR_GROUP5_INPUT21    = 0x40000B0Cu, /* tr_group[5].input[21] */
1171     TRIG11_OUT_TR_GROUP6_INPUT21    = 0x40000B0Cu, /* tr_group[6].input[21] */
1172     TRIG11_OUT_TR_GROUP7_INPUT21    = 0x40000B0Cu, /* tr_group[7].input[21] */
1173     TRIG11_OUT_TR_GROUP8_INPUT21    = 0x40000B0Cu, /* tr_group[8].input[21] */
1174     TRIG11_OUT_TR_GROUP0_INPUT22    = 0x40000B0Du, /* tr_group[0].input[22] */
1175     TRIG11_OUT_TR_GROUP1_INPUT22    = 0x40000B0Du, /* tr_group[1].input[22] */
1176     TRIG11_OUT_TR_GROUP2_INPUT22    = 0x40000B0Du, /* tr_group[2].input[22] */
1177     TRIG11_OUT_TR_GROUP3_INPUT22    = 0x40000B0Du, /* tr_group[3].input[22] */
1178     TRIG11_OUT_TR_GROUP4_INPUT22    = 0x40000B0Du, /* tr_group[4].input[22] */
1179     TRIG11_OUT_TR_GROUP5_INPUT22    = 0x40000B0Du, /* tr_group[5].input[22] */
1180     TRIG11_OUT_TR_GROUP6_INPUT22    = 0x40000B0Du, /* tr_group[6].input[22] */
1181     TRIG11_OUT_TR_GROUP7_INPUT22    = 0x40000B0Du, /* tr_group[7].input[22] */
1182     TRIG11_OUT_TR_GROUP8_INPUT22    = 0x40000B0Du, /* tr_group[8].input[22] */
1183     TRIG11_OUT_TR_GROUP0_INPUT23    = 0x40000B0Eu, /* tr_group[0].input[23] */
1184     TRIG11_OUT_TR_GROUP1_INPUT23    = 0x40000B0Eu, /* tr_group[1].input[23] */
1185     TRIG11_OUT_TR_GROUP2_INPUT23    = 0x40000B0Eu, /* tr_group[2].input[23] */
1186     TRIG11_OUT_TR_GROUP3_INPUT23    = 0x40000B0Eu, /* tr_group[3].input[23] */
1187     TRIG11_OUT_TR_GROUP4_INPUT23    = 0x40000B0Eu, /* tr_group[4].input[23] */
1188     TRIG11_OUT_TR_GROUP5_INPUT23    = 0x40000B0Eu, /* tr_group[5].input[23] */
1189     TRIG11_OUT_TR_GROUP6_INPUT23    = 0x40000B0Eu, /* tr_group[6].input[23] */
1190     TRIG11_OUT_TR_GROUP7_INPUT23    = 0x40000B0Eu, /* tr_group[7].input[23] */
1191     TRIG11_OUT_TR_GROUP8_INPUT23    = 0x40000B0Eu, /* tr_group[8].input[23] */
1192     TRIG11_OUT_TR_GROUP0_INPUT24    = 0x40000B0Fu, /* tr_group[0].input[24] */
1193     TRIG11_OUT_TR_GROUP1_INPUT24    = 0x40000B0Fu, /* tr_group[1].input[24] */
1194     TRIG11_OUT_TR_GROUP2_INPUT24    = 0x40000B0Fu, /* tr_group[2].input[24] */
1195     TRIG11_OUT_TR_GROUP3_INPUT24    = 0x40000B0Fu, /* tr_group[3].input[24] */
1196     TRIG11_OUT_TR_GROUP4_INPUT24    = 0x40000B0Fu, /* tr_group[4].input[24] */
1197     TRIG11_OUT_TR_GROUP5_INPUT24    = 0x40000B0Fu, /* tr_group[5].input[24] */
1198     TRIG11_OUT_TR_GROUP6_INPUT24    = 0x40000B0Fu, /* tr_group[6].input[24] */
1199     TRIG11_OUT_TR_GROUP7_INPUT24    = 0x40000B0Fu, /* tr_group[7].input[24] */
1200     TRIG11_OUT_TR_GROUP8_INPUT24    = 0x40000B0Fu /* tr_group[8].input[24] */
1201 } en_trig_output_grp11_t;
1202 
1203 /* Trigger Output Group 12 - Reduces 28 pin input signals to 10 triggers used by all sinks */
1204 typedef enum
1205 {
1206     TRIG12_OUT_TR_GROUP2_INPUT25    = 0x40000C00u, /* tr_group[2].input[25] */
1207     TRIG12_OUT_TR_GROUP3_INPUT25    = 0x40000C00u, /* tr_group[3].input[25] */
1208     TRIG12_OUT_TR_GROUP4_INPUT25    = 0x40000C00u, /* tr_group[4].input[25] */
1209     TRIG12_OUT_TR_GROUP5_INPUT25    = 0x40000C00u, /* tr_group[5].input[25] */
1210     TRIG12_OUT_TR_GROUP6_INPUT25    = 0x40000C00u, /* tr_group[6].input[25] */
1211     TRIG12_OUT_TR_GROUP7_INPUT25    = 0x40000C00u, /* tr_group[7].input[25] */
1212     TRIG12_OUT_TR_GROUP8_INPUT25    = 0x40000C00u, /* tr_group[8].input[25] */
1213     TRIG12_OUT_TR_GROUP2_INPUT26    = 0x40000C01u, /* tr_group[2].input[26] */
1214     TRIG12_OUT_TR_GROUP3_INPUT26    = 0x40000C01u, /* tr_group[3].input[26] */
1215     TRIG12_OUT_TR_GROUP4_INPUT26    = 0x40000C01u, /* tr_group[4].input[26] */
1216     TRIG12_OUT_TR_GROUP5_INPUT26    = 0x40000C01u, /* tr_group[5].input[26] */
1217     TRIG12_OUT_TR_GROUP6_INPUT26    = 0x40000C01u, /* tr_group[6].input[26] */
1218     TRIG12_OUT_TR_GROUP7_INPUT26    = 0x40000C01u, /* tr_group[7].input[26] */
1219     TRIG12_OUT_TR_GROUP8_INPUT26    = 0x40000C01u, /* tr_group[8].input[26] */
1220     TRIG12_OUT_TR_GROUP2_INPUT27    = 0x40000C02u, /* tr_group[2].input[27] */
1221     TRIG12_OUT_TR_GROUP3_INPUT27    = 0x40000C02u, /* tr_group[3].input[27] */
1222     TRIG12_OUT_TR_GROUP4_INPUT27    = 0x40000C02u, /* tr_group[4].input[27] */
1223     TRIG12_OUT_TR_GROUP5_INPUT27    = 0x40000C02u, /* tr_group[5].input[27] */
1224     TRIG12_OUT_TR_GROUP6_INPUT27    = 0x40000C02u, /* tr_group[6].input[27] */
1225     TRIG12_OUT_TR_GROUP7_INPUT27    = 0x40000C02u, /* tr_group[7].input[27] */
1226     TRIG12_OUT_TR_GROUP8_INPUT27    = 0x40000C02u, /* tr_group[8].input[27] */
1227     TRIG12_OUT_TR_GROUP2_INPUT28    = 0x40000C03u, /* tr_group[2].input[28] */
1228     TRIG12_OUT_TR_GROUP3_INPUT28    = 0x40000C03u, /* tr_group[3].input[28] */
1229     TRIG12_OUT_TR_GROUP4_INPUT28    = 0x40000C03u, /* tr_group[4].input[28] */
1230     TRIG12_OUT_TR_GROUP5_INPUT28    = 0x40000C03u, /* tr_group[5].input[28] */
1231     TRIG12_OUT_TR_GROUP6_INPUT28    = 0x40000C03u, /* tr_group[6].input[28] */
1232     TRIG12_OUT_TR_GROUP7_INPUT28    = 0x40000C03u, /* tr_group[7].input[28] */
1233     TRIG12_OUT_TR_GROUP8_INPUT28    = 0x40000C03u, /* tr_group[8].input[28] */
1234     TRIG12_OUT_TR_GROUP2_INPUT29    = 0x40000C04u, /* tr_group[2].input[29] */
1235     TRIG12_OUT_TR_GROUP3_INPUT29    = 0x40000C04u, /* tr_group[3].input[29] */
1236     TRIG12_OUT_TR_GROUP4_INPUT29    = 0x40000C04u, /* tr_group[4].input[29] */
1237     TRIG12_OUT_TR_GROUP5_INPUT29    = 0x40000C04u, /* tr_group[5].input[29] */
1238     TRIG12_OUT_TR_GROUP6_INPUT29    = 0x40000C04u, /* tr_group[6].input[29] */
1239     TRIG12_OUT_TR_GROUP7_INPUT29    = 0x40000C04u, /* tr_group[7].input[29] */
1240     TRIG12_OUT_TR_GROUP8_INPUT29    = 0x40000C04u, /* tr_group[8].input[29] */
1241     TRIG12_OUT_TR_GROUP2_INPUT30    = 0x40000C05u, /* tr_group[2].input[30] */
1242     TRIG12_OUT_TR_GROUP3_INPUT30    = 0x40000C05u, /* tr_group[3].input[30] */
1243     TRIG12_OUT_TR_GROUP4_INPUT30    = 0x40000C05u, /* tr_group[4].input[30] */
1244     TRIG12_OUT_TR_GROUP5_INPUT30    = 0x40000C05u, /* tr_group[5].input[30] */
1245     TRIG12_OUT_TR_GROUP6_INPUT30    = 0x40000C05u, /* tr_group[6].input[30] */
1246     TRIG12_OUT_TR_GROUP7_INPUT30    = 0x40000C05u, /* tr_group[7].input[30] */
1247     TRIG12_OUT_TR_GROUP8_INPUT30    = 0x40000C05u, /* tr_group[8].input[30] */
1248     TRIG12_OUT_TR_GROUP2_INPUT31    = 0x40000C06u, /* tr_group[2].input[31] */
1249     TRIG12_OUT_TR_GROUP3_INPUT31    = 0x40000C06u, /* tr_group[3].input[31] */
1250     TRIG12_OUT_TR_GROUP4_INPUT31    = 0x40000C06u, /* tr_group[4].input[31] */
1251     TRIG12_OUT_TR_GROUP5_INPUT31    = 0x40000C06u, /* tr_group[5].input[31] */
1252     TRIG12_OUT_TR_GROUP6_INPUT31    = 0x40000C06u, /* tr_group[6].input[31] */
1253     TRIG12_OUT_TR_GROUP7_INPUT31    = 0x40000C06u, /* tr_group[7].input[31] */
1254     TRIG12_OUT_TR_GROUP8_INPUT31    = 0x40000C06u, /* tr_group[8].input[31] */
1255     TRIG12_OUT_TR_GROUP2_INPUT32    = 0x40000C07u, /* tr_group[2].input[32] */
1256     TRIG12_OUT_TR_GROUP3_INPUT32    = 0x40000C07u, /* tr_group[3].input[32] */
1257     TRIG12_OUT_TR_GROUP4_INPUT32    = 0x40000C07u, /* tr_group[4].input[32] */
1258     TRIG12_OUT_TR_GROUP5_INPUT32    = 0x40000C07u, /* tr_group[5].input[32] */
1259     TRIG12_OUT_TR_GROUP6_INPUT32    = 0x40000C07u, /* tr_group[6].input[32] */
1260     TRIG12_OUT_TR_GROUP7_INPUT32    = 0x40000C07u, /* tr_group[7].input[32] */
1261     TRIG12_OUT_TR_GROUP8_INPUT32    = 0x40000C07u, /* tr_group[8].input[32] */
1262     TRIG12_OUT_TR_GROUP0_INPUT25    = 0x40000C08u, /* tr_group[0].input[25] */
1263     TRIG12_OUT_TR_GROUP1_INPUT25    = 0x40000C08u, /* tr_group[1].input[25] */
1264     TRIG12_OUT_TR_GROUP0_INPUT26    = 0x40000C09u, /* tr_group[0].input[26] */
1265     TRIG12_OUT_TR_GROUP1_INPUT26    = 0x40000C09u /* tr_group[1].input[26] */
1266 } en_trig_output_grp12_t;
1267 
1268 /* Trigger Output Group 13 - Reduces DMA requests to 16+2 outputs used by all sinks */
1269 typedef enum
1270 {
1271     TRIG13_OUT_TR_GROUP0_INPUT27    = 0x40000D00u, /* tr_group[0].input[27] */
1272     TRIG13_OUT_TR_GROUP1_INPUT27    = 0x40000D00u, /* tr_group[1].input[27] */
1273     TRIG13_OUT_TR_GROUP0_INPUT28    = 0x40000D01u, /* tr_group[0].input[28] */
1274     TRIG13_OUT_TR_GROUP1_INPUT28    = 0x40000D01u, /* tr_group[1].input[28] */
1275     TRIG13_OUT_TR_GROUP0_INPUT29    = 0x40000D02u, /* tr_group[0].input[29] */
1276     TRIG13_OUT_TR_GROUP1_INPUT29    = 0x40000D02u, /* tr_group[1].input[29] */
1277     TRIG13_OUT_TR_GROUP0_INPUT30    = 0x40000D03u, /* tr_group[0].input[30] */
1278     TRIG13_OUT_TR_GROUP1_INPUT30    = 0x40000D03u, /* tr_group[1].input[30] */
1279     TRIG13_OUT_TR_GROUP0_INPUT31    = 0x40000D04u, /* tr_group[0].input[31] */
1280     TRIG13_OUT_TR_GROUP1_INPUT31    = 0x40000D04u, /* tr_group[1].input[31] */
1281     TRIG13_OUT_TR_GROUP0_INPUT32    = 0x40000D05u, /* tr_group[0].input[32] */
1282     TRIG13_OUT_TR_GROUP1_INPUT32    = 0x40000D05u, /* tr_group[1].input[32] */
1283     TRIG13_OUT_TR_GROUP0_INPUT33    = 0x40000D06u, /* tr_group[0].input[33] */
1284     TRIG13_OUT_TR_GROUP1_INPUT33    = 0x40000D06u, /* tr_group[1].input[33] */
1285     TRIG13_OUT_TR_GROUP0_INPUT34    = 0x40000D07u, /* tr_group[0].input[34] */
1286     TRIG13_OUT_TR_GROUP1_INPUT34    = 0x40000D07u, /* tr_group[1].input[34] */
1287     TRIG13_OUT_TR_GROUP0_INPUT35    = 0x40000D08u, /* tr_group[0].input[35] */
1288     TRIG13_OUT_TR_GROUP1_INPUT35    = 0x40000D08u, /* tr_group[1].input[35] */
1289     TRIG13_OUT_TR_GROUP0_INPUT36    = 0x40000D09u, /* tr_group[0].input[36] */
1290     TRIG13_OUT_TR_GROUP1_INPUT36    = 0x40000D09u, /* tr_group[1].input[36] */
1291     TRIG13_OUT_TR_GROUP0_INPUT37    = 0x40000D0Au, /* tr_group[0].input[37] */
1292     TRIG13_OUT_TR_GROUP1_INPUT37    = 0x40000D0Au, /* tr_group[1].input[37] */
1293     TRIG13_OUT_TR_GROUP0_INPUT38    = 0x40000D0Bu, /* tr_group[0].input[38] */
1294     TRIG13_OUT_TR_GROUP1_INPUT38    = 0x40000D0Bu, /* tr_group[1].input[38] */
1295     TRIG13_OUT_TR_GROUP0_INPUT39    = 0x40000D0Cu, /* tr_group[0].input[39] */
1296     TRIG13_OUT_TR_GROUP1_INPUT39    = 0x40000D0Cu, /* tr_group[1].input[39] */
1297     TRIG13_OUT_TR_GROUP0_INPUT40    = 0x40000D0Du, /* tr_group[0].input[40] */
1298     TRIG13_OUT_TR_GROUP1_INPUT40    = 0x40000D0Du, /* tr_group[1].input[40] */
1299     TRIG13_OUT_TR_GROUP0_INPUT41    = 0x40000D0Eu, /* tr_group[0].input[41] */
1300     TRIG13_OUT_TR_GROUP1_INPUT41    = 0x40000D0Eu, /* tr_group[1].input[41] */
1301     TRIG13_OUT_TR_GROUP0_INPUT42    = 0x40000D0Fu, /* tr_group[0].input[42] */
1302     TRIG13_OUT_TR_GROUP1_INPUT42    = 0x40000D0Fu, /* tr_group[1].input[42] */
1303     TRIG13_OUT_TR_GROUP2_INPUT33    = 0x40000D10u, /* tr_group[2].input[33] */
1304     TRIG13_OUT_TR_GROUP3_INPUT33    = 0x40000D10u, /* tr_group[3].input[33] */
1305     TRIG13_OUT_TR_GROUP4_INPUT33    = 0x40000D10u, /* tr_group[4].input[33] */
1306     TRIG13_OUT_TR_GROUP5_INPUT33    = 0x40000D10u, /* tr_group[5].input[33] */
1307     TRIG13_OUT_TR_GROUP6_INPUT33    = 0x40000D10u, /* tr_group[6].input[33] */
1308     TRIG13_OUT_TR_GROUP7_INPUT33    = 0x40000D10u, /* tr_group[7].input[33] */
1309     TRIG13_OUT_TR_GROUP8_INPUT33    = 0x40000D10u, /* tr_group[8].input[33] */
1310     TRIG13_OUT_TR_GROUP2_INPUT34    = 0x40000D11u, /* tr_group[2].input[34] */
1311     TRIG13_OUT_TR_GROUP3_INPUT34    = 0x40000D11u, /* tr_group[3].input[34] */
1312     TRIG13_OUT_TR_GROUP4_INPUT34    = 0x40000D11u, /* tr_group[4].input[34] */
1313     TRIG13_OUT_TR_GROUP5_INPUT34    = 0x40000D11u, /* tr_group[5].input[34] */
1314     TRIG13_OUT_TR_GROUP6_INPUT34    = 0x40000D11u, /* tr_group[6].input[34] */
1315     TRIG13_OUT_TR_GROUP7_INPUT34    = 0x40000D11u, /* tr_group[7].input[34] */
1316     TRIG13_OUT_TR_GROUP8_INPUT34    = 0x40000D11u /* tr_group[8].input[34] */
1317 } en_trig_output_grp13_t;
1318 
1319 /* Trigger Output Group 14 - Reduces general purpose trigger inputs to 8+8 outputs used by all sinks */
1320 typedef enum
1321 {
1322     TRIG14_OUT_TR_GROUP0_INPUT43    = 0x40000E00u, /* tr_group[0].input[43] */
1323     TRIG14_OUT_TR_GROUP1_INPUT43    = 0x40000E00u, /* tr_group[1].input[43] */
1324     TRIG14_OUT_TR_GROUP0_INPUT44    = 0x40000E01u, /* tr_group[0].input[44] */
1325     TRIG14_OUT_TR_GROUP1_INPUT44    = 0x40000E01u, /* tr_group[1].input[44] */
1326     TRIG14_OUT_TR_GROUP0_INPUT45    = 0x40000E02u, /* tr_group[0].input[45] */
1327     TRIG14_OUT_TR_GROUP1_INPUT45    = 0x40000E02u, /* tr_group[1].input[45] */
1328     TRIG14_OUT_TR_GROUP0_INPUT46    = 0x40000E03u, /* tr_group[0].input[46] */
1329     TRIG14_OUT_TR_GROUP1_INPUT46    = 0x40000E03u, /* tr_group[1].input[46] */
1330     TRIG14_OUT_TR_GROUP0_INPUT47    = 0x40000E04u, /* tr_group[0].input[47] */
1331     TRIG14_OUT_TR_GROUP1_INPUT47    = 0x40000E04u, /* tr_group[1].input[47] */
1332     TRIG14_OUT_TR_GROUP0_INPUT48    = 0x40000E05u, /* tr_group[0].input[48] */
1333     TRIG14_OUT_TR_GROUP1_INPUT48    = 0x40000E05u, /* tr_group[1].input[48] */
1334     TRIG14_OUT_TR_GROUP0_INPUT49    = 0x40000E06u, /* tr_group[0].input[49] */
1335     TRIG14_OUT_TR_GROUP1_INPUT49    = 0x40000E06u, /* tr_group[1].input[49] */
1336     TRIG14_OUT_TR_GROUP0_INPUT50    = 0x40000E07u, /* tr_group[0].input[50] */
1337     TRIG14_OUT_TR_GROUP1_INPUT50    = 0x40000E07u, /* tr_group[1].input[50] */
1338     TRIG14_OUT_TR_GROUP2_INPUT35    = 0x40000E08u, /* tr_group[2].input[35] */
1339     TRIG14_OUT_TR_GROUP3_INPUT35    = 0x40000E08u, /* tr_group[3].input[35] */
1340     TRIG14_OUT_TR_GROUP4_INPUT35    = 0x40000E08u, /* tr_group[4].input[35] */
1341     TRIG14_OUT_TR_GROUP5_INPUT35    = 0x40000E08u, /* tr_group[5].input[35] */
1342     TRIG14_OUT_TR_GROUP6_INPUT35    = 0x40000E08u, /* tr_group[6].input[35] */
1343     TRIG14_OUT_TR_GROUP7_INPUT35    = 0x40000E08u, /* tr_group[7].input[35] */
1344     TRIG14_OUT_TR_GROUP8_INPUT35    = 0x40000E08u, /* tr_group[8].input[35] */
1345     TRIG14_OUT_TR_GROUP2_INPUT36    = 0x40000E09u, /* tr_group[2].input[36] */
1346     TRIG14_OUT_TR_GROUP3_INPUT36    = 0x40000E09u, /* tr_group[3].input[36] */
1347     TRIG14_OUT_TR_GROUP4_INPUT36    = 0x40000E09u, /* tr_group[4].input[36] */
1348     TRIG14_OUT_TR_GROUP5_INPUT36    = 0x40000E09u, /* tr_group[5].input[36] */
1349     TRIG14_OUT_TR_GROUP6_INPUT36    = 0x40000E09u, /* tr_group[6].input[36] */
1350     TRIG14_OUT_TR_GROUP7_INPUT36    = 0x40000E09u, /* tr_group[7].input[36] */
1351     TRIG14_OUT_TR_GROUP8_INPUT36    = 0x40000E09u, /* tr_group[8].input[36] */
1352     TRIG14_OUT_TR_GROUP2_INPUT37    = 0x40000E0Au, /* tr_group[2].input[37] */
1353     TRIG14_OUT_TR_GROUP3_INPUT37    = 0x40000E0Au, /* tr_group[3].input[37] */
1354     TRIG14_OUT_TR_GROUP4_INPUT37    = 0x40000E0Au, /* tr_group[4].input[37] */
1355     TRIG14_OUT_TR_GROUP5_INPUT37    = 0x40000E0Au, /* tr_group[5].input[37] */
1356     TRIG14_OUT_TR_GROUP6_INPUT37    = 0x40000E0Au, /* tr_group[6].input[37] */
1357     TRIG14_OUT_TR_GROUP7_INPUT37    = 0x40000E0Au, /* tr_group[7].input[37] */
1358     TRIG14_OUT_TR_GROUP8_INPUT37    = 0x40000E0Au, /* tr_group[8].input[37] */
1359     TRIG14_OUT_TR_GROUP2_INPUT38    = 0x40000E0Bu, /* tr_group[2].input[38] */
1360     TRIG14_OUT_TR_GROUP3_INPUT38    = 0x40000E0Bu, /* tr_group[3].input[38] */
1361     TRIG14_OUT_TR_GROUP4_INPUT38    = 0x40000E0Bu, /* tr_group[4].input[38] */
1362     TRIG14_OUT_TR_GROUP5_INPUT38    = 0x40000E0Bu, /* tr_group[5].input[38] */
1363     TRIG14_OUT_TR_GROUP6_INPUT38    = 0x40000E0Bu, /* tr_group[6].input[38] */
1364     TRIG14_OUT_TR_GROUP7_INPUT38    = 0x40000E0Bu, /* tr_group[7].input[38] */
1365     TRIG14_OUT_TR_GROUP8_INPUT38    = 0x40000E0Bu, /* tr_group[8].input[38] */
1366     TRIG14_OUT_TR_GROUP2_INPUT39    = 0x40000E0Cu, /* tr_group[2].input[39] */
1367     TRIG14_OUT_TR_GROUP3_INPUT39    = 0x40000E0Cu, /* tr_group[3].input[39] */
1368     TRIG14_OUT_TR_GROUP4_INPUT39    = 0x40000E0Cu, /* tr_group[4].input[39] */
1369     TRIG14_OUT_TR_GROUP5_INPUT39    = 0x40000E0Cu, /* tr_group[5].input[39] */
1370     TRIG14_OUT_TR_GROUP6_INPUT39    = 0x40000E0Cu, /* tr_group[6].input[39] */
1371     TRIG14_OUT_TR_GROUP7_INPUT39    = 0x40000E0Cu, /* tr_group[7].input[39] */
1372     TRIG14_OUT_TR_GROUP8_INPUT39    = 0x40000E0Cu, /* tr_group[8].input[39] */
1373     TRIG14_OUT_TR_GROUP2_INPUT40    = 0x40000E0Du, /* tr_group[2].input[40] */
1374     TRIG14_OUT_TR_GROUP3_INPUT40    = 0x40000E0Du, /* tr_group[3].input[40] */
1375     TRIG14_OUT_TR_GROUP4_INPUT40    = 0x40000E0Du, /* tr_group[4].input[40] */
1376     TRIG14_OUT_TR_GROUP5_INPUT40    = 0x40000E0Du, /* tr_group[5].input[40] */
1377     TRIG14_OUT_TR_GROUP6_INPUT40    = 0x40000E0Du, /* tr_group[6].input[40] */
1378     TRIG14_OUT_TR_GROUP7_INPUT40    = 0x40000E0Du, /* tr_group[7].input[40] */
1379     TRIG14_OUT_TR_GROUP8_INPUT40    = 0x40000E0Du, /* tr_group[8].input[40] */
1380     TRIG14_OUT_TR_GROUP2_INPUT41    = 0x40000E0Eu, /* tr_group[2].input[41] */
1381     TRIG14_OUT_TR_GROUP3_INPUT41    = 0x40000E0Eu, /* tr_group[3].input[41] */
1382     TRIG14_OUT_TR_GROUP4_INPUT41    = 0x40000E0Eu, /* tr_group[4].input[41] */
1383     TRIG14_OUT_TR_GROUP5_INPUT41    = 0x40000E0Eu, /* tr_group[5].input[41] */
1384     TRIG14_OUT_TR_GROUP6_INPUT41    = 0x40000E0Eu, /* tr_group[6].input[41] */
1385     TRIG14_OUT_TR_GROUP7_INPUT41    = 0x40000E0Eu, /* tr_group[7].input[41] */
1386     TRIG14_OUT_TR_GROUP8_INPUT41    = 0x40000E0Eu, /* tr_group[8].input[41] */
1387     TRIG14_OUT_TR_GROUP2_INPUT42    = 0x40000E0Fu, /* tr_group[2].input[42] */
1388     TRIG14_OUT_TR_GROUP3_INPUT42    = 0x40000E0Fu, /* tr_group[3].input[42] */
1389     TRIG14_OUT_TR_GROUP4_INPUT42    = 0x40000E0Fu, /* tr_group[4].input[42] */
1390     TRIG14_OUT_TR_GROUP5_INPUT42    = 0x40000E0Fu, /* tr_group[5].input[42] */
1391     TRIG14_OUT_TR_GROUP6_INPUT42    = 0x40000E0Fu, /* tr_group[6].input[42] */
1392     TRIG14_OUT_TR_GROUP7_INPUT42    = 0x40000E0Fu, /* tr_group[7].input[42] */
1393     TRIG14_OUT_TR_GROUP8_INPUT42    = 0x40000E0Fu /* tr_group[8].input[42] */
1394 } en_trig_output_grp14_t;
1395 
1396 /* Level or edge detection setting for a trigger mux */
1397 typedef enum
1398 {
1399     /* The trigger is a simple level output */
1400     TRIGGER_TYPE_LEVEL = 0u,
1401     /* The trigger is synchronized to the consumer blocks clock
1402        and a two cycle pulse is generated on this clock */
1403     TRIGGER_TYPE_EDGE = 1u
1404 } en_trig_type_t;
1405 
1406 /* Trigger Type Defines */
1407 /* AUDIOSS Trigger Types */
1408 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_RX_REQ      TRIGGER_TYPE_LEVEL
1409 #define TRIGGER_TYPE_AUDIOSS_TR_I2S_TX_REQ      TRIGGER_TYPE_LEVEL
1410 #define TRIGGER_TYPE_AUDIOSS_TR_PDM_RX_REQ      TRIGGER_TYPE_LEVEL
1411 /* CPUSS Trigger Types */
1412 #define TRIGGER_TYPE_CPUSS_CTI_TR_IN            TRIGGER_TYPE_EDGE
1413 #define TRIGGER_TYPE_CPUSS_CTI_TR_OUT           TRIGGER_TYPE_EDGE
1414 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL     TRIGGER_TYPE_LEVEL
1415 #define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE      TRIGGER_TYPE_EDGE
1416 #define TRIGGER_TYPE_CPUSS_DW0_TR_OUT           TRIGGER_TYPE_EDGE
1417 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL     TRIGGER_TYPE_LEVEL
1418 #define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE      TRIGGER_TYPE_EDGE
1419 #define TRIGGER_TYPE_CPUSS_DW1_TR_OUT           TRIGGER_TYPE_EDGE
1420 #define TRIGGER_TYPE_CPUSS_TR_FAULT             TRIGGER_TYPE_EDGE
1421 /* CSD Trigger Types */
1422 #define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT         TRIGGER_TYPE_EDGE
1423 /* LPCOMP Trigger Types */
1424 #define TRIGGER_TYPE_LPCOMP_DSI_COMP0           TRIGGER_TYPE_LEVEL
1425 #define TRIGGER_TYPE_LPCOMP_DSI_COMP1           TRIGGER_TYPE_LEVEL
1426 /* PASS Trigger Types */
1427 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL   TRIGGER_TYPE_LEVEL
1428 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE    TRIGGER_TYPE_EDGE
1429 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL   TRIGGER_TYPE_LEVEL
1430 #define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE    TRIGGER_TYPE_EDGE
1431 #define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY        TRIGGER_TYPE_EDGE
1432 #define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL      TRIGGER_TYPE_LEVEL
1433 #define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE       TRIGGER_TYPE_EDGE
1434 #define TRIGGER_TYPE_PASS_TR_SAR_OUT            TRIGGER_TYPE_EDGE
1435 /* PERI Trigger Types */
1436 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL    TRIGGER_TYPE_LEVEL
1437 #define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE     TRIGGER_TYPE_EDGE
1438 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL   TRIGGER_TYPE_LEVEL
1439 #define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE    TRIGGER_TYPE_EDGE
1440 /* PROFILE Trigger Types */
1441 #define TRIGGER_TYPE_PROFILE_TR_START           TRIGGER_TYPE_EDGE
1442 #define TRIGGER_TYPE_PROFILE_TR_STOP            TRIGGER_TYPE_EDGE
1443 /* SCB Trigger Types */
1444 #define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED    TRIGGER_TYPE_LEVEL
1445 #define TRIGGER_TYPE_SCB_TR_RX_REQ              TRIGGER_TYPE_LEVEL
1446 #define TRIGGER_TYPE_SCB_TR_TX_REQ              TRIGGER_TYPE_LEVEL
1447 /* SMIF Trigger Types */
1448 #define TRIGGER_TYPE_SMIF_TR_RX_REQ             TRIGGER_TYPE_LEVEL
1449 #define TRIGGER_TYPE_SMIF_TR_TX_REQ             TRIGGER_TYPE_LEVEL
1450 /* TCPWM Trigger Types */
1451 #define TRIGGER_TYPE_TCPWM_LINE                 TRIGGER_TYPE_LEVEL
1452 #define TRIGGER_TYPE_TCPWM_LINE_COMPL           TRIGGER_TYPE_LEVEL
1453 #define TRIGGER_TYPE_TCPWM_TR_COMPARE_MATCH     TRIGGER_TYPE_EDGE
1454 #define TRIGGER_TYPE_TCPWM_TR_IN__LEVEL         TRIGGER_TYPE_LEVEL
1455 #define TRIGGER_TYPE_TCPWM_TR_IN__EDGE          TRIGGER_TYPE_EDGE
1456 #define TRIGGER_TYPE_TCPWM_TR_OVERFLOW          TRIGGER_TYPE_EDGE
1457 #define TRIGGER_TYPE_TCPWM_TR_UNDERFLOW         TRIGGER_TYPE_EDGE
1458 /* TR_GROUP Trigger Types */
1459 #define TRIGGER_TYPE_TR_GROUP_INPUT__LEVEL      TRIGGER_TYPE_LEVEL
1460 #define TRIGGER_TYPE_TR_GROUP_INPUT__EDGE       TRIGGER_TYPE_EDGE
1461 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__LEVEL     TRIGGER_TYPE_LEVEL
1462 #define TRIGGER_TYPE_TR_GROUP_OUTPUT__EDGE      TRIGGER_TYPE_EDGE
1463 /* UDB Trigger Types */
1464 #define TRIGGER_TYPE_UDB_DSI_OUT_TR__LEVEL      TRIGGER_TYPE_LEVEL
1465 #define TRIGGER_TYPE_UDB_DSI_OUT_TR__EDGE       TRIGGER_TYPE_EDGE
1466 #define TRIGGER_TYPE_UDB_TR_DW_ACK__LEVEL       TRIGGER_TYPE_LEVEL
1467 #define TRIGGER_TYPE_UDB_TR_DW_ACK__EDGE        TRIGGER_TYPE_EDGE
1468 #define TRIGGER_TYPE_UDB_TR_IN__LEVEL           TRIGGER_TYPE_LEVEL
1469 #define TRIGGER_TYPE_UDB_TR_IN__EDGE            TRIGGER_TYPE_EDGE
1470 #define TRIGGER_TYPE_UDB_TR_UDB__LEVEL          TRIGGER_TYPE_LEVEL
1471 #define TRIGGER_TYPE_UDB_TR_UDB__EDGE           TRIGGER_TYPE_EDGE
1472 /* USB Trigger Types */
1473 #define TRIGGER_TYPE_USB_DMA_BURSTEND           TRIGGER_TYPE_EDGE
1474 #define TRIGGER_TYPE_USB_DMA_REQ                TRIGGER_TYPE_EDGE
1475 
1476 /* Fault connections */
1477 typedef enum
1478 {
1479     CPUSS_MPU_VIO_0                 = 0x0000u,
1480     CPUSS_MPU_VIO_1                 = 0x0001u,
1481     CPUSS_MPU_VIO_2                 = 0x0002u,
1482     CPUSS_MPU_VIO_3                 = 0x0003u,
1483     CPUSS_MPU_VIO_14                = 0x000Eu,
1484     CPUSS_MPU_VIO_15                = 0x000Fu,
1485     CPUSS_MPU_VIO_16                = 0x0010u,
1486     PERI_MS_VIO_0                   = 0x001Cu,
1487     PERI_MS_VIO_1                   = 0x001Du,
1488     PERI_MS_VIO_2                   = 0x001Eu,
1489     PERI_MS_VIO_3                   = 0x001Fu,
1490     PERI_GROUP_VIO_0                = 0x0020u,
1491     PERI_GROUP_VIO_1                = 0x0021u,
1492     PERI_GROUP_VIO_2                = 0x0022u,
1493     PERI_GROUP_VIO_3                = 0x0023u,
1494     PERI_GROUP_VIO_4                = 0x0024u,
1495     PERI_GROUP_VIO_6                = 0x0026u,
1496     PERI_GROUP_VIO_9                = 0x0029u,
1497     PERI_GROUP_VIO_10               = 0x002Au,
1498     CPUSS_FLASHC_MAIN_BUS_ERR       = 0x0032u
1499 } en_sysfault_source_t;
1500 
1501 /* Monitor Signal Defines */
1502 typedef enum
1503 {
1504     PROFILE_ONE                     =  0,       /* profile.one */
1505     CPUSS_MONITOR_CM0               =  1,       /* cpuss.monitor_cm0 */
1506     CPUSS_MONITOR_CM4               =  2,       /* cpuss.monitor_cm4 */
1507     CPUSS_MONITOR_FLASH             =  3,       /* cpuss.monitor_flash */
1508     CPUSS_MONITOR_DW0_AHB           =  4,       /* cpuss.monitor_dw0_ahb */
1509     CPUSS_MONITOR_DW1_AHB           =  5,       /* cpuss.monitor_dw1_ahb */
1510     CPUSS_MONITOR_CRYPTO            =  6,       /* cpuss.monitor_crypto */
1511     USB_MONITOR_AHB                 =  7,       /* usb.monitor_ahb */
1512     SCB0_MONITOR_AHB                =  8,       /* scb[0].monitor_ahb */
1513     SCB1_MONITOR_AHB                =  9,       /* scb[1].monitor_ahb */
1514     SCB2_MONITOR_AHB                = 10,       /* scb[2].monitor_ahb */
1515     SCB3_MONITOR_AHB                = 11,       /* scb[3].monitor_ahb */
1516     SCB4_MONITOR_AHB                = 12,       /* scb[4].monitor_ahb */
1517     SCB5_MONITOR_AHB                = 13,       /* scb[5].monitor_ahb */
1518     SCB6_MONITOR_AHB                = 14,       /* scb[6].monitor_ahb */
1519     SCB7_MONITOR_AHB                = 15,       /* scb[7].monitor_ahb */
1520     SCB8_MONITOR_AHB                = 16,       /* scb[8].monitor_ahb */
1521     UDB_MONITOR_UDB0                = 17,       /* udb.monitor_udb[0] */
1522     UDB_MONITOR_UDB1                = 18,       /* udb.monitor_udb[1] */
1523     UDB_MONITOR_UDB2                = 19,       /* udb.monitor_udb[2] */
1524     UDB_MONITOR_UDB3                = 20,       /* udb.monitor_udb[3] */
1525     SMIF_MONITOR_SMIF_SPI_SELECT0   = 21,       /* smif.monitor_smif_spi_select[0] */
1526     SMIF_MONITOR_SMIF_SPI_SELECT1   = 22,       /* smif.monitor_smif_spi_select[1] */
1527     SMIF_MONITOR_SMIF_SPI_SELECT2   = 23,       /* smif.monitor_smif_spi_select[2] */
1528     SMIF_MONITOR_SMIF_SPI_SELECT3   = 24,       /* smif.monitor_smif_spi_select[3] */
1529     SMIF_MONITOR_SMIF_SPI_SELECT_ANY = 25,      /* smif.monitor_smif_spi_select_any */
1530     BLESS_EXT_LNA_RX_CTL_OUT        = 26,       /* bless.ext_lna_rx_ctl_out */
1531     BLESS_EXT_PA_TX_CTL_OUT         = 27        /* bless.ext_pa_tx_ctl_out */
1532 } en_ep_mon_sel_t;
1533 
1534 /* Total count of Energy Profiler monitor signal connections */
1535 #define EP_MONITOR_COUNT                28u
1536 
1537 /* Bus masters */
1538 typedef enum
1539 {
1540     CPUSS_MS_ID_CM0                 =  0,
1541     CPUSS_MS_ID_CRYPTO              =  1,
1542     CPUSS_MS_ID_DW0                 =  2,
1543     CPUSS_MS_ID_DW1                 =  3,
1544     CPUSS_MS_ID_CM4                 = 14,
1545     CPUSS_MS_ID_TC                  = 15
1546 } en_prot_master_t;
1547 
1548 /* Pointer to device configuration structure */
1549 #define CY_DEVICE_CFG                   (&cy_deviceIpBlockCfgPSoC6_01)
1550 
1551 /* Include IP definitions */
1552 #include "ip/cyip_sflash.h"
1553 #include "ip/cyip_peri.h"
1554 #include "ip/cyip_crypto.h"
1555 #include "ip/cyip_cpuss.h"
1556 #include "ip/cyip_fault.h"
1557 #include "ip/cyip_ipc.h"
1558 #include "ip/cyip_prot.h"
1559 #include "ip/cyip_flashc.h"
1560 #include "ip/cyip_srss.h"
1561 #include "ip/cyip_backup.h"
1562 #include "ip/cyip_dw.h"
1563 #include "ip/cyip_efuse.h"
1564 #include "ip/cyip_efuse_data_psoc6_01.h"
1565 #include "ip/cyip_profile.h"
1566 #include "ip/cyip_hsiom.h"
1567 #include "ip/cyip_gpio.h"
1568 #include "ip/cyip_smartio.h"
1569 #include "ip/cyip_udb.h"
1570 #include "ip/cyip_lpcomp.h"
1571 #include "ip/cyip_csd.h"
1572 #include "ip/cyip_tcpwm.h"
1573 #include "ip/cyip_lcd.h"
1574 #include "ip/cyip_ble.h"
1575 #include "ip/cyip_usbfs.h"
1576 #include "ip/cyip_smif.h"
1577 #include "ip/cyip_scb.h"
1578 #include "ip/cyip_ctbm.h"
1579 #include "ip/cyip_ctdac.h"
1580 #include "ip/cyip_sar.h"
1581 #include "ip/cyip_pass.h"
1582 #include "ip/cyip_i2s.h"
1583 #include "ip/cyip_pdm.h"
1584 
1585 /* IP type definitions */
1586 typedef SFLASH_V1_Type SFLASH_Type;
1587 typedef PERI_GR_V1_Type PERI_GR_Type;
1588 typedef PERI_TR_GR_V1_Type PERI_TR_GR_Type;
1589 typedef PERI_PPU_PR_V1_Type PERI_PPU_PR_Type;
1590 typedef PERI_PPU_GR_V1_Type PERI_PPU_GR_Type;
1591 typedef PERI_GR_PPU_SL_V1_Type PERI_GR_PPU_SL_Type;
1592 typedef PERI_GR_PPU_RG_V1_Type PERI_GR_PPU_RG_Type;
1593 typedef PERI_V1_Type PERI_Type;
1594 typedef CRYPTO_V1_Type CRYPTO_Type;
1595 typedef CPUSS_V1_Type CPUSS_Type;
1596 typedef FAULT_STRUCT_V1_Type FAULT_STRUCT_Type;
1597 typedef FAULT_V1_Type FAULT_Type;
1598 typedef IPC_STRUCT_V1_Type IPC_STRUCT_Type;
1599 typedef IPC_INTR_STRUCT_V1_Type IPC_INTR_STRUCT_Type;
1600 typedef IPC_V1_Type IPC_Type;
1601 typedef PROT_SMPU_SMPU_STRUCT_V1_Type PROT_SMPU_SMPU_STRUCT_Type;
1602 typedef PROT_SMPU_V1_Type PROT_SMPU_Type;
1603 typedef PROT_MPU_MPU_STRUCT_V1_Type PROT_MPU_MPU_STRUCT_Type;
1604 typedef PROT_MPU_V1_Type PROT_MPU_Type;
1605 typedef PROT_V1_Type PROT_Type;
1606 typedef FLASHC_FM_CTL_V1_Type FLASHC_FM_CTL_Type;
1607 typedef FLASHC_V1_Type FLASHC_Type;
1608 typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type;
1609 typedef SRSS_V1_Type SRSS_Type;
1610 typedef BACKUP_V1_Type BACKUP_Type;
1611 typedef DW_CH_STRUCT_V1_Type DW_CH_STRUCT_Type;
1612 typedef DW_V1_Type DW_Type;
1613 typedef EFUSE_V1_Type EFUSE_Type;
1614 typedef PROFILE_CNT_STRUCT_V1_Type PROFILE_CNT_STRUCT_Type;
1615 typedef PROFILE_V1_Type PROFILE_Type;
1616 typedef HSIOM_PRT_V1_Type HSIOM_PRT_Type;
1617 typedef HSIOM_V1_Type HSIOM_Type;
1618 typedef GPIO_PRT_V1_Type GPIO_PRT_Type;
1619 typedef GPIO_V1_Type GPIO_Type;
1620 typedef SMARTIO_PRT_V1_Type SMARTIO_PRT_Type;
1621 typedef SMARTIO_V1_Type SMARTIO_Type;
1622 typedef UDB_WRKONE_V1_Type UDB_WRKONE_Type;
1623 typedef UDB_WRKMULT_V1_Type UDB_WRKMULT_Type;
1624 typedef UDB_UDBPAIR_UDBSNG_V1_Type UDB_UDBPAIR_UDBSNG_Type;
1625 typedef UDB_UDBPAIR_ROUTE_V1_Type UDB_UDBPAIR_ROUTE_Type;
1626 typedef UDB_UDBPAIR_V1_Type UDB_UDBPAIR_Type;
1627 typedef UDB_DSI_V1_Type UDB_DSI_Type;
1628 typedef UDB_PA_V1_Type UDB_PA_Type;
1629 typedef UDB_BCTL_V1_Type UDB_BCTL_Type;
1630 typedef UDB_UDBIF_V1_Type UDB_UDBIF_Type;
1631 typedef UDB_V1_Type UDB_Type;
1632 typedef LPCOMP_V1_Type LPCOMP_Type;
1633 typedef CSD_V1_Type CSD_Type;
1634 typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type;
1635 typedef TCPWM_V1_Type TCPWM_Type;
1636 typedef LCD_V1_Type LCD_Type;
1637 typedef BLE_RCB_RCBLL_V1_Type BLE_RCB_RCBLL_Type;
1638 typedef BLE_RCB_V1_Type BLE_RCB_Type;
1639 typedef BLE_BLELL_V1_Type BLE_BLELL_Type;
1640 typedef BLE_BLESS_V1_Type BLE_BLESS_Type;
1641 typedef BLE_V1_Type BLE_Type;
1642 typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type;
1643 typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type;
1644 typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type;
1645 typedef USBFS_V1_Type USBFS_Type;
1646 typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type;
1647 typedef SMIF_V1_Type SMIF_Type;
1648 typedef CySCB_V1_Type CySCB_Type;
1649 typedef CTBM_V1_Type CTBM_Type;
1650 typedef CTDAC_V1_Type CTDAC_Type;
1651 typedef SAR_V1_Type SAR_Type;
1652 typedef PASS_AREF_V1_Type PASS_AREF_Type;
1653 typedef PASS_V1_Type PASS_Type;
1654 typedef I2S_V1_Type I2S_Type;
1655 typedef PDM_V1_Type PDM_Type;
1656 
1657 /* Parameter Defines */
1658 /* I2S capable? (0=No,1=Yes) */
1659 #define AUDIOSS_I2S                     1u
1660 /* PDM capable? (0=No,1=Yes) */
1661 #define AUDIOSS_PDM                     1u
1662 /* UDB present or not ('0': no, '1': yes) */
1663 #define CPUSS_UDB_PRESENT               1u
1664 /* System RAM 0 size in kilobytes */
1665 #define CPUSS_SRAM0_SIZE                288u
1666 /* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System
1667    SRAM0 is implemented with 8 32KB macros. */
1668 #define CPUSS_RAMC0_MACRO_NR            9u
1669 /* System RAM 1 present or not (0=No, 1=Yes) */
1670 #define CPUSS_RAMC1_PRESENT             0u
1671 /* System RAM 1 size in kilobytes */
1672 #define CPUSS_SRAM1_SIZE                32u
1673 /* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System
1674    RAM 1 is implemented with 8 32KB macros. */
1675 #define CPUSS_RAMC1_MACRO_NR            1u
1676 /* System RAM 2 present or not (0=No, 1=Yes) */
1677 #define CPUSS_RAMC2_PRESENT             0u
1678 /* System RAM 2 size in kilobytes */
1679 #define CPUSS_SRAM2_SIZE                256u
1680 /* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System
1681    RAM 2 is implemented with 8 32KB macros. */
1682 #define CPUSS_RAMC2_MACRO_NR            16u
1683 /* System ROM size in KB */
1684 #define CPUSS_ROM_SIZE                  128u
1685 /* Flash main region size in KB */
1686 #define CPUSS_FLASH_SIZE                1024u
1687 /* Flash work region size in KB (EEPROM emulation, data) */
1688 #define CPUSS_WFLASH_SIZE               32u
1689 /* Flash supervisory region size in KB */
1690 #define CPUSS_SFLASH_SIZE               32u
1691 /* Flash data output size (in Bytes) */
1692 #define CPUSS_FLASHC_WORD_SIZE          16u
1693 /* Flash row address width */
1694 #define CPUSS_FLASHC_ROW_ADDR_WIDTH     12u
1695 /* Flash column address width */
1696 #define CPUSS_FLASHC_COL_ADDR_WIDTH     5u
1697 /* Number of external slaves directly connected to slow AHB-Lite infrastructure.
1698    Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
1699    1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
1700    0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK
1701    parameters (for the slaves present) should be derived from the Memory Map. */
1702 #define CPUSS_SLOW_SL_PRESENT           1u
1703 /* Number of external slaves directly connected to fast AHB-Lite infrastructure.
1704    Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits.
1705    1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave
1706    0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK
1707    parameters (for the slaves present) should be derived from the Memory Map. */
1708 #define CPUSS_FAST_SL_PRESENT           1u
1709 /* Number of external masters driving the slow AHB-Lite infrastructure. Maximum
1710    number of masters supported is 2. Width of this parameter is 2-bits. 1-bit
1711    mask for each master indicating present or not. Example: 2'b01 - master 0 is
1712    present. */
1713 #define CPUSS_SLOW_MS_PRESENT           0u
1714 /* Number of total interrupt request inputs to CPUSS */
1715 #define CPUSS_IRQ_NR                    147u
1716 /* Number of DeepSleep wakeup interrupt inputs to CPUSS */
1717 #define CPUSS_DPSLP_IRQ_NR              41u
1718 /* Number of DeepSleep wakeup interrupt inputs to CM0+ (product configuration) */
1719 #define CPUSS_CM0_DPSLP_IRQ_NR          8u
1720 /* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8
1721    levels of priority 8 = 256 levels of priority */
1722 #define CPUSS_CM4_LVL_WIDTH             3u
1723 /* CM4 Floating point unit present or not (0=No, 1=Yes) */
1724 #define CPUSS_CM4_FPU_PRESENT           1u
1725 /* Debug level. Legal range [0,3] */
1726 #define CPUSS_DEBUG_LVL                 3u
1727 /* Trace level. Legal range [0,2] Note: CM4 HTM is not supported. Hence vaule 3
1728    for trace level is not supported in CPUSS. */
1729 #define CPUSS_TRACE_LVL                 2u
1730 /* Embedded Trace Buffer present or not (0=No, 1=Yes) */
1731 #define CPUSS_ETB_PRESENT               0u
1732 /* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
1733 #define CPUSS_MTB_SRAM_SIZE             4u
1734 /* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */
1735 #define CPUSS_ETB_SRAM_SIZE             16u
1736 /* PTM interface present (0=No, 1=Yes) */
1737 #define CPUSS_PTM_PRESENT               1u
1738 /* Width of the PTM interface in bits ([2,32]) */
1739 #define CPUSS_PTM_WIDTH                 8u
1740 /* Width of the TPIU interface in bits ([1,32]) */
1741 #define CPUSS_TPIU_WIDTH                4u
1742 /* CoreSight Part Identification Number */
1743 #define CPUSS_JEPID                     52u
1744 /* CoreSight Part Identification Number */
1745 #define CPUSS_JEPCONTINUATION           0u
1746 /* CoreSight Part Identification Number */
1747 #define CPUSS_FAMILYID                  256u
1748 /* Cryptography IP present or not (0=No, 1=Yes) */
1749 #define CPUSS_CRYPTO_PRESENT            1u
1750 /* DataWire 0 present or not (0=No, 1=Yes) */
1751 #define CPUSS_DW0_PRESENT               1u
1752 /* Number of DataWire 0 channels (8, 16 or 32) */
1753 #define CPUSS_DW0_CH_NR                 16u
1754 /* DataWire 1 present or not (0=No, 1=Yes) */
1755 #define CPUSS_DW1_PRESENT               1u
1756 /* Number of DataWire 1 channels (8, 16 or 32) */
1757 #define CPUSS_DW1_CH_NR                 16u
1758 /* AES cipher support (0 = no support, 1 = support */
1759 #define CPUSS_CRYPTO_AES                1u
1760 /* (Tripple) DES cipher support (0 = no support, 1 = support */
1761 #define CPUSS_CRYPTO_DES                1u
1762 /* Pseudo random number generation support (0 = no support, 1 = support) */
1763 #define CPUSS_CRYPTO_PR                 1u
1764 /* SHA support included */
1765 #define CPUSS_CRYPTO_SHA                1u
1766 /* SHA1 hash support (0 = no support, 1 = support) */
1767 #define CPUSS_CRYPTO_SHA1               1u
1768 /* SHA256 hash support (0 = no support, 1 = support) */
1769 #define CPUSS_CRYPTO_SHA256             1u
1770 /* SHA512 hash support (0 = no support, 1 = support) */
1771 #define CPUSS_CRYPTO_SHA512             1u
1772 /* Cyclic Redundancy Check support (0 = no support, 1 = support) */
1773 #define CPUSS_CRYPTO_CRC                1u
1774 /* Vector unit support (0 = no support, 1 = support) */
1775 #define CPUSS_CRYPTO_VU                 1u
1776 /* True random number generation support (0 = no support, 1 = support) */
1777 #define CPUSS_CRYPTO_TR                 1u
1778 /* String support (0 = no support, 1 = support) */
1779 #define CPUSS_CRYPTO_STR                1u
1780 /* AHB-Lite master interface support (0 = no support, 1 = support) */
1781 #define CPUSS_CRYPTO_MASTER_IF          1u
1782 /* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128,
1783    256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8
1784    kB and 16 kB memory buffer) */
1785 #define CPUSS_CRYPTO_BUFF_SIZE          1024u
1786 /* Number of DataWire controllers present (max 2) */
1787 #define CPUSS_DW_NR                     2u
1788 /* Number of channels in each DataWire controller (must be the same for now) */
1789 #define CPUSS_DW_CH_NR                  16u
1790 /* Number of fault structures. Legal range [1, 4] */
1791 #define CPUSS_FAULT_FAULT_NR            2u
1792 /* Number of Flash BIST_DATA registers */
1793 #define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u
1794 /* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */
1795 #define CPUSS_FLASHC_PA_SIZE            128u
1796 /* Number of IPC structures. Legal range [1, 16] */
1797 #define CPUSS_IPC_IPC_NR                16u
1798 /* Number of IPC interrupt structures. Legal range [1, 16] */
1799 #define CPUSS_IPC_IPC_IRQ_NR            16u
1800 /* Master 0 protect contexts minus one */
1801 #define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u
1802 /* Master 1 protect contexts minus one */
1803 #define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 7u
1804 /* Master 2 protect contexts minus one */
1805 #define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u
1806 /* Master 3 protect contexts minus one */
1807 #define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u
1808 /* Master 4 protect contexts minus one */
1809 #define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u
1810 /* Master 5 protect contexts minus one */
1811 #define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u
1812 /* Master 6 protect contexts minus one */
1813 #define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u
1814 /* Master 7 protect contexts minus one */
1815 #define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u
1816 /* Master 8 protect contexts minus one */
1817 #define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u
1818 /* Master 9 protect contexts minus one */
1819 #define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u
1820 /* Master 10 protect contexts minus one */
1821 #define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u
1822 /* Master 11 protect contexts minus one */
1823 #define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u
1824 /* Master 12 protect contexts minus one */
1825 #define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u
1826 /* Master 13 protect contexts minus one */
1827 #define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u
1828 /* Master 14 protect contexts minus one */
1829 #define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u
1830 /* Master 15 protect contexts minus one */
1831 #define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u
1832 /* Number of SMPU protection structures */
1833 #define CPUSS_PROT_SMPU_STRUCT_NR       16u
1834 /* Number of protection contexts supported minus 1. Legal range [1,16] */
1835 #define CPUSS_SMPU_STRUCT_PC_NR_MINUS1  7u
1836 /* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */
1837 #define EFUSE_EFUSE_NR                  4u
1838 /* Number of GPIO ports in range 0..31 */
1839 #define IOSS_GPIO_GPIO_PORT_NR_0_31     15u
1840 /* Number of GPIO ports in range 32..63 */
1841 #define IOSS_GPIO_GPIO_PORT_NR_32_63    0u
1842 /* Number of GPIO ports in range 64..95 */
1843 #define IOSS_GPIO_GPIO_PORT_NR_64_95    0u
1844 /* Number of GPIO ports in range 96..127 */
1845 #define IOSS_GPIO_GPIO_PORT_NR_96_127   0u
1846 /* Number of ports in device */
1847 #define IOSS_GPIO_GPIO_PORT_NR          15u
1848 /* Number of AMUX splitter cells */
1849 #define IOSS_HSIOM_AMUX_SPLIT_NR        9u
1850 /* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */
1851 #define IOSS_HSIOM_HSIOM_PORT_NR        15u
1852 /* Mask of SMARTIO instances presence */
1853 #define IOSS_SMARTIO_SMARTIO_MASK       768u
1854 /* Number of ports supoprting up to 4 COMs */
1855 #define LCD_NUMPORTS                    8u
1856 /* Number of ports supporting up to 8 COMs */
1857 #define LCD_NUMPORTS8                   8u
1858 /* Number of ports supporting up to 16 COMs */
1859 #define LCD_NUMPORTS16                  0u
1860 /* Max number of LCD commons supported */
1861 #define LCD_CHIP_TOP_COM_NR             8u
1862 /* Max number of LCD pins (total) supported */
1863 #define LCD_CHIP_TOP_PIN_NR             62u
1864 /* Number of IREF outputs from AREF */
1865 #define PASS_NR_IREFS                   4u
1866 /* Number of CTBs in the Subsystem */
1867 #define PASS_NR_CTBS                    1u
1868 /* Number of CTDACs in the Subsystem */
1869 #define PASS_NR_CTDACS                  1u
1870 /* CTB0 Exists */
1871 #define PASS_CTB0_EXISTS                1u
1872 /* CTB1 Exists */
1873 #define PASS_CTB1_EXISTS                0u
1874 /* CTB2 Exists */
1875 #define PASS_CTB2_EXISTS                0u
1876 /* CTB3 Exists */
1877 #define PASS_CTB3_EXISTS                0u
1878 /* CTDAC0 Exists */
1879 #define PASS_CTDAC0_EXISTS              1u
1880 /* CTDAC1 Exists */
1881 #define PASS_CTDAC1_EXISTS              0u
1882 /* CTDAC2 Exists */
1883 #define PASS_CTDAC2_EXISTS              0u
1884 /* CTDAC3 Exists */
1885 #define PASS_CTDAC3_EXISTS              0u
1886 #define PASS_CTBM_CTDAC_PRESENT         1u
1887 /* Number of SAR channels */
1888 #define PASS_SAR_SAR_CHANNELS           16u
1889 /* Averaging logic present in SAR */
1890 #define PASS_SAR_SAR_AVERAGE            1u
1891 /* Range detect logic present in SAR */
1892 #define PASS_SAR_SAR_RANGEDET           1u
1893 /* Support for UAB sampling */
1894 #define PASS_SAR_SAR_UAB                0u
1895 /* The number of protection contexts ([2, 16]). */
1896 #define PERI_PC_NR                      8u
1897 /* Master interface presence mask (4 bits) */
1898 #define PERI_MS_PRESENT                 15u
1899 /* Master interface PPU combinatorial (1) or registerd (0) */
1900 #define PERI_MS_PPU_COMBINATORIAL       1u
1901 /* The number of programmable PPU structures for PERI (all peripherals) */
1902 #define PERI_MS_PPU_PROG_STRUCT_NR      16u
1903 /* Presence of a timeout functionality (1: Yes, 0:No) */
1904 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
1905 /* Slave present (0:No, 1:Yes) */
1906 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 0u
1907 /* Slave present (0:No, 1:Yes) */
1908 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u
1909 /* Slave present (0:No, 1:Yes) */
1910 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u
1911 /* Slave present (0:No, 1:Yes) */
1912 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u
1913 /* Slave present (0:No, 1:Yes) */
1914 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u
1915 /* Slave present (0:No, 1:Yes) */
1916 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u
1917 /* Slave present (0:No, 1:Yes) */
1918 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u
1919 /* Slave present (0:No, 1:Yes) */
1920 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u
1921 /* Slave present (0:No, 1:Yes) */
1922 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u
1923 /* Slave present (0:No, 1:Yes) */
1924 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u
1925 /* Slave present (0:No, 1:Yes) */
1926 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u
1927 /* Slave present (0:No, 1:Yes) */
1928 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u
1929 /* Slave present (0:No, 1:Yes) */
1930 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u
1931 /* Slave present (0:No, 1:Yes) */
1932 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u
1933 /* Slave present (0:No, 1:Yes) */
1934 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u
1935 /* Slave present (0:No, 1:Yes) */
1936 #define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u
1937 /* Presence of a timeout functionality (1: Yes, 0:No) */
1938 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
1939 /* Slave present (0:No, 1:Yes) */
1940 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u
1941 /* Slave present (0:No, 1:Yes) */
1942 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 1u
1943 /* Slave present (0:No, 1:Yes) */
1944 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u
1945 /* Slave present (0:No, 1:Yes) */
1946 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u
1947 /* Slave present (0:No, 1:Yes) */
1948 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u
1949 /* Slave present (0:No, 1:Yes) */
1950 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u
1951 /* Slave present (0:No, 1:Yes) */
1952 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u
1953 /* Slave present (0:No, 1:Yes) */
1954 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u
1955 /* Slave present (0:No, 1:Yes) */
1956 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u
1957 /* Slave present (0:No, 1:Yes) */
1958 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u
1959 /* Slave present (0:No, 1:Yes) */
1960 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u
1961 /* Slave present (0:No, 1:Yes) */
1962 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u
1963 /* Slave present (0:No, 1:Yes) */
1964 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u
1965 /* Slave present (0:No, 1:Yes) */
1966 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u
1967 /* Slave present (0:No, 1:Yes) */
1968 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u
1969 /* Slave present (0:No, 1:Yes) */
1970 #define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u
1971 /* Presence of a timeout functionality (1: Yes, 0:No) */
1972 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u
1973 /* Slave present (0:No, 1:Yes) */
1974 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u
1975 /* Slave present (0:No, 1:Yes) */
1976 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u
1977 /* Slave present (0:No, 1:Yes) */
1978 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u
1979 /* Slave present (0:No, 1:Yes) */
1980 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u
1981 /* Slave present (0:No, 1:Yes) */
1982 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u
1983 /* Slave present (0:No, 1:Yes) */
1984 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 1u
1985 /* Slave present (0:No, 1:Yes) */
1986 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u
1987 /* Slave present (0:No, 1:Yes) */
1988 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u
1989 /* Slave present (0:No, 1:Yes) */
1990 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u
1991 /* Slave present (0:No, 1:Yes) */
1992 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u
1993 /* Slave present (0:No, 1:Yes) */
1994 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 0u
1995 /* Slave present (0:No, 1:Yes) */
1996 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u
1997 /* Slave present (0:No, 1:Yes) */
1998 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u
1999 /* Slave present (0:No, 1:Yes) */
2000 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 1u
2001 /* Slave present (0:No, 1:Yes) */
2002 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2003 /* Slave present (0:No, 1:Yes) */
2004 #define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2005 /* Presence of a timeout functionality (1: Yes, 0:No) */
2006 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2007 /* Slave present (0:No, 1:Yes) */
2008 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u
2009 /* Slave present (0:No, 1:Yes) */
2010 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u
2011 /* Slave present (0:No, 1:Yes) */
2012 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u
2013 /* Slave present (0:No, 1:Yes) */
2014 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 1u
2015 /* Slave present (0:No, 1:Yes) */
2016 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 1u
2017 /* Slave present (0:No, 1:Yes) */
2018 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u
2019 /* Slave present (0:No, 1:Yes) */
2020 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u
2021 /* Slave present (0:No, 1:Yes) */
2022 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2023 /* Slave present (0:No, 1:Yes) */
2024 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u
2025 /* Slave present (0:No, 1:Yes) */
2026 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 1u
2027 /* Slave present (0:No, 1:Yes) */
2028 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 1u
2029 /* Slave present (0:No, 1:Yes) */
2030 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u
2031 /* Slave present (0:No, 1:Yes) */
2032 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 1u
2033 /* Slave present (0:No, 1:Yes) */
2034 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2035 /* Slave present (0:No, 1:Yes) */
2036 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2037 /* Slave present (0:No, 1:Yes) */
2038 #define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2039 /* Presence of a timeout functionality (1: Yes, 0:No) */
2040 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2041 /* Slave present (0:No, 1:Yes) */
2042 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 1u
2043 /* Slave present (0:No, 1:Yes) */
2044 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2045 /* Slave present (0:No, 1:Yes) */
2046 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u
2047 /* Slave present (0:No, 1:Yes) */
2048 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2049 /* Slave present (0:No, 1:Yes) */
2050 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2051 /* Slave present (0:No, 1:Yes) */
2052 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2053 /* Slave present (0:No, 1:Yes) */
2054 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2055 /* Slave present (0:No, 1:Yes) */
2056 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2057 /* Slave present (0:No, 1:Yes) */
2058 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2059 /* Slave present (0:No, 1:Yes) */
2060 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2061 /* Slave present (0:No, 1:Yes) */
2062 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2063 /* Slave present (0:No, 1:Yes) */
2064 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2065 /* Slave present (0:No, 1:Yes) */
2066 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2067 /* Slave present (0:No, 1:Yes) */
2068 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2069 /* Slave present (0:No, 1:Yes) */
2070 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2071 /* Slave present (0:No, 1:Yes) */
2072 #define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2073 /* Presence of a timeout functionality (1: Yes, 0:No) */
2074 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2075 /* Slave present (0:No, 1:Yes) */
2076 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2077 /* Slave present (0:No, 1:Yes) */
2078 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2079 /* Slave present (0:No, 1:Yes) */
2080 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2081 /* Slave present (0:No, 1:Yes) */
2082 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2083 /* Slave present (0:No, 1:Yes) */
2084 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2085 /* Slave present (0:No, 1:Yes) */
2086 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2087 /* Slave present (0:No, 1:Yes) */
2088 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2089 /* Slave present (0:No, 1:Yes) */
2090 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2091 /* Slave present (0:No, 1:Yes) */
2092 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2093 /* Slave present (0:No, 1:Yes) */
2094 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2095 /* Slave present (0:No, 1:Yes) */
2096 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2097 /* Slave present (0:No, 1:Yes) */
2098 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2099 /* Slave present (0:No, 1:Yes) */
2100 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2101 /* Slave present (0:No, 1:Yes) */
2102 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2103 /* Slave present (0:No, 1:Yes) */
2104 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2105 /* Slave present (0:No, 1:Yes) */
2106 #define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2107 /* Presence of a timeout functionality (1: Yes, 0:No) */
2108 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2109 /* Slave present (0:No, 1:Yes) */
2110 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u
2111 /* Slave present (0:No, 1:Yes) */
2112 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u
2113 /* Slave present (0:No, 1:Yes) */
2114 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u
2115 /* Slave present (0:No, 1:Yes) */
2116 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 1u
2117 /* Slave present (0:No, 1:Yes) */
2118 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u
2119 /* Slave present (0:No, 1:Yes) */
2120 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u
2121 /* Slave present (0:No, 1:Yes) */
2122 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u
2123 /* Slave present (0:No, 1:Yes) */
2124 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 1u
2125 /* Slave present (0:No, 1:Yes) */
2126 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 1u
2127 /* Slave present (0:No, 1:Yes) */
2128 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 1u
2129 /* Slave present (0:No, 1:Yes) */
2130 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2131 /* Slave present (0:No, 1:Yes) */
2132 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2133 /* Slave present (0:No, 1:Yes) */
2134 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2135 /* Slave present (0:No, 1:Yes) */
2136 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2137 /* Slave present (0:No, 1:Yes) */
2138 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2139 /* Slave present (0:No, 1:Yes) */
2140 #define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2141 /* Presence of a timeout functionality (1: Yes, 0:No) */
2142 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2143 /* Slave present (0:No, 1:Yes) */
2144 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2145 /* Slave present (0:No, 1:Yes) */
2146 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2147 /* Slave present (0:No, 1:Yes) */
2148 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2149 /* Slave present (0:No, 1:Yes) */
2150 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2151 /* Slave present (0:No, 1:Yes) */
2152 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2153 /* Slave present (0:No, 1:Yes) */
2154 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2155 /* Slave present (0:No, 1:Yes) */
2156 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2157 /* Slave present (0:No, 1:Yes) */
2158 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2159 /* Slave present (0:No, 1:Yes) */
2160 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2161 /* Slave present (0:No, 1:Yes) */
2162 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2163 /* Slave present (0:No, 1:Yes) */
2164 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2165 /* Slave present (0:No, 1:Yes) */
2166 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2167 /* Slave present (0:No, 1:Yes) */
2168 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2169 /* Slave present (0:No, 1:Yes) */
2170 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2171 /* Slave present (0:No, 1:Yes) */
2172 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2173 /* Slave present (0:No, 1:Yes) */
2174 #define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2175 /* Presence of a timeout functionality (1: Yes, 0:No) */
2176 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2177 /* Slave present (0:No, 1:Yes) */
2178 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2179 /* Slave present (0:No, 1:Yes) */
2180 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2181 /* Slave present (0:No, 1:Yes) */
2182 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2183 /* Slave present (0:No, 1:Yes) */
2184 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2185 /* Slave present (0:No, 1:Yes) */
2186 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2187 /* Slave present (0:No, 1:Yes) */
2188 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2189 /* Slave present (0:No, 1:Yes) */
2190 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2191 /* Slave present (0:No, 1:Yes) */
2192 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2193 /* Slave present (0:No, 1:Yes) */
2194 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2195 /* Slave present (0:No, 1:Yes) */
2196 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2197 /* Slave present (0:No, 1:Yes) */
2198 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2199 /* Slave present (0:No, 1:Yes) */
2200 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2201 /* Slave present (0:No, 1:Yes) */
2202 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2203 /* Slave present (0:No, 1:Yes) */
2204 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2205 /* Slave present (0:No, 1:Yes) */
2206 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2207 /* Slave present (0:No, 1:Yes) */
2208 #define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2209 /* Presence of a timeout functionality (1: Yes, 0:No) */
2210 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2211 /* Slave present (0:No, 1:Yes) */
2212 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u
2213 /* Slave present (0:No, 1:Yes) */
2214 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 1u
2215 /* Slave present (0:No, 1:Yes) */
2216 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2217 /* Slave present (0:No, 1:Yes) */
2218 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2219 /* Slave present (0:No, 1:Yes) */
2220 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2221 /* Slave present (0:No, 1:Yes) */
2222 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2223 /* Slave present (0:No, 1:Yes) */
2224 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2225 /* Slave present (0:No, 1:Yes) */
2226 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2227 /* Slave present (0:No, 1:Yes) */
2228 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2229 /* Slave present (0:No, 1:Yes) */
2230 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2231 /* Slave present (0:No, 1:Yes) */
2232 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2233 /* Slave present (0:No, 1:Yes) */
2234 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2235 /* Slave present (0:No, 1:Yes) */
2236 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2237 /* Slave present (0:No, 1:Yes) */
2238 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2239 /* Slave present (0:No, 1:Yes) */
2240 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2241 /* Slave present (0:No, 1:Yes) */
2242 #define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2243 /* Presence of a timeout functionality (1: Yes, 0:No) */
2244 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2245 /* Slave present (0:No, 1:Yes) */
2246 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 1u
2247 /* Slave present (0:No, 1:Yes) */
2248 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 1u
2249 /* Slave present (0:No, 1:Yes) */
2250 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 1u
2251 /* Slave present (0:No, 1:Yes) */
2252 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2253 /* Slave present (0:No, 1:Yes) */
2254 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2255 /* Slave present (0:No, 1:Yes) */
2256 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2257 /* Slave present (0:No, 1:Yes) */
2258 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2259 /* Slave present (0:No, 1:Yes) */
2260 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2261 /* Slave present (0:No, 1:Yes) */
2262 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2263 /* Slave present (0:No, 1:Yes) */
2264 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2265 /* Slave present (0:No, 1:Yes) */
2266 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2267 /* Slave present (0:No, 1:Yes) */
2268 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2269 /* Slave present (0:No, 1:Yes) */
2270 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2271 /* Slave present (0:No, 1:Yes) */
2272 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2273 /* Slave present (0:No, 1:Yes) */
2274 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2275 /* Slave present (0:No, 1:Yes) */
2276 #define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2277 /* Presence of a timeout functionality (1: Yes, 0:No) */
2278 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2279 /* Slave present (0:No, 1:Yes) */
2280 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2281 /* Slave present (0:No, 1:Yes) */
2282 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2283 /* Slave present (0:No, 1:Yes) */
2284 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2285 /* Slave present (0:No, 1:Yes) */
2286 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2287 /* Slave present (0:No, 1:Yes) */
2288 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2289 /* Slave present (0:No, 1:Yes) */
2290 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2291 /* Slave present (0:No, 1:Yes) */
2292 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2293 /* Slave present (0:No, 1:Yes) */
2294 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2295 /* Slave present (0:No, 1:Yes) */
2296 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2297 /* Slave present (0:No, 1:Yes) */
2298 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2299 /* Slave present (0:No, 1:Yes) */
2300 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2301 /* Slave present (0:No, 1:Yes) */
2302 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2303 /* Slave present (0:No, 1:Yes) */
2304 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2305 /* Slave present (0:No, 1:Yes) */
2306 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2307 /* Slave present (0:No, 1:Yes) */
2308 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2309 /* Slave present (0:No, 1:Yes) */
2310 #define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2311 /* Presence of a timeout functionality (1: Yes, 0:No) */
2312 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2313 /* Slave present (0:No, 1:Yes) */
2314 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2315 /* Slave present (0:No, 1:Yes) */
2316 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2317 /* Slave present (0:No, 1:Yes) */
2318 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2319 /* Slave present (0:No, 1:Yes) */
2320 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2321 /* Slave present (0:No, 1:Yes) */
2322 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2323 /* Slave present (0:No, 1:Yes) */
2324 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2325 /* Slave present (0:No, 1:Yes) */
2326 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2327 /* Slave present (0:No, 1:Yes) */
2328 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2329 /* Slave present (0:No, 1:Yes) */
2330 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2331 /* Slave present (0:No, 1:Yes) */
2332 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2333 /* Slave present (0:No, 1:Yes) */
2334 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2335 /* Slave present (0:No, 1:Yes) */
2336 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2337 /* Slave present (0:No, 1:Yes) */
2338 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2339 /* Slave present (0:No, 1:Yes) */
2340 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2341 /* Slave present (0:No, 1:Yes) */
2342 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2343 /* Slave present (0:No, 1:Yes) */
2344 #define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2345 /* Presence of a timeout functionality (1: Yes, 0:No) */
2346 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2347 /* Slave present (0:No, 1:Yes) */
2348 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2349 /* Slave present (0:No, 1:Yes) */
2350 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2351 /* Slave present (0:No, 1:Yes) */
2352 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2353 /* Slave present (0:No, 1:Yes) */
2354 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2355 /* Slave present (0:No, 1:Yes) */
2356 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2357 /* Slave present (0:No, 1:Yes) */
2358 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2359 /* Slave present (0:No, 1:Yes) */
2360 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2361 /* Slave present (0:No, 1:Yes) */
2362 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2363 /* Slave present (0:No, 1:Yes) */
2364 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2365 /* Slave present (0:No, 1:Yes) */
2366 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2367 /* Slave present (0:No, 1:Yes) */
2368 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2369 /* Slave present (0:No, 1:Yes) */
2370 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2371 /* Slave present (0:No, 1:Yes) */
2372 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2373 /* Slave present (0:No, 1:Yes) */
2374 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2375 /* Slave present (0:No, 1:Yes) */
2376 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2377 /* Slave present (0:No, 1:Yes) */
2378 #define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2379 /* Presence of a timeout functionality (1: Yes, 0:No) */
2380 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2381 /* Slave present (0:No, 1:Yes) */
2382 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2383 /* Slave present (0:No, 1:Yes) */
2384 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2385 /* Slave present (0:No, 1:Yes) */
2386 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2387 /* Slave present (0:No, 1:Yes) */
2388 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2389 /* Slave present (0:No, 1:Yes) */
2390 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2391 /* Slave present (0:No, 1:Yes) */
2392 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2393 /* Slave present (0:No, 1:Yes) */
2394 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2395 /* Slave present (0:No, 1:Yes) */
2396 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2397 /* Slave present (0:No, 1:Yes) */
2398 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2399 /* Slave present (0:No, 1:Yes) */
2400 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2401 /* Slave present (0:No, 1:Yes) */
2402 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2403 /* Slave present (0:No, 1:Yes) */
2404 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2405 /* Slave present (0:No, 1:Yes) */
2406 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2407 /* Slave present (0:No, 1:Yes) */
2408 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2409 /* Slave present (0:No, 1:Yes) */
2410 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2411 /* Slave present (0:No, 1:Yes) */
2412 #define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2413 /* Presence of a timeout functionality (1: Yes, 0:No) */
2414 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u
2415 /* Slave present (0:No, 1:Yes) */
2416 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u
2417 /* Slave present (0:No, 1:Yes) */
2418 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u
2419 /* Slave present (0:No, 1:Yes) */
2420 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u
2421 /* Slave present (0:No, 1:Yes) */
2422 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u
2423 /* Slave present (0:No, 1:Yes) */
2424 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u
2425 /* Slave present (0:No, 1:Yes) */
2426 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u
2427 /* Slave present (0:No, 1:Yes) */
2428 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u
2429 /* Slave present (0:No, 1:Yes) */
2430 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u
2431 /* Slave present (0:No, 1:Yes) */
2432 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u
2433 /* Slave present (0:No, 1:Yes) */
2434 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u
2435 /* Slave present (0:No, 1:Yes) */
2436 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u
2437 /* Slave present (0:No, 1:Yes) */
2438 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u
2439 /* Slave present (0:No, 1:Yes) */
2440 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u
2441 /* Slave present (0:No, 1:Yes) */
2442 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u
2443 /* Slave present (0:No, 1:Yes) */
2444 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u
2445 /* Slave present (0:No, 1:Yes) */
2446 #define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u
2447 /* Number of programmable clocks (outputs) */
2448 #define PERI_CLOCK_NR                   59u
2449 /* Number of 8.0 dividers */
2450 #define PERI_DIV_8_NR                   8u
2451 /* Number of 16.0 dividers */
2452 #define PERI_DIV_16_NR                  16u
2453 /* Number of 16.5 (fractional) dividers */
2454 #define PERI_DIV_16_5_NR                4u
2455 /* Number of 24.5 (fractional) dividers */
2456 #define PERI_DIV_24_5_NR                1u
2457 /* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */
2458 #define PERI_DIV_ADDR_WIDTH             4u
2459 /* Trigger module present (0=No, 1=Yes) */
2460 #define PERI_TR                         1u
2461 /* Number of trigger groups */
2462 #define PERI_TR_GROUP_NR                15u
2463 /* The number of protection contexts minus 1 ([1, 15]). */
2464 #define PERI_PPU_FIXED_STRUCT_PC_NR_MINUS1 7u
2465 /* The number of protection contexts minus 1 ([1, 15]). */
2466 #define PERI_PPU_PROG_STRUCT_PC_NR_MINUS1 7u
2467 /* Number of profiling counters. Legal range [1, 32] */
2468 #define PROFILE_PRFL_CNT_NR             8u
2469 /* Number of monitor event signals. Legal range [1, 128] */
2470 #define PROFILE_PRFL_MONITOR_NR         128u
2471 /* DeepSleep support ('0':no, '1': yes) */
2472 #define SCB0_DEEPSLEEP                  0u
2473 /* Externally clocked support? ('0': no, '1': yes) */
2474 #define SCB0_EC                         0u
2475 /* I2C master support? ('0': no, '1': yes) */
2476 #define SCB0_I2C_M                      1u
2477 /* I2C slave support? ('0': no, '1': yes) */
2478 #define SCB0_I2C_S                      1u
2479 /* I2C support? (I2C_M | I2C_S) */
2480 #define SCB0_I2C                        1u
2481 /* I2C glitch filters present? ('0': no, '1': yes) */
2482 #define SCB0_I2C_GLITCH                 1u
2483 /* I2C externally clocked support? ('0': no, '1': yes) */
2484 #define SCB0_I2C_EC                     0u
2485 /* I2C master and slave support? (I2C_M & I2C_S) */
2486 #define SCB0_I2C_M_S                    1u
2487 /* I2C slave with EC? (I2C_S & I2C_EC) */
2488 #define SCB0_I2C_S_EC                   0u
2489 /* SPI master support? ('0': no, '1': yes) */
2490 #define SCB0_SPI_M                      1u
2491 /* SPI slave support? ('0': no, '1': yes) */
2492 #define SCB0_SPI_S                      1u
2493 /* SPI support? (SPI_M | SPI_S) */
2494 #define SCB0_SPI                        1u
2495 /* SPI externally clocked support? ('0': no, '1': yes) */
2496 #define SCB0_SPI_EC                     0u
2497 /* SPI slave with EC? (SPI_S & SPI_EC) */
2498 #define SCB0_SPI_S_EC                   0u
2499 /* UART support? ('0': no, '1': yes) */
2500 #define SCB0_UART                       1u
2501 /* SPI or UART (SPI | UART) */
2502 #define SCB0_SPI_UART                   1u
2503 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2504    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2505    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2506 #define SCB0_EZ_DATA_NR                 256u
2507 /* Command/response mode support? ('0': no, '1': yes) */
2508 #define SCB0_CMD_RESP                   0u
2509 /* EZ mode support? ('0': no, '1': yes) */
2510 #define SCB0_EZ                         0u
2511 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2512 #define SCB0_EZ_CMD_RESP                0u
2513 /* I2C slave with EZ mode (I2C_S & EZ) */
2514 #define SCB0_I2C_S_EZ                   0u
2515 /* SPI slave with EZ mode (SPI_S & EZ) */
2516 #define SCB0_SPI_S_EZ                   0u
2517 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2518 #define SCB0_I2C_FAST_PLUS              1u
2519 /* Number of used spi_select signals (max 4) */
2520 #define SCB0_CHIP_TOP_SPI_SEL_NR        3u
2521 /* DeepSleep support ('0':no, '1': yes) */
2522 #define SCB1_DEEPSLEEP                  0u
2523 /* Externally clocked support? ('0': no, '1': yes) */
2524 #define SCB1_EC                         0u
2525 /* I2C master support? ('0': no, '1': yes) */
2526 #define SCB1_I2C_M                      1u
2527 /* I2C slave support? ('0': no, '1': yes) */
2528 #define SCB1_I2C_S                      1u
2529 /* I2C support? (I2C_M | I2C_S) */
2530 #define SCB1_I2C                        1u
2531 /* I2C glitch filters present? ('0': no, '1': yes) */
2532 #define SCB1_I2C_GLITCH                 1u
2533 /* I2C externally clocked support? ('0': no, '1': yes) */
2534 #define SCB1_I2C_EC                     0u
2535 /* I2C master and slave support? (I2C_M & I2C_S) */
2536 #define SCB1_I2C_M_S                    1u
2537 /* I2C slave with EC? (I2C_S & I2C_EC) */
2538 #define SCB1_I2C_S_EC                   0u
2539 /* SPI master support? ('0': no, '1': yes) */
2540 #define SCB1_SPI_M                      1u
2541 /* SPI slave support? ('0': no, '1': yes) */
2542 #define SCB1_SPI_S                      1u
2543 /* SPI support? (SPI_M | SPI_S) */
2544 #define SCB1_SPI                        1u
2545 /* SPI externally clocked support? ('0': no, '1': yes) */
2546 #define SCB1_SPI_EC                     0u
2547 /* SPI slave with EC? (SPI_S & SPI_EC) */
2548 #define SCB1_SPI_S_EC                   0u
2549 /* UART support? ('0': no, '1': yes) */
2550 #define SCB1_UART                       1u
2551 /* SPI or UART (SPI | UART) */
2552 #define SCB1_SPI_UART                   1u
2553 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2554    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2555    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2556 #define SCB1_EZ_DATA_NR                 256u
2557 /* Command/response mode support? ('0': no, '1': yes) */
2558 #define SCB1_CMD_RESP                   0u
2559 /* EZ mode support? ('0': no, '1': yes) */
2560 #define SCB1_EZ                         0u
2561 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2562 #define SCB1_EZ_CMD_RESP                0u
2563 /* I2C slave with EZ mode (I2C_S & EZ) */
2564 #define SCB1_I2C_S_EZ                   0u
2565 /* SPI slave with EZ mode (SPI_S & EZ) */
2566 #define SCB1_SPI_S_EZ                   0u
2567 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2568 #define SCB1_I2C_FAST_PLUS              1u
2569 /* Number of used spi_select signals (max 4) */
2570 #define SCB1_CHIP_TOP_SPI_SEL_NR        3u
2571 /* DeepSleep support ('0':no, '1': yes) */
2572 #define SCB2_DEEPSLEEP                  0u
2573 /* Externally clocked support? ('0': no, '1': yes) */
2574 #define SCB2_EC                         0u
2575 /* I2C master support? ('0': no, '1': yes) */
2576 #define SCB2_I2C_M                      1u
2577 /* I2C slave support? ('0': no, '1': yes) */
2578 #define SCB2_I2C_S                      1u
2579 /* I2C support? (I2C_M | I2C_S) */
2580 #define SCB2_I2C                        1u
2581 /* I2C glitch filters present? ('0': no, '1': yes) */
2582 #define SCB2_I2C_GLITCH                 1u
2583 /* I2C externally clocked support? ('0': no, '1': yes) */
2584 #define SCB2_I2C_EC                     0u
2585 /* I2C master and slave support? (I2C_M & I2C_S) */
2586 #define SCB2_I2C_M_S                    1u
2587 /* I2C slave with EC? (I2C_S & I2C_EC) */
2588 #define SCB2_I2C_S_EC                   0u
2589 /* SPI master support? ('0': no, '1': yes) */
2590 #define SCB2_SPI_M                      1u
2591 /* SPI slave support? ('0': no, '1': yes) */
2592 #define SCB2_SPI_S                      1u
2593 /* SPI support? (SPI_M | SPI_S) */
2594 #define SCB2_SPI                        1u
2595 /* SPI externally clocked support? ('0': no, '1': yes) */
2596 #define SCB2_SPI_EC                     0u
2597 /* SPI slave with EC? (SPI_S & SPI_EC) */
2598 #define SCB2_SPI_S_EC                   0u
2599 /* UART support? ('0': no, '1': yes) */
2600 #define SCB2_UART                       1u
2601 /* SPI or UART (SPI | UART) */
2602 #define SCB2_SPI_UART                   1u
2603 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2604    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2605    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2606 #define SCB2_EZ_DATA_NR                 256u
2607 /* Command/response mode support? ('0': no, '1': yes) */
2608 #define SCB2_CMD_RESP                   0u
2609 /* EZ mode support? ('0': no, '1': yes) */
2610 #define SCB2_EZ                         0u
2611 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2612 #define SCB2_EZ_CMD_RESP                0u
2613 /* I2C slave with EZ mode (I2C_S & EZ) */
2614 #define SCB2_I2C_S_EZ                   0u
2615 /* SPI slave with EZ mode (SPI_S & EZ) */
2616 #define SCB2_SPI_S_EZ                   0u
2617 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2618 #define SCB2_I2C_FAST_PLUS              1u
2619 /* Number of used spi_select signals (max 4) */
2620 #define SCB2_CHIP_TOP_SPI_SEL_NR        3u
2621 /* DeepSleep support ('0':no, '1': yes) */
2622 #define SCB3_DEEPSLEEP                  0u
2623 /* Externally clocked support? ('0': no, '1': yes) */
2624 #define SCB3_EC                         0u
2625 /* I2C master support? ('0': no, '1': yes) */
2626 #define SCB3_I2C_M                      1u
2627 /* I2C slave support? ('0': no, '1': yes) */
2628 #define SCB3_I2C_S                      1u
2629 /* I2C support? (I2C_M | I2C_S) */
2630 #define SCB3_I2C                        1u
2631 /* I2C glitch filters present? ('0': no, '1': yes) */
2632 #define SCB3_I2C_GLITCH                 1u
2633 /* I2C externally clocked support? ('0': no, '1': yes) */
2634 #define SCB3_I2C_EC                     0u
2635 /* I2C master and slave support? (I2C_M & I2C_S) */
2636 #define SCB3_I2C_M_S                    1u
2637 /* I2C slave with EC? (I2C_S & I2C_EC) */
2638 #define SCB3_I2C_S_EC                   0u
2639 /* SPI master support? ('0': no, '1': yes) */
2640 #define SCB3_SPI_M                      1u
2641 /* SPI slave support? ('0': no, '1': yes) */
2642 #define SCB3_SPI_S                      1u
2643 /* SPI support? (SPI_M | SPI_S) */
2644 #define SCB3_SPI                        1u
2645 /* SPI externally clocked support? ('0': no, '1': yes) */
2646 #define SCB3_SPI_EC                     0u
2647 /* SPI slave with EC? (SPI_S & SPI_EC) */
2648 #define SCB3_SPI_S_EC                   0u
2649 /* UART support? ('0': no, '1': yes) */
2650 #define SCB3_UART                       1u
2651 /* SPI or UART (SPI | UART) */
2652 #define SCB3_SPI_UART                   1u
2653 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2654    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2655    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2656 #define SCB3_EZ_DATA_NR                 256u
2657 /* Command/response mode support? ('0': no, '1': yes) */
2658 #define SCB3_CMD_RESP                   0u
2659 /* EZ mode support? ('0': no, '1': yes) */
2660 #define SCB3_EZ                         0u
2661 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2662 #define SCB3_EZ_CMD_RESP                0u
2663 /* I2C slave with EZ mode (I2C_S & EZ) */
2664 #define SCB3_I2C_S_EZ                   0u
2665 /* SPI slave with EZ mode (SPI_S & EZ) */
2666 #define SCB3_SPI_S_EZ                   0u
2667 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2668 #define SCB3_I2C_FAST_PLUS              1u
2669 /* Number of used spi_select signals (max 4) */
2670 #define SCB3_CHIP_TOP_SPI_SEL_NR        3u
2671 /* DeepSleep support ('0':no, '1': yes) */
2672 #define SCB4_DEEPSLEEP                  0u
2673 /* Externally clocked support? ('0': no, '1': yes) */
2674 #define SCB4_EC                         0u
2675 /* I2C master support? ('0': no, '1': yes) */
2676 #define SCB4_I2C_M                      1u
2677 /* I2C slave support? ('0': no, '1': yes) */
2678 #define SCB4_I2C_S                      1u
2679 /* I2C support? (I2C_M | I2C_S) */
2680 #define SCB4_I2C                        1u
2681 /* I2C glitch filters present? ('0': no, '1': yes) */
2682 #define SCB4_I2C_GLITCH                 1u
2683 /* I2C externally clocked support? ('0': no, '1': yes) */
2684 #define SCB4_I2C_EC                     0u
2685 /* I2C master and slave support? (I2C_M & I2C_S) */
2686 #define SCB4_I2C_M_S                    1u
2687 /* I2C slave with EC? (I2C_S & I2C_EC) */
2688 #define SCB4_I2C_S_EC                   0u
2689 /* SPI master support? ('0': no, '1': yes) */
2690 #define SCB4_SPI_M                      1u
2691 /* SPI slave support? ('0': no, '1': yes) */
2692 #define SCB4_SPI_S                      1u
2693 /* SPI support? (SPI_M | SPI_S) */
2694 #define SCB4_SPI                        1u
2695 /* SPI externally clocked support? ('0': no, '1': yes) */
2696 #define SCB4_SPI_EC                     0u
2697 /* SPI slave with EC? (SPI_S & SPI_EC) */
2698 #define SCB4_SPI_S_EC                   0u
2699 /* UART support? ('0': no, '1': yes) */
2700 #define SCB4_UART                       1u
2701 /* SPI or UART (SPI | UART) */
2702 #define SCB4_SPI_UART                   1u
2703 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2704    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2705    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2706 #define SCB4_EZ_DATA_NR                 256u
2707 /* Command/response mode support? ('0': no, '1': yes) */
2708 #define SCB4_CMD_RESP                   0u
2709 /* EZ mode support? ('0': no, '1': yes) */
2710 #define SCB4_EZ                         0u
2711 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2712 #define SCB4_EZ_CMD_RESP                0u
2713 /* I2C slave with EZ mode (I2C_S & EZ) */
2714 #define SCB4_I2C_S_EZ                   0u
2715 /* SPI slave with EZ mode (SPI_S & EZ) */
2716 #define SCB4_SPI_S_EZ                   0u
2717 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2718 #define SCB4_I2C_FAST_PLUS              1u
2719 /* Number of used spi_select signals (max 4) */
2720 #define SCB4_CHIP_TOP_SPI_SEL_NR        3u
2721 /* DeepSleep support ('0':no, '1': yes) */
2722 #define SCB5_DEEPSLEEP                  0u
2723 /* Externally clocked support? ('0': no, '1': yes) */
2724 #define SCB5_EC                         0u
2725 /* I2C master support? ('0': no, '1': yes) */
2726 #define SCB5_I2C_M                      1u
2727 /* I2C slave support? ('0': no, '1': yes) */
2728 #define SCB5_I2C_S                      1u
2729 /* I2C support? (I2C_M | I2C_S) */
2730 #define SCB5_I2C                        1u
2731 /* I2C glitch filters present? ('0': no, '1': yes) */
2732 #define SCB5_I2C_GLITCH                 1u
2733 /* I2C externally clocked support? ('0': no, '1': yes) */
2734 #define SCB5_I2C_EC                     0u
2735 /* I2C master and slave support? (I2C_M & I2C_S) */
2736 #define SCB5_I2C_M_S                    1u
2737 /* I2C slave with EC? (I2C_S & I2C_EC) */
2738 #define SCB5_I2C_S_EC                   0u
2739 /* SPI master support? ('0': no, '1': yes) */
2740 #define SCB5_SPI_M                      1u
2741 /* SPI slave support? ('0': no, '1': yes) */
2742 #define SCB5_SPI_S                      1u
2743 /* SPI support? (SPI_M | SPI_S) */
2744 #define SCB5_SPI                        1u
2745 /* SPI externally clocked support? ('0': no, '1': yes) */
2746 #define SCB5_SPI_EC                     0u
2747 /* SPI slave with EC? (SPI_S & SPI_EC) */
2748 #define SCB5_SPI_S_EC                   0u
2749 /* UART support? ('0': no, '1': yes) */
2750 #define SCB5_UART                       1u
2751 /* SPI or UART (SPI | UART) */
2752 #define SCB5_SPI_UART                   1u
2753 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2754    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2755    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2756 #define SCB5_EZ_DATA_NR                 256u
2757 /* Command/response mode support? ('0': no, '1': yes) */
2758 #define SCB5_CMD_RESP                   0u
2759 /* EZ mode support? ('0': no, '1': yes) */
2760 #define SCB5_EZ                         0u
2761 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2762 #define SCB5_EZ_CMD_RESP                0u
2763 /* I2C slave with EZ mode (I2C_S & EZ) */
2764 #define SCB5_I2C_S_EZ                   0u
2765 /* SPI slave with EZ mode (SPI_S & EZ) */
2766 #define SCB5_SPI_S_EZ                   0u
2767 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2768 #define SCB5_I2C_FAST_PLUS              1u
2769 /* Number of used spi_select signals (max 4) */
2770 #define SCB5_CHIP_TOP_SPI_SEL_NR        3u
2771 /* DeepSleep support ('0':no, '1': yes) */
2772 #define SCB6_DEEPSLEEP                  0u
2773 /* Externally clocked support? ('0': no, '1': yes) */
2774 #define SCB6_EC                         0u
2775 /* I2C master support? ('0': no, '1': yes) */
2776 #define SCB6_I2C_M                      1u
2777 /* I2C slave support? ('0': no, '1': yes) */
2778 #define SCB6_I2C_S                      1u
2779 /* I2C support? (I2C_M | I2C_S) */
2780 #define SCB6_I2C                        1u
2781 /* I2C glitch filters present? ('0': no, '1': yes) */
2782 #define SCB6_I2C_GLITCH                 1u
2783 /* I2C externally clocked support? ('0': no, '1': yes) */
2784 #define SCB6_I2C_EC                     0u
2785 /* I2C master and slave support? (I2C_M & I2C_S) */
2786 #define SCB6_I2C_M_S                    1u
2787 /* I2C slave with EC? (I2C_S & I2C_EC) */
2788 #define SCB6_I2C_S_EC                   0u
2789 /* SPI master support? ('0': no, '1': yes) */
2790 #define SCB6_SPI_M                      1u
2791 /* SPI slave support? ('0': no, '1': yes) */
2792 #define SCB6_SPI_S                      1u
2793 /* SPI support? (SPI_M | SPI_S) */
2794 #define SCB6_SPI                        1u
2795 /* SPI externally clocked support? ('0': no, '1': yes) */
2796 #define SCB6_SPI_EC                     0u
2797 /* SPI slave with EC? (SPI_S & SPI_EC) */
2798 #define SCB6_SPI_S_EC                   0u
2799 /* UART support? ('0': no, '1': yes) */
2800 #define SCB6_UART                       1u
2801 /* SPI or UART (SPI | UART) */
2802 #define SCB6_SPI_UART                   1u
2803 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2804    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2805    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2806 #define SCB6_EZ_DATA_NR                 256u
2807 /* Command/response mode support? ('0': no, '1': yes) */
2808 #define SCB6_CMD_RESP                   0u
2809 /* EZ mode support? ('0': no, '1': yes) */
2810 #define SCB6_EZ                         0u
2811 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2812 #define SCB6_EZ_CMD_RESP                0u
2813 /* I2C slave with EZ mode (I2C_S & EZ) */
2814 #define SCB6_I2C_S_EZ                   0u
2815 /* SPI slave with EZ mode (SPI_S & EZ) */
2816 #define SCB6_SPI_S_EZ                   0u
2817 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2818 #define SCB6_I2C_FAST_PLUS              1u
2819 /* Number of used spi_select signals (max 4) */
2820 #define SCB6_CHIP_TOP_SPI_SEL_NR        3u
2821 /* DeepSleep support ('0':no, '1': yes) */
2822 #define SCB7_DEEPSLEEP                  0u
2823 /* Externally clocked support? ('0': no, '1': yes) */
2824 #define SCB7_EC                         0u
2825 /* I2C master support? ('0': no, '1': yes) */
2826 #define SCB7_I2C_M                      1u
2827 /* I2C slave support? ('0': no, '1': yes) */
2828 #define SCB7_I2C_S                      1u
2829 /* I2C support? (I2C_M | I2C_S) */
2830 #define SCB7_I2C                        1u
2831 /* I2C glitch filters present? ('0': no, '1': yes) */
2832 #define SCB7_I2C_GLITCH                 1u
2833 /* I2C externally clocked support? ('0': no, '1': yes) */
2834 #define SCB7_I2C_EC                     0u
2835 /* I2C master and slave support? (I2C_M & I2C_S) */
2836 #define SCB7_I2C_M_S                    1u
2837 /* I2C slave with EC? (I2C_S & I2C_EC) */
2838 #define SCB7_I2C_S_EC                   0u
2839 /* SPI master support? ('0': no, '1': yes) */
2840 #define SCB7_SPI_M                      1u
2841 /* SPI slave support? ('0': no, '1': yes) */
2842 #define SCB7_SPI_S                      1u
2843 /* SPI support? (SPI_M | SPI_S) */
2844 #define SCB7_SPI                        1u
2845 /* SPI externally clocked support? ('0': no, '1': yes) */
2846 #define SCB7_SPI_EC                     0u
2847 /* SPI slave with EC? (SPI_S & SPI_EC) */
2848 #define SCB7_SPI_S_EC                   0u
2849 /* UART support? ('0': no, '1': yes) */
2850 #define SCB7_UART                       1u
2851 /* SPI or UART (SPI | UART) */
2852 #define SCB7_SPI_UART                   1u
2853 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2854    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2855    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2856 #define SCB7_EZ_DATA_NR                 256u
2857 /* Command/response mode support? ('0': no, '1': yes) */
2858 #define SCB7_CMD_RESP                   0u
2859 /* EZ mode support? ('0': no, '1': yes) */
2860 #define SCB7_EZ                         0u
2861 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2862 #define SCB7_EZ_CMD_RESP                0u
2863 /* I2C slave with EZ mode (I2C_S & EZ) */
2864 #define SCB7_I2C_S_EZ                   0u
2865 /* SPI slave with EZ mode (SPI_S & EZ) */
2866 #define SCB7_SPI_S_EZ                   0u
2867 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2868 #define SCB7_I2C_FAST_PLUS              1u
2869 /* Number of used spi_select signals (max 4) */
2870 #define SCB7_CHIP_TOP_SPI_SEL_NR        3u
2871 /* DeepSleep support ('0':no, '1': yes) */
2872 #define SCB8_DEEPSLEEP                  1u
2873 /* Externally clocked support? ('0': no, '1': yes) */
2874 #define SCB8_EC                         1u
2875 /* I2C master support? ('0': no, '1': yes) */
2876 #define SCB8_I2C_M                      0u
2877 /* I2C slave support? ('0': no, '1': yes) */
2878 #define SCB8_I2C_S                      1u
2879 /* I2C support? (I2C_M | I2C_S) */
2880 #define SCB8_I2C                        1u
2881 /* I2C glitch filters present? ('0': no, '1': yes) */
2882 #define SCB8_I2C_GLITCH                 1u
2883 /* I2C externally clocked support? ('0': no, '1': yes) */
2884 #define SCB8_I2C_EC                     1u
2885 /* I2C master and slave support? (I2C_M & I2C_S) */
2886 #define SCB8_I2C_M_S                    0u
2887 /* I2C slave with EC? (I2C_S & I2C_EC) */
2888 #define SCB8_I2C_S_EC                   1u
2889 /* SPI master support? ('0': no, '1': yes) */
2890 #define SCB8_SPI_M                      0u
2891 /* SPI slave support? ('0': no, '1': yes) */
2892 #define SCB8_SPI_S                      1u
2893 /* SPI support? (SPI_M | SPI_S) */
2894 #define SCB8_SPI                        1u
2895 /* SPI externally clocked support? ('0': no, '1': yes) */
2896 #define SCB8_SPI_EC                     1u
2897 /* SPI slave with EC? (SPI_S & SPI_EC) */
2898 #define SCB8_SPI_S_EC                   1u
2899 /* UART support? ('0': no, '1': yes) */
2900 #define SCB8_UART                       0u
2901 /* SPI or UART (SPI | UART) */
2902 #define SCB8_SPI_UART                   1u
2903 /* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode,
2904    CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only
2905    256 B are used. This is because the EZ mode uses 8-bit addresses. */
2906 #define SCB8_EZ_DATA_NR                 256u
2907 /* Command/response mode support? ('0': no, '1': yes) */
2908 #define SCB8_CMD_RESP                   1u
2909 /* EZ mode support? ('0': no, '1': yes) */
2910 #define SCB8_EZ                         1u
2911 /* Command/response mode or EZ mode support? (CMD_RESP | EZ) */
2912 #define SCB8_EZ_CMD_RESP                1u
2913 /* I2C slave with EZ mode (I2C_S & EZ) */
2914 #define SCB8_I2C_S_EZ                   1u
2915 /* SPI slave with EZ mode (SPI_S & EZ) */
2916 #define SCB8_SPI_S_EZ                   1u
2917 /* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */
2918 #define SCB8_I2C_FAST_PLUS              1u
2919 /* Number of used spi_select signals (max 4) */
2920 #define SCB8_CHIP_TOP_SPI_SEL_NR        1u
2921 /* SONOS Flash is used or not ('0': no, '1': yes) */
2922 #define SFLASH_FLASHC_IS_SONOS          1u
2923 /* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */
2924 #define SFLASH_CPUSS_WOUNDING_PRESENT   1u
2925 /* Number of AHB-Lite "hmaster[]" bits ([1, 8]) */
2926 #define SMIF_MASTER_WIDTH               8u
2927 /* Base address of the SMIF XIP memory region. This address must be a multiple of
2928    the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This
2929    address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP
2930    memory region should NOT overlap with other memory regions. */
2931 #define SMIF_SMIF_XIP_ADDR              0x18000000u
2932 /* Capacity of the SMIF XIP memory region. The more significant bits of this
2933    parameter must be '1' and the lesser significant bits of this paramter must
2934    be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are
2935    {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000,
2936    0xffe0:0000, ..., 0xe000:0000}. */
2937 #define SMIF_SMIF_XIP_MASK              0xF8000000u
2938 /* Cryptography (AES) support ('0' = no support, '1' = support) */
2939 #define SMIF_CRYPTO                     1u
2940 /* Number of external devices supported ([1,4]) */
2941 #define SMIF_DEVICE_NR                  4u
2942 /* External device write support. This is a 4-bit field. Each external device has
2943    a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */
2944 #define SMIF_DEVICE_WR_EN               15u
2945 /* Chip top connect all 8 data pins (0= connect 4 data pins, 1= connect 8 data
2946    pins) */
2947 #define SMIF_CHIP_TOP_DATA8_PRESENT     1u
2948 /* Number of used spi_select signals (max 4) */
2949 #define SMIF_CHIP_TOP_SPI_SEL_NR        4u
2950 /* Number of regulator modules instantiated within SRSS */
2951 #define SRSS_NUM_ACTREG_PWRMOD          2u
2952 /* Number of shorting switches between vccd and vccact */
2953 #define SRSS_NUM_ACTIVE_SWITCH          3u
2954 /* ULP linear regulator system is present */
2955 #define SRSS_ULPLINREG_PRESENT          1u
2956 /* HT linear regulator system is present */
2957 #define SRSS_HTLINREG_PRESENT           0u
2958 /* SIMO buck core regulator is present. Only compatible with ULP linear regulator
2959    system (ULPLINREG_PRESENT==1). */
2960 #define SRSS_SIMOBUCK_PRESENT           1u
2961 /* Precision ILO (PILO) is present */
2962 #define SRSS_PILO_PRESENT               1u
2963 /* External Crystal Oscillator is present (high frequency) */
2964 #define SRSS_ECO_PRESENT                1u
2965 /* System Buck-Boost is present */
2966 #define SRSS_SYSBB_PRESENT              0u
2967 /* Number of clock paths. Must be > 0 */
2968 #define SRSS_NUM_CLKPATH                5u
2969 /* Number of PLLs present. Must be <= NUM_CLKPATH */
2970 #define SRSS_NUM_PLL                    1u
2971 /* Number of HFCLK roots present. Must be > 0 */
2972 #define SRSS_NUM_HFROOT                 5u
2973 /* Number of PWR_HIB_DATA registers */
2974 #define SRSS_NUM_HIBDATA                1u
2975 /* Backup domain is present */
2976 #define SRSS_BACKUP_PRESENT             1u
2977 /* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of
2978    mask indicates presence of a CSV. */
2979 #define SRSS_MASK_HFCSV                 0u
2980 /* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */
2981 #define SRSS_WCOCSV_PRESENT             0u
2982 /* Number of software watchdog timers. */
2983 #define SRSS_NUM_MCWDT                  2u
2984 /* Number of DSI inputs into clock muxes. This is used for logic optimization. */
2985 #define SRSS_NUM_DSI                    2u
2986 /* Alternate high-frequency clock is present. This is used for logic optimization. */
2987 #define SRSS_ALTHF_PRESENT              1u
2988 /* Alternate low-frequency clock is present. This is used for logic optimization. */
2989 #define SRSS_ALTLF_PRESENT              0u
2990 /* Use the hardened clkactfllmux block */
2991 #define SRSS_USE_HARD_CLKACTFLLMUX      1u
2992 /* Number of clock paths, including direct paths in hardened clkactfllmux block
2993    (Must be >= NUM_CLKPATH) */
2994 #define SRSS_HARD_CLKPATH               6u
2995 /* Number of clock paths with muxes in hardened clkactfllmux block (Must be >=
2996    NUM_PLL+1) */
2997 #define SRSS_HARD_CLKPATHMUX            6u
2998 /* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */
2999 #define SRSS_HARD_HFROOT                6u
3000 /* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */
3001 #define SRSS_HARD_ECOMUX_PRESENT        1u
3002 /* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */
3003 #define SRSS_HARD_ALTHFMUX_PRESENT      1u
3004 /* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT
3005    or SIMOBUCK_PRESENT. */
3006 #define SRSS_BUCKCTL_PRESENT            1u
3007 /* Low-current SISO buck core regulator is present. Only compatible with ULP
3008    linear regulator system (ULPLINREG_PRESENT==1). */
3009 #define SRSS_S40S_SISOBUCKLC_PRESENT    0u
3010 /* Backup memory is present (only used when BACKUP_PRESENT==1) */
3011 #define SRSS_BACKUP_BMEM_PRESENT        0u
3012 /* Number of Backup registers to include (each is 32b). Only used when
3013    BACKUP_PRESENT==1. */
3014 #define SRSS_BACKUP_NUM_BREG            16u
3015 /* Number of counters per IP (1..8) */
3016 #define TCPWM0_CNT_NR                   8u
3017 /* Counter width (in number of bits) */
3018 #define TCPWM0_CNT_CNT_WIDTH            32u
3019 /* Number of counters per IP (1..8) */
3020 #define TCPWM1_CNT_NR                   24u
3021 /* Counter width (in number of bits) */
3022 #define TCPWM1_CNT_CNT_WIDTH            16u
3023 /* Number of UDB Interrupts */
3024 #define UDB_NUMINT                      16u
3025 /* Number of triggers */
3026 #define UDB_NUMTR                       16u
3027 /* Number of UDB array rows (must be multiple of 2) */
3028 #define UDB_NUMROW                      2u
3029 /* Number of UDB array columns */
3030 #define UDB_NUMCOL                      6u
3031 /* DSI on bottom (1) or on bottom and top (2) of UDB array */
3032 #define UDB_DSISIDES                    2u
3033 /* Number of UDBs = NUMROW * NUMCOL */
3034 #define UDB_NUMUDB                      12u
3035 /* Number of UDB pairs = NUMUDB / 2 */
3036 #define UDB_NUMUDBPAIR                  6u
3037 /* Number of DSIs = NUMCOL * DSISIDES */
3038 #define UDB_NUMDSI                      12u
3039 /* Number of quad clocks */
3040 #define UDB_NUMQCLK                     3u
3041 
3042 /* MMIO Targets Defines */
3043 /* MMIO1.CRYPTO */
3044 #define CY_MMIO_CRYPTO_GROUP_NR         1u
3045 #define CY_MMIO_CRYPTO_SLAVE_NR         1u
3046 /* MMIO2.CPUSS */
3047 #define CY_MMIO_CPUSS_GROUP_NR          2u
3048 #define CY_MMIO_CPUSS_SLAVE_NR          1u
3049 /* MMIO2.FAULT */
3050 #define CY_MMIO_FAULT_GROUP_NR          2u
3051 #define CY_MMIO_FAULT_SLAVE_NR          2u
3052 /* MMIO2.IPC */
3053 #define CY_MMIO_IPC_GROUP_NR            2u
3054 #define CY_MMIO_IPC_SLAVE_NR            3u
3055 /* MMIO2.PROT */
3056 #define CY_MMIO_PROT_GROUP_NR           2u
3057 #define CY_MMIO_PROT_SLAVE_NR           4u
3058 /* MMIO2.FLASHC */
3059 #define CY_MMIO_FLASHC_GROUP_NR         2u
3060 #define CY_MMIO_FLASHC_SLAVE_NR         5u
3061 /* MMIO2.SRSS */
3062 #define CY_MMIO_SRSS_GROUP_NR           2u
3063 #define CY_MMIO_SRSS_SLAVE_NR           6u
3064 /* MMIO2.BACKUP */
3065 #define CY_MMIO_BACKUP_GROUP_NR         2u
3066 #define CY_MMIO_BACKUP_SLAVE_NR         7u
3067 /* MMIO2.DW */
3068 #define CY_MMIO_DW_GROUP_NR             2u
3069 #define CY_MMIO_DW_SLAVE_NR             8u
3070 /* MMIO2.EFUSE */
3071 #define CY_MMIO_EFUSE_GROUP_NR          2u
3072 #define CY_MMIO_EFUSE_SLAVE_NR          12u
3073 /* MMIO2.PROFILE */
3074 #define CY_MMIO_PROFILE_GROUP_NR        2u
3075 #define CY_MMIO_PROFILE_SLAVE_NR        13u
3076 /* MMIO3.HSIOM */
3077 #define CY_MMIO_HSIOM_GROUP_NR          3u
3078 #define CY_MMIO_HSIOM_SLAVE_NR          1u
3079 /* MMIO3.GPIO */
3080 #define CY_MMIO_GPIO_GROUP_NR           3u
3081 #define CY_MMIO_GPIO_SLAVE_NR           2u
3082 /* MMIO3.SMARTIO */
3083 #define CY_MMIO_SMARTIO_GROUP_NR        3u
3084 #define CY_MMIO_SMARTIO_SLAVE_NR        3u
3085 /* MMIO3.UDB */
3086 #define CY_MMIO_UDB_GROUP_NR            3u
3087 #define CY_MMIO_UDB_SLAVE_NR            4u
3088 /* MMIO3.LPCOMP */
3089 #define CY_MMIO_LPCOMP_GROUP_NR         3u
3090 #define CY_MMIO_LPCOMP_SLAVE_NR         5u
3091 /* MMIO3.CSD0 */
3092 #define CY_MMIO_CSD0_GROUP_NR           3u
3093 #define CY_MMIO_CSD0_SLAVE_NR           6u
3094 /* MMIO3.TCPWM0 */
3095 #define CY_MMIO_TCPWM0_GROUP_NR         3u
3096 #define CY_MMIO_TCPWM0_SLAVE_NR         8u
3097 /* MMIO3.TCPWM1 */
3098 #define CY_MMIO_TCPWM1_GROUP_NR         3u
3099 #define CY_MMIO_TCPWM1_SLAVE_NR         9u
3100 /* MMIO3.LCD0 */
3101 #define CY_MMIO_LCD0_GROUP_NR           3u
3102 #define CY_MMIO_LCD0_SLAVE_NR           10u
3103 /* MMIO3.BLE */
3104 #define CY_MMIO_BLE_GROUP_NR            3u
3105 #define CY_MMIO_BLE_SLAVE_NR            11u
3106 /* MMIO3.USBFS0 */
3107 #define CY_MMIO_USBFS0_GROUP_NR         3u
3108 #define CY_MMIO_USBFS0_SLAVE_NR         12u
3109 /* MMIO4.SMIF0 */
3110 #define CY_MMIO_SMIF0_GROUP_NR          4u
3111 #define CY_MMIO_SMIF0_SLAVE_NR          2u
3112 /* MMIO6.SCB0 */
3113 #define CY_MMIO_SCB0_GROUP_NR           6u
3114 #define CY_MMIO_SCB0_SLAVE_NR           1u
3115 /* MMIO6.SCB1 */
3116 #define CY_MMIO_SCB1_GROUP_NR           6u
3117 #define CY_MMIO_SCB1_SLAVE_NR           2u
3118 /* MMIO6.SCB2 */
3119 #define CY_MMIO_SCB2_GROUP_NR           6u
3120 #define CY_MMIO_SCB2_SLAVE_NR           3u
3121 /* MMIO6.SCB3 */
3122 #define CY_MMIO_SCB3_GROUP_NR           6u
3123 #define CY_MMIO_SCB3_SLAVE_NR           4u
3124 /* MMIO6.SCB4 */
3125 #define CY_MMIO_SCB4_GROUP_NR           6u
3126 #define CY_MMIO_SCB4_SLAVE_NR           5u
3127 /* MMIO6.SCB5 */
3128 #define CY_MMIO_SCB5_GROUP_NR           6u
3129 #define CY_MMIO_SCB5_SLAVE_NR           6u
3130 /* MMIO6.SCB6 */
3131 #define CY_MMIO_SCB6_GROUP_NR           6u
3132 #define CY_MMIO_SCB6_SLAVE_NR           7u
3133 /* MMIO6.SCB7 */
3134 #define CY_MMIO_SCB7_GROUP_NR           6u
3135 #define CY_MMIO_SCB7_SLAVE_NR           8u
3136 /* MMIO6.SCB8 */
3137 #define CY_MMIO_SCB8_GROUP_NR           6u
3138 #define CY_MMIO_SCB8_SLAVE_NR           9u
3139 /* MMIO9.PASS */
3140 #define CY_MMIO_PASS_GROUP_NR           9u
3141 #define CY_MMIO_PASS_SLAVE_NR           1u
3142 /* MMIO10.I2S0 */
3143 #define CY_MMIO_I2S0_GROUP_NR           10u
3144 #define CY_MMIO_I2S0_SLAVE_NR           1u
3145 /* MMIO10.PDM0 */
3146 #define CY_MMIO_PDM0_GROUP_NR           10u
3147 #define CY_MMIO_PDM0_SLAVE_NR           2u
3148 
3149 /* Backward compatibility definitions */
3150 #define CPUSS_SYSTEM_INT_NR             CPUSS_IRQ_NR
3151 #define CPUSS_SYSTEM_DPSLP_INT_NR       CPUSS_DPSLP_IRQ_NR
3152 
3153 #endif /* _PSOC6_01_CONFIG_H_ */
3154 
3155 
3156 /* [] END OF FILE */
3157