1 /***************************************************************************//**
2 * \file cy_device.h
3 * \version 2.0
4 *
5 * This file specifies the structure for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************/
9 #ifndef CY_DEVICE_H_
10 #define CY_DEVICE_H_
11 
12 #include <stdint.h>
13 #include <stddef.h>
14 
15 #include "cy_utils.h"
16 #include "cy_device_headers.h"
17 #include "startup_cat1b.h"
18 
19 
20 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 1, \
21 'Checked manually. The definition is a part of linker script.')
22 
23 /* Device descriptor type */
24 typedef struct
25 {
26     /* Base HW addresses */
27     uint32_t hsiomBase;
28     uint32_t gpioBase;
29 
30     /* IP block versions: [7:4] major, [3:0] minor */
31     uint8_t  dwVersion;
32 
33     /* Parameters */
34     uint8_t  cpussDw0ChNr;
35     uint8_t  cpussDw1ChNr;
36     uint8_t  epMonitorNr;
37 
38     /* Peripheral register offsets */
39 
40    /* DW registers */
41     uint16_t dwChOffset;
42     uint16_t dwChSize;
43     uint8_t  dwChCtlPrioPos;
44     uint8_t  dwChCtlPreemptablePos;
45     uint8_t  dwStatusChIdxPos;
46     uint32_t dwStatusChIdxMsk;
47 
48     uint8_t  tcpwmCC1Present;
49     uint8_t  tcpwmAMCPresent;
50     uint8_t  tcpwmSMCPrecent;
51 
52 } cy_stc_device_t;
53 
54 /* Pointer to device configuration structure */
55 #define CY_DEVICE_CFG                   (&cy_deviceIpBlockCfg)
56 
57 
58 /*******************************************************************************
59 *                   Global Variables
60 *******************************************************************************/
61 
62 extern const cy_stc_device_t   cy_deviceIpBlockCfg;
63 extern const cy_stc_device_t* cy_device;
64 
65 /*******************************************************************************
66 *                   Global Extern Functions
67 *******************************************************************************/
68 
69 /*******************************************************************************
70 *               Macro Definitions
71 *******************************************************************************/
72 #ifdef CY_PDL_TZ_ENABLED
73 #define SECURE_ALIAS_OFFSET                 0x10000000UL
74 #define GET_ALIAS_ADDRESS(addr)             ((uint32_t)((uint32_t)addr + SECURE_ALIAS_OFFSET))
75 #else
76 #define GET_ALIAS_ADDRESS(addr)             (uint32_t)(addr)
77 #endif
78 
79 /*******************************************************************************
80 *                   Function Prototypes
81 *******************************************************************************/
82 
83 void Cy_PDL_Init(const cy_stc_device_t * device);
84 
85 /*******************************************************************************
86 *               Register Access Helper Macros
87 *******************************************************************************/
88 #define CY_DEVICE_CAT1B                /* Device Category */
89 /*******************************************************************************
90 *               SDHC
91 *******************************************************************************/
92 #define SDHC_WRAP_CTL(base)                     (((SDHC_Type *)(base))->WRAP.CTL)
93 #define SDHC_CORE_SDMASA_R(base)                (((SDHC_Type *)(base))->CORE.SDMASA_R)
94 #define SDHC_CORE_BLOCKSIZE_R(base)             (((SDHC_Type *)(base))->CORE.BLOCKSIZE_R)
95 #define SDHC_CORE_BLOCKCOUNT_R(base)            (((SDHC_Type *)(base))->CORE.BLOCKCOUNT_R)
96 #define SDHC_CORE_ARGUMENT_R(base)              (((SDHC_Type *)(base))->CORE.ARGUMENT_R)
97 #define SDHC_CORE_XFER_MODE_R(base)             (((SDHC_Type *)(base))->CORE.XFER_MODE_R)
98 #define SDHC_CORE_CMD_R(base)                   (((SDHC_Type *)(base))->CORE.CMD_R)
99 #define SDHC_CORE_RESP01_R(base)                (((SDHC_Type *)(base))->CORE.RESP01_R)
100 #define SDHC_CORE_RESP23_R(base)                (((SDHC_Type *)(base))->CORE.RESP23_R)
101 #define SDHC_CORE_RESP45_R(base)                (((SDHC_Type *)(base))->CORE.RESP45_R)
102 #define SDHC_CORE_RESP67_R(base)                (((SDHC_Type *)(base))->CORE.RESP67_R)
103 #define SDHC_CORE_BUF_DATA_R(base)              (((SDHC_Type *)(base))->CORE.BUF_DATA_R)
104 #define SDHC_CORE_PSTATE_REG(base)              (((SDHC_Type *)(base))->CORE.PSTATE_REG)
105 #define SDHC_CORE_HOST_CTRL1_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL1_R)
106 #define SDHC_CORE_PWR_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.PWR_CTRL_R)
107 #define SDHC_CORE_BGAP_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.BGAP_CTRL_R)
108 #define SDHC_CORE_WUP_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.WUP_CTRL_R)
109 #define SDHC_CORE_CLK_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.CLK_CTRL_R)
110 #define SDHC_CORE_TOUT_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.TOUT_CTRL_R)
111 #define SDHC_CORE_SW_RST_R(base)                (((SDHC_Type *)(base))->CORE.SW_RST_R)
112 #define SDHC_CORE_NORMAL_INT_STAT_R(base)       (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_R)
113 #define SDHC_CORE_ERROR_INT_STAT_R(base)        (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_R)
114 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base)    (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R)
115 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base)     (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_EN_R)
116 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base)  (((SDHC_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R)
117 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base)   (((SDHC_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R)
118 #define SDHC_CORE_AUTO_CMD_STAT_R(base)         (((SDHC_Type *)(base))->CORE.AUTO_CMD_STAT_R)
119 #define SDHC_CORE_HOST_CTRL2_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL2_R)
120 #define SDHC_CORE_CAPABILITIES1_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES1_R)
121 #define SDHC_CORE_CAPABILITIES2_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES2_R)
122 #define SDHC_CORE_CURR_CAPABILITIES1_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES1_R)
123 #define SDHC_CORE_CURR_CAPABILITIES2_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES2_R)
124 #define SDHC_CORE_ADMA_ERR_STAT_R(base)         (((SDHC_Type *)(base))->CORE.ADMA_ERR_STAT_R)
125 #define SDHC_CORE_ADMA_SA_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_SA_LOW_R)
126 #define SDHC_CORE_ADMA_ID_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_ID_LOW_R)
127 #define SDHC_CORE_EMMC_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.EMMC_CTRL_R)
128 #define SDHC_CORE_GP_OUT_R(base)                (((SDHC_Type *)(base))->CORE.GP_OUT_R)
129 
130 /*******************************************************************************
131 *                SMARTIO
132 *******************************************************************************/
133 
134 #define SMARTIO_PRT_CTL(base)               (((SMARTIO_PRT_Type *)(base))->CTL)
135 #define SMARTIO_PRT_SYNC_CTL(base)          (((SMARTIO_PRT_Type *)(base))->SYNC_CTL)
136 #define SMARTIO_PRT_LUT_SEL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx])
137 #define SMARTIO_PRT_LUT_CTL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx])
138 #define SMARTIO_PRT_DU_SEL(base)            (((SMARTIO_PRT_Type *)(base))->DU_SEL)
139 #define SMARTIO_PRT_DU_CTL(base)            (((SMARTIO_PRT_Type *)(base))->DU_CTL)
140 #define SMARTIO_PRT_DATA(base)              (((SMARTIO_PRT_Type *)(base))->DATA)
141 
142 
143 /*******************************************************************************
144 *                SMIF
145 *******************************************************************************/
146 #if ((defined(CY_IP_MXSMIF_VERSION)) && (CY_IP_MXSMIF_VERSION>=3))
147 /* For backward compatibility of API, use first crypto device as default device */
148 #define SMIF_CRYPTO_CMD(base)            (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_CMD)
149 #define SMIF_CRYPTO_ADDR(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_ADDR)
150 #define SMIF_CRYPTO_MASK(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_MASK)
151 #define SMIF_CRYPTO_SUBREGION(base)      (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_SUBREGION)
152 #define SMIF_CRYPTO_INPUT0(base)         (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT0)
153 #define SMIF_CRYPTO_INPUT1(base)         (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT1)
154 #define SMIF_CRYPTO_INPUT2(base)         (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT2)
155 #define SMIF_CRYPTO_INPUT3(base)         (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT3)
156 #define SMIF_CRYPTO_KEY0(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY0)
157 #define SMIF_CRYPTO_KEY1(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY1)
158 #define SMIF_CRYPTO_KEY2(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY2)
159 #define SMIF_CRYPTO_KEY3(base)           (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY3)
160 #define SMIF_CRYPTO_OUTPUT0(base)        (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT0)
161 #define SMIF_CRYPTO_OUTPUT1(base)        (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT1)
162 #define SMIF_CRYPTO_OUTPUT2(base)        (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT2)
163 #define SMIF_CRYPTO_OUTPUT3(base)        (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT3)
164 #else
165 #define SMIF_CRYPTO_CMD(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_CMD)
166 #define SMIF_CRYPTO_ADDR(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_ADDR)
167 #define SMIF_CRYPTO_MASK(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_MASK)
168 #define SMIF_CRYPTO_SUBREGION(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_SUBREGION)
169 #define SMIF_CRYPTO_INPUT0(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT0)
170 #define SMIF_CRYPTO_INPUT1(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT1)
171 #define SMIF_CRYPTO_INPUT2(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT2)
172 #define SMIF_CRYPTO_INPUT3(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT3)
173 #define SMIF_CRYPTO_KEY0(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY0)
174 #define SMIF_CRYPTO_KEY1(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY1)
175 #define SMIF_CRYPTO_KEY2(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY2)
176 #define SMIF_CRYPTO_KEY3(base)            (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY3)
177 #define SMIF_CRYPTO_OUTPUT0(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT0)
178 #define SMIF_CRYPTO_OUTPUT1(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT1)
179 #define SMIF_CRYPTO_OUTPUT2(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT2)
180 #define SMIF_CRYPTO_OUTPUT3(base)        (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT3)
181 #endif
182 
183 #define SMIF_CRYPTO_IDX(base, deviceIndex)                 (((SMIF_Type *)(base))->SMIF_CRYPTO_BLOCK[deviceIndex])
184 
185 #define SMIF_CRYPTO_IDX_CMD(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_CMD)
186 #define SMIF_CRYPTO_IDX_ADDR(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_ADDR)
187 #define SMIF_CRYPTO_IDX_MASK(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_MASK)
188 #define SMIF_CRYPTO_IDX_SUBREGION(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_SUBREGION)
189 #define SMIF_CRYPTO_IDX_INPUT0(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT0)
190 #define SMIF_CRYPTO_IDX_INPUT1(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT1)
191 #define SMIF_CRYPTO_IDX_INPUT2(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT2)
192 #define SMIF_CRYPTO_IDX_INPUT3(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT3)
193 #define SMIF_CRYPTO_IDX_KEY0(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY0)
194 #define SMIF_CRYPTO_IDX_KEY1(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY1)
195 #define SMIF_CRYPTO_IDX_KEY2(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY2)
196 #define SMIF_CRYPTO_IDX_KEY3(base, deviceIndex)        (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY3)
197 #define SMIF_CRYPTO_IDX_OUTPUT0(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT0)
198 #define SMIF_CRYPTO_IDX_OUTPUT1(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT1)
199 #define SMIF_CRYPTO_IDX_OUTPUT2(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT2)
200 #define SMIF_CRYPTO_IDX_OUTPUT3(base, deviceIndex)    (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT3)
201 
202 
203 #define SMIF_DEVICE_CTL(base)               (((SMIF_DEVICE_Type *)(base))->CTL)
204 #define SMIF_DEVICE_ADDR(base)              (((SMIF_DEVICE_Type *)(base))->ADDR)
205 #define SMIF_DEVICE_ADDR_CTL(base)          (((SMIF_DEVICE_Type *)(base))->ADDR_CTL)
206 #define SMIF_DEVICE_MASK(base)              (((SMIF_DEVICE_Type *)(base))->MASK)
207 #define SMIF_DEVICE_RD_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->RD_CMD_CTL)
208 #define SMIF_DEVICE_RD_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_ADDR_CTL)
209 #define SMIF_DEVICE_RD_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_MODE_CTL)
210 #define SMIF_DEVICE_RD_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->RD_DUMMY_CTL)
211 #define SMIF_DEVICE_RD_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_DATA_CTL)
212 #define SMIF_DEVICE_RD_BOUND_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_BOUND_CTL)
213 #define SMIF_DEVICE_WR_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->WR_CMD_CTL)
214 #define SMIF_DEVICE_WR_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_ADDR_CTL)
215 #define SMIF_DEVICE_WR_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_MODE_CTL)
216 #define SMIF_DEVICE_WR_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->WR_DUMMY_CTL)
217 #define SMIF_DEVICE_WR_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_DATA_CTL)
218 
219 #define SMIF_DEVICE_IDX(base, deviceIndex)                 (((SMIF_Type *)(base))->DEVICE[deviceIndex])
220 
221 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex)             (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
222 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
223 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex)        (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
224 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
225 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
226 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
227 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
228 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
229 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
230 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
231 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
232 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
233 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
234 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
235 
236 #define SMIF_CTL(base)                        (((SMIF_Type *)(base))->CTL)
237 #define SMIF_STATUS(base)                    (((SMIF_Type *)(base))->STATUS)
238 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0(base)    (((SMIF_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL0)
239 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1(base)    (((SMIF_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL1)
240 #define SMIF_DL_CTL(base)                    (((SMIF_Type *)(base))->DL_CTL)
241 #define SMIF_DL_STATUS0(base)                (((SMIF_Type *)(base))->DL_STATUS0)
242 #define SMIF_DL_STATUS1(base)                (((SMIF_Type *)(base))->DL_STATUS1)
243 #define SMIF_TX_CMD_FIFO_STATUS(base)        (((SMIF_Type *)(base))->TX_CMD_FIFO_STATUS)
244 #define SMIF_TX_CMD_MMIO_FIFO_STATUS(base)    (((SMIF_Type *)(base))->TX_CMD_MMIO_FIFO_STATUS)
245 #define SMIF_TX_CMD_MMIO_FIFO_WR(base)        (((SMIF_Type *)(base))->TX_CMD_MMIO_FIFO_WR)
246 #define SMIF_TX_DATA_MMIO_FIFO_CTL(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_CTL)
247 #define SMIF_TX_DATA_FIFO_STATUS(base)        (((SMIF_Type *)(base))->TX_DATA_FIFO_STATUS)
248 #define SMIF_TX_DATA_MMIO_FIFO_STATUS(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_STATUS)
249 #define SMIF_TX_DATA_MMIO_FIFO_WR1(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR1)
250 #define SMIF_TX_DATA_MMIO_FIFO_WR2(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR2)
251 #define SMIF_TX_DATA_MMIO_FIFO_WR4(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR4)
252 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD(base)    (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR1ODD)
253 #define SMIF_RX_DATA_MMIO_FIFO_CTL(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_CTL)
254 #define SMIF_RX_DATA_MMIO_FIFO_STATUS(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_STATUS)
255 #define SMIF_RX_DATA_FIFO_STATUS(base)        (((SMIF_Type *)(base))->RX_DATA_FIFO_STATUS)
256 #define SMIF_RX_DATA_MMIO_FIFO_RD1(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1)
257 #define SMIF_RX_DATA_MMIO_FIFO_RD2(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD2)
258 #define SMIF_RX_DATA_MMIO_FIFO_RD4(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD4)
259 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1_SILENT)
260 #define SMIF_SLOW_CA_CTL(base)                   (((SMIF_Type *)(base))->SLOW_CA_CTL)
261 #define SMIF_SLOW_CA_CMD(base)                (((SMIF_Type *)(base))->SLOW_CA_CMD)
262 #define SMIF_FAST_CA_CTL(base)                (((SMIF_Type *)(base))->FAST_CA_CTL)
263 #define SMIF_FAST_CA_CMD(base)                (((SMIF_Type *)(base))->FAST_CA_CMD)
264 #define SMIF_CRC_CMD(base)                    (((SMIF_Type *)(base))->CRC_CMD)
265 #define SMIF_CRC_INPUT0(base)                (((SMIF_Type *)(base))->CRC_INPUT0)
266 #define SMIF_CRC_INPUT1(base)                (((SMIF_Type *)(base))->CRC_INPUT1)
267 #define SMIF_CRC_OUTPUT(base)                (((SMIF_Type *)(base))->CRC_OUTPUT)
268 #define SMIF_INTR(base)                        (((SMIF_Type *)(base))->INTR)
269 #define SMIF_INTR_SET(base)                    (((SMIF_Type *)(base))->INTR_SET)
270 #define SMIF_INTR_MASK(base)                (((SMIF_Type *)(base))->INTR_MASK)
271 #define SMIF_INTR_MASKED(base)                (((SMIF_Type *)(base))->INTR_MASKED)
272 
273 /*******************************************************************************
274 *                DW
275 *******************************************************************************/
276 
277 
278 #define CY_DW                               (0UL)
279 #define CY_DW_CRC                           (1UL)
280 #define CY_DW0_BASE                         DW0
281 #define CY_DW1_BASE                         DW1
282 #define CY_DW0_CH_NR                        CPUSS_DW0_CH_NR
283 #define CY_DW1_CH_NR                        CPUSS_DW1_CH_NR
284 
285 #define CY_DW_CH_CTL_PRIO_Pos               ((uint32_t)(DW_CH_STRUCT_CH_CTL_PRIO_Pos))
286 #define CY_DW_CH_CTL_PRIO_Msk               ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos))
287 #define CY_DW_CH_CTL_PREEMPTABLE_Pos        ((uint32_t)(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos))
288 #define CY_DW_CH_CTL_PREEMPTABLE_Msk        ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos))
289 #define CY_DW_STATUS_CH_IDX_Pos             ((uint32_t)(DW_STATUS_CH_IDX_Pos))
290 #define CY_DW_STATUS_CH_IDX_Msk             (DW_STATUS_CH_IDX_Msk)
291 
292 #define DW_CTL(base)                        (((DW_Type*)(base))->CTL)
293 #define DW_STATUS(base)                     (((DW_Type const*)(base))->STATUS)
294 #define DW_DESCR_SRC(base)                  (((DW_Type*)(base))->ACT_DESCR_SRC)
295 #define DW_DESCR_DST(base)                  (((DW_Type*)(base))->ACT_DESCR_DST)
296 
297 #define DW_CRC_CTL(base)                    (((DW_Type*)(base))->CRC_CTL)
298 #define DW_CRC_DATA_CTL(base)               (((DW_Type*)(base))->CRC_DATA_CTL)
299 #define DW_CRC_REM_CTL(base)                (((DW_Type*)(base))->CRC_REM_CTL)
300 #define DW_CRC_POL_CTL(base)                (((DW_Type*)(base))->CRC_POL_CTL)
301 #define DW_CRC_LFSR_CTL(base)               (((DW_Type*)(base))->CRC_LFSR_CTL)
302 
303 #define DW_CH_OFFSET                        (uint32_t)(offsetof(DW_Type, CH_STRUCT))
304 #define DW_CH_SIZE                            (uint32_t)(sizeof(DW_CH_STRUCT_Type))
305 
306 #define DW_CH(base, chan)                    ((DW_CH_STRUCT_Type*)((uint32_t)(base) + DW_CH_OFFSET + (chan * DW_CH_SIZE)))
307 #define DW_CH_CTL(base, chan)               (DW_CH((base), (chan))->CH_CTL)
308 #define DW_CH_STATUS(base, chan)            (DW_CH((base), (chan))->CH_STATUS)
309 #define DW_CH_IDX(base, chan)               (DW_CH((base), (chan))->CH_IDX)
310 #define DW_CH_CURR_PTR(base, chan)          (DW_CH((base), (chan))->CH_CURR_PTR)
311 
312 #define DW_CH_INTR(base, chan)              (DW_CH((base), (chan))->INTR)
313 #define DW_CH_INTR_SET(base, chan)          (DW_CH((base), (chan))->INTR_SET)
314 #define DW_CH_INTR_MASK(base, chan)         (DW_CH((base), (chan))->INTR_MASK)
315 #define DW_CH_INTR_MASKED(base, chan)       (DW_CH((base), (chan))->INTR_MASKED)
316 
317 #if defined (CY_IP_MXDW)
318 #define DW_V2_CRC_CTL_DATA_REVERSE_Msk DW_CRC_CTL_DATA_REVERSE_Msk
319 #define DW_V2_CRC_CTL_REM_REVERSE_Msk DW_CRC_CTL_REM_REVERSE_Msk
320 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk DW_CRC_DATA_CTL_DATA_XOR_Msk
321 #define DW_V2_CRC_REM_CTL_REM_XOR_Msk DW_CRC_REM_CTL_REM_XOR_Msk
322 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk DW_CRC_POL_CTL_POLYNOMIAL_Msk
323 #define DW_V2_CRC_LFSR_CTL_LFSR32_Msk DW_CRC_LFSR_CTL_LFSR32_Msk
324 #define DW_V2_CRC_CTL_DATA_REVERSE_Pos DW_CRC_CTL_DATA_REVERSE_Pos
325 #define DW_V2_CRC_CTL_REM_REVERSE_Pos DW_CRC_CTL_REM_REVERSE_Pos
326 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos DW_CRC_DATA_CTL_DATA_XOR_Pos
327 #define DW_V2_CRC_REM_CTL_REM_XOR_Pos DW_CRC_REM_CTL_REM_XOR_Pos
328 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos DW_CRC_POL_CTL_POLYNOMIAL_Pos
329 #define DW_V2_CRC_LFSR_CTL_LFSR32_Pos DW_CRC_LFSR_CTL_LFSR32_Pos
330 #endif /* CY_IP_MXDW */
331 
332 /*******************************************************************************
333 *                DMAC
334 *******************************************************************************/
335 #if defined (CY_IP_MXAHBDMAC)
336 #define CY_DMAC_CH_NR                       (4UL)
337 #define DMAC_CTL(base)                      (((MXAHBDMAC_Type*)(base))->CTL)
338 #define DMAC_ACTIVE(base)                   (((MXAHBDMAC_Type const*)(base))->ACTIVE)
339 #define DMAC_CH(base, chan)                 (&(((MXAHBDMAC_Type*)(base))->CH[(chan)]))
340 #define DMAC_CH_CTL(base, chan)             (DMAC_CH(base, chan)->CTL)
341 #define DMAC_CH_IDX(base, chan)             (DMAC_CH(base, chan)->IDX)
342 #define DMAC_CH_CURR(base, chan)            (DMAC_CH(base, chan)->CURR)
343 #define DMAC_CH_DESCR_SRC(base, chan)       (DMAC_CH(base, chan)->DESCR_SRC)
344 #define DMAC_CH_DESCR_DST(base, chan)       (DMAC_CH(base, chan)->DESCR_DST)
345 #define DMAC_CH_INTR(base, chan)            (DMAC_CH(base, chan)->INTR)
346 #define DMAC_CH_INTR_SET(base, chan)        (DMAC_CH(base, chan)->INTR_SET)
347 #define DMAC_CH_INTR_MASK(base, chan)       (DMAC_CH(base, chan)->INTR_MASK)
348 #define DMAC_CH_INTR_MASKED(base, chan)     (DMAC_CH(base, chan)->INTR_MASKED)
349 
350 typedef MXAHBDMAC_Type DMAC_Type;
351 #define DMAC                                    MXAHBDMAC0_BASE
352 
353 #define DMAC_CH_V2_INTR_COMPLETION_Msk MXAHBDMAC_CH_INTR_COMPLETION_Msk
354 #define DMAC_CH_V2_INTR_COMPLETION_Pos MXAHBDMAC_CH_INTR_COMPLETION_Pos
355 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_SRC_BUS_ERROR_Msk
356 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_SRC_BUS_ERROR_Pos
357 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_DST_BUS_ERROR_Msk
358 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_DST_BUS_ERROR_Pos
359 #define DMAC_CH_V2_INTR_SRC_MISAL_Msk MXAHBDMAC_CH_INTR_SRC_MISAL_Msk
360 #define DMAC_CH_V2_INTR_SRC_MISAL_Pos MXAHBDMAC_CH_INTR_SRC_MISAL_Pos
361 #define DMAC_CH_V2_INTR_DST_MISAL_Msk MXAHBDMAC_CH_INTR_DST_MISAL_Msk
362 #define DMAC_CH_V2_INTR_DST_MISAL_Pos MXAHBDMAC_CH_INTR_DST_MISAL_Pos
363 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk MXAHBDMAC_CH_INTR_CURR_PTR_NULL_Msk
364 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos MXAHBDMAC_CH_INTR_CURR_PTR_NULL_Pos
365 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk MXAHBDMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk
366 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos MXAHBDMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos
367 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_DESCR_BUS_ERROR_Msk
368 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_DESCR_BUS_ERROR_Pos
369 #define DMAC_Type MXAHBDMAC_Type
370 #define DMAC_V2_CTL_ENABLED_Msk MXAHBDMAC_CTL_ENABLED_Msk
371 #define DMAC_V2_CTL_ENABLED_Pos MXAHBDMAC_CTL_ENABLED_Pos
372 #define DMAC_V2_ACTIVE_ACTIVE_Msk MXAHBDMAC_ACTIVE_ACTIVE_Msk
373 #define DMAC_V2_ACTIVE_ACTIVE_Pos MXAHBDMAC_ACTIVE_ACTIVE_Pos
374 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_INTR_TYPE_Msk
375 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_INTR_TYPE_Pos
376 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk
377 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos
378 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk
379 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos
380 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_DATA_SIZE_Msk
381 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_DATA_SIZE_Pos
382 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk
383 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos
384 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk
385 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos
386 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk MXAHBDMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk
387 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos MXAHBDMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos
388 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_DESCR_TYPE_Msk
389 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_DESCR_TYPE_Pos
390 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk MXAHBDMAC_CH_DESCR_CTL_CH_DISABLE_Msk
391 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos MXAHBDMAC_CH_DESCR_CTL_CH_DISABLE_Pos
392 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk MXAHBDMAC_CH_DESCR_X_INCR_SRC_X_Msk
393 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos MXAHBDMAC_CH_DESCR_X_INCR_SRC_X_Pos
394 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk MXAHBDMAC_CH_DESCR_X_INCR_DST_X_Msk
395 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos MXAHBDMAC_CH_DESCR_X_INCR_DST_X_Pos
396 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk MXAHBDMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk
397 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos MXAHBDMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos
398 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk MXAHBDMAC_CH_DESCR_Y_INCR_SRC_Y_Msk
399 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos MXAHBDMAC_CH_DESCR_Y_INCR_SRC_Y_Pos
400 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk MXAHBDMAC_CH_DESCR_Y_INCR_DST_Y_Msk
401 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos MXAHBDMAC_CH_DESCR_Y_INCR_DST_Y_Pos
402 #define DMAC_CH_V2_CTL_ENABLED_Msk MXAHBDMAC_CH_CTL_ENABLED_Msk
403 #define DMAC_CH_V2_CTL_ENABLED_Pos MXAHBDMAC_CH_CTL_ENABLED_Pos
404 #define DMAC_CH_V2_CTL_PRIO_Msk MXAHBDMAC_CH_CTL_PRIO_Msk
405 #define DMAC_CH_V2_CTL_PRIO_Pos MXAHBDMAC_CH_CTL_PRIO_Pos
406 #define DMAC_CH_V2_IDX_X_Msk MXAHBDMAC_CH_IDX_X_Msk
407 #define DMAC_CH_V2_IDX_X_Pos MXAHBDMAC_CH_IDX_X_Pos
408 #define DMAC_CH_V2_IDX_Y_Msk MXAHBDMAC_CH_IDX_Y_Msk
409 #define DMAC_CH_V2_IDX_Y_Pos MXAHBDMAC_CH_IDX_Y_Pos
410 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk MXAHBDMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk
411 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos MXAHBDMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos
412 #define DMAC_CH_V2_CTL_B_Msk MXAHBDMAC_CH_CTL_B_Msk
413 #define DMAC_CH_V2_CTL_B_Pos MXAHBDMAC_CH_CTL_B_Pos
414 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk MXAHBDMAC_CH_DESCR_X_SIZE_X_COUNT_Msk
415 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos MXAHBDMAC_CH_DESCR_X_SIZE_X_COUNT_Pos
416 
417 #endif
418 
419 
420 /*******************************************************************************
421 *                IOSS
422 *******************************************************************************/
423 
424 #define CY_GPIO_BASE                       ((uint32_t)GPIO_BASE)
425 
426 #define GPIO_SEC_INTR_CAUSE0               ((GPIO)->SEC_INTR_CAUSE0)
427 #define GPIO_SEC_INTR_CAUSE1               ((GPIO)->SEC_INTR_CAUSE1)
428 #define GPIO_SEC_INTR_CAUSE2               ((GPIO)->SEC_INTR_CAUSE2)
429 #define GPIO_SEC_INTR_CAUSE3               ((GPIO)->SEC_INTR_CAUSE3)
430 #define GPIO_INTR_CAUSE0                   ((GPIO)->INTR_CAUSE0)
431 #define GPIO_INTR_CAUSE1                   ((GPIO)->INTR_CAUSE1)
432 #define GPIO_INTR_CAUSE2                   ((GPIO)->INTR_CAUSE2)
433 #define GPIO_INTR_CAUSE3                   ((GPIO)->INTR_CAUSE3)
434 
435 #define GPIO_PRT_OUT(base)                 (((GPIO_PRT_Type*)(base))->OUT)
436 #define GPIO_PRT_OUT_CLR(base)             (((GPIO_PRT_Type*)(base))->OUT_CLR)
437 #define GPIO_PRT_OUT_SET(base)             (((GPIO_PRT_Type*)(base))->OUT_SET)
438 #define GPIO_PRT_OUT_INV(base)             (((GPIO_PRT_Type*)(base))->OUT_INV)
439 #define GPIO_PRT_IN(base)                  (((GPIO_PRT_Type*)(base))->IN)
440 #define GPIO_PRT_INTR(base)                (((GPIO_PRT_Type*)(base))->INTR)
441 #define GPIO_PRT_INTR_MASK(base)           (((GPIO_PRT_Type*)(base))->INTR_MASK)
442 #define GPIO_PRT_INTR_MASKED(base)         (((GPIO_PRT_Type*)(base))->INTR_MASKED)
443 #define GPIO_PRT_INTR_SET(base)            (((GPIO_PRT_Type*)(base))->INTR_SET)
444 #define GPIO_PRT_INTR_CFG(base)            (((GPIO_PRT_Type*)(base))->INTR_CFG)
445 #define GPIO_PRT_CFG(base)                 (((GPIO_PRT_Type*)(base))->CFG)
446 #define GPIO_PRT_CFG_IN(base)              (((GPIO_PRT_Type*)(base))->CFG_IN)
447 #define GPIO_PRT_CFG_OUT(base)             (((GPIO_PRT_Type*)(base))->CFG_OUT)
448 #define GPIO_PRT_CFG_SIO(base)             (((GPIO_PRT_Type*)(base))->CFG_SIO)
449 #define GPIO_PRT_SLEW_EXT(base)            (((GPIO_PRT_Type*)(base))->CFG_SLEW_EXT)
450 #define GPIO_PRT_DRIVE_EXT0(base)          (((GPIO_PRT_Type*)(base))->CFG_DRIVE_EXT0)
451 #define GPIO_PRT_DRIVE_EXT1(base)          (((GPIO_PRT_Type*)(base))->CFG_DRIVE_EXT1)
452 #define GPIO_PRT_CFG_IN_AUTOLVL(base)      (((GPIO_PRT_Type*)(base))->CFG_IN_AUTOLVL)
453 
454 #define CY_HSIOM_BASE                      ((uint32_t)HSIOM_BASE)
455 
456 #define HSIOM_PRT_PORT_SEL0(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL0)
457 #define HSIOM_PRT_PORT_SEL1(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL1)
458 
459 #if (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0)
460 #define CY_HSIOM_SECURE_BASE               ((uint32_t)&HSIOM->SECURE_PRT[0])
461 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
462 
463 
464 #define HSIOM_SEC_PRT_NONSEC_MASK(base)    (((HSIOM_SECURE_PRT_Type *)(base))->NONSECURE_MASK)
465 
466 
467 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl)    (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl])
468 
469 /*******************************************************************************
470 *                SCB
471 *******************************************************************************/
472 #define SCB_CTRL(base)                      (((CySCB_Type*) (base))->CTRL)
473 #define SCB_SPI_CTRL(base)                  (((CySCB_Type*) (base))->SPI_CTRL)
474 #define SCB_SPI_STATUS(base)                (((CySCB_Type*) (base))->SPI_STATUS)
475 #define SCB_SPI_TX_CTRL(base)              (((CySCB_Type*) (base))->SPI_TX_CTRL)
476 #define SCB_SPI_RX_CTRL(base)              (((CySCB_Type*) (base))->SPI_RX_CTRL)
477 #define SCB_UART_CTRL(base)                 (((CySCB_Type*) (base))->UART_CTRL)
478 #define SCB_UART_TX_CTRL(base)              (((CySCB_Type*) (base))->UART_TX_CTRL)
479 #define SCB_UART_RX_CTRL(base)              (((CySCB_Type*) (base))->UART_RX_CTRL)
480 #define SCB_UART_FLOW_CTRL(base)            (((CySCB_Type*) (base))->UART_FLOW_CTRL)
481 #define SCB_I2C_CTRL(base)                  (((CySCB_Type*) (base))->I2C_CTRL)
482 #define SCB_I2C_STATUS(base)                (((CySCB_Type*) (base))->I2C_STATUS)
483 #define SCB_I2C_M_CMD(base)                 (((CySCB_Type*) (base))->I2C_M_CMD)
484 #define SCB_I2C_S_CMD(base)                 (((CySCB_Type*) (base))->I2C_S_CMD)
485 #define SCB_I2C_CFG(base)                   (((CySCB_Type*) (base))->I2C_CFG)
486 #define SCB_I2C_STRETCH_CTRL(base)          (((CySCB_Type*) (base))->I2C_STRETCH_CTRL)
487 #define SCB_I2C_STRETCH_STATUS(base)        (((CySCB_Type*) (base))->I2C_STRETCH_STATUS)
488 #define SCB_TX_CTRL(base)                   (((CySCB_Type*) (base))->TX_CTRL)
489 #define SCB_TX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->TX_FIFO_CTRL)
490 #define SCB_TX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->TX_FIFO_STATUS)
491 #define SCB_TX_FIFO_WR(base)                (((CySCB_Type*) (base))->TX_FIFO_WR)
492 #define SCB_RX_CTRL(base)                   (((CySCB_Type*) (base))->RX_CTRL)
493 #define SCB_RX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->RX_FIFO_CTRL)
494 #define SCB_RX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->RX_FIFO_STATUS)
495 #define SCB_RX_MATCH(base)                  (((CySCB_Type*) (base))->RX_MATCH)
496 #define SCB_RX_FIFO_RD(base)                (((CySCB_Type*) (base))->RX_FIFO_RD)
497 #define SCB_INTR_CAUSE(base)                (((CySCB_Type*) (base))->INTR_CAUSE)
498 #define SCB_INTR_I2C_EC(base)               (((CySCB_Type*) (base))->INTR_I2C_EC)
499 #define SCB_INTR_I2C_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_I2C_EC_MASK)
500 #define SCB_INTR_I2C_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_I2C_EC_MASKED)
501 #define SCB_INTR_SPI_EC(base)               (((CySCB_Type*) (base))->INTR_SPI_EC)
502 #define SCB_INTR_SPI_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_SPI_EC_MASK)
503 #define SCB_INTR_SPI_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_SPI_EC_MASKED)
504 #define SCB_INTR_M(base)                    (((CySCB_Type*) (base))->INTR_M)
505 #define SCB_INTR_M_SET(base)                (((CySCB_Type*) (base))->INTR_M_SET)
506 #define SCB_INTR_M_MASK(base)               (((CySCB_Type*) (base))->INTR_M_MASK)
507 #define SCB_INTR_M_MASKED(base)             (((CySCB_Type*) (base))->INTR_M_MASKED)
508 #define SCB_INTR_S(base)                    (((CySCB_Type*) (base))->INTR_S)
509 #define SCB_INTR_S_SET(base)                (((CySCB_Type*) (base))->INTR_S_SET)
510 #define SCB_INTR_S_MASK(base)               (((CySCB_Type*) (base))->INTR_S_MASK)
511 #define SCB_INTR_S_MASKED(base)             (((CySCB_Type*) (base))->INTR_S_MASKED)
512 #define SCB_INTR_TX(base)                   (((CySCB_Type*) (base))->INTR_TX)
513 #define SCB_INTR_TX_SET(base)               (((CySCB_Type*) (base))->INTR_TX_SET)
514 #define SCB_INTR_TX_MASK(base)              (((CySCB_Type*) (base))->INTR_TX_MASK)
515 #define SCB_INTR_TX_MASKED(base)            (((CySCB_Type*) (base))->INTR_TX_MASKED)
516 #define SCB_INTR_RX(base)                   (((CySCB_Type*) (base))->INTR_RX)
517 #define SCB_INTR_RX_SET(base)               (((CySCB_Type*) (base))->INTR_RX_SET)
518 #define SCB_INTR_RX_MASK(base)              (((CySCB_Type*) (base))->INTR_RX_MASK)
519 #define SCB_INTR_RX_MASKED(base)            (((CySCB_Type*) (base))->INTR_RX_MASKED)
520 
521 #if(CY_IP_MXSCB_VERSION>=4)
522 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos SCB_SPI_CTRL_LATE_SAMPLE_Pos
523 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk SCB_SPI_CTRL_LATE_SAMPLE_Msk
524 #endif
525 
526 
527 /*******************************************************************************
528 *                I3C
529 *******************************************************************************/
530 
531 
532 #define I3C_CORE_DEVICE_CTRL(base)                         (((I3C_CORE_Type*) (base))->DEVICE_CTRL)
533 #define I3C_CORE_DEVICE_ADDR(base)                         (((I3C_CORE_Type*) (base))->DEVICE_ADDR)
534 #define I3C_CORE_HW_CAPABILITY(base)                     (((I3C_CORE_Type*) (base))->HW_CAPABILITY)
535 #define I3C_CORE_COMMAND_QUEUE_PORT(base)                 (((I3C_CORE_Type*) (base))->COMMAND_QUEUE_PORT)
536 #define I3C_CORE_RESPONSE_QUEUE_PORT(base)                 (((I3C_CORE_Type*) (base))->RESPONSE_QUEUE_PORT)
537 #define I3C_CORE_TX_RX_DATA_PORT(base)                     (((I3C_CORE_Type*) (base))->TX_RX_DATA_PORT)
538 #define I3C_CORE_IBI_QUEUE_STATUS(base)                 (((I3C_CORE_Type*) (base))->IBI_QUEUE_STATUS)
539 #define I3C_CORE_QUEUE_THLD_CTRL(base)                     (((I3C_CORE_Type*) (base))->QUEUE_THLD_CTRL)
540 #define I3C_CORE_DATA_BUFFER_THLD_CTRL(base)            (((I3C_CORE_Type*) (base))->DATA_BUFFER_THLD_CTRL)
541 #define I3C_CORE_IBI_QUEUE_CTRL(base)                    (((I3C_CORE_Type*) (base))->IBI_QUEUE_CTRL)
542 #define I3C_CORE_IBI_MR_REQ_REJECT(base)                 (((I3C_CORE_Type*) (base))->IBI_MR_REQ_REJECT)
543 #define I3C_CORE_IBI_SIR_REQ_REJECT(base)               (((I3C_CORE_Type*) (base))->IBI_SIR_REQ_REJECT)
544 #define I3C_CORE_RESET_CTRL(base)                       (((I3C_CORE_Type*) (base))->RESET_CTRL)
545 #define I3C_CORE_SLV_EVENT_STATUS(base)                 (((I3C_CORE_Type*) (base))->SLV_EVENT_STATUS)
546 #define I3C_CORE_INTR_STATUS(base)                      (((I3C_CORE_Type*) (base))->INTR_STATUS)
547 #define I3C_CORE_INTR_STATUS_EN(base)                   (((I3C_CORE_Type*) (base))->INTR_STATUS_EN)
548 #define I3C_CORE_INTR_SIGNAL_EN(base)                   (((I3C_CORE_Type*) (base))->INTR_SIGNAL_EN)
549 #define I3C_CORE_INTR_FORCE(base)                       (((I3C_CORE_Type*) (base))->INTR_FORCE)
550 #define I3C_CORE_QUEUE_STATUS_LEVEL(base)               (((I3C_CORE_Type*) (base))->QUEUE_STATUS_LEVEL)
551 #define I3C_CORE_DATA_BUFFER_STATUS_LEVEL(base)         (((I3C_CORE_Type*) (base))->DATA_BUFFER_STATUS_LEVEL)
552 #define I3C_CORE_PRESENT_STATE(base)                     (((I3C_CORE_Type*) (base))->PRESENT_STATE)
553 #define I3C_CORE_CCC_DEVICE_STATUS(base)                (((I3C_CORE_Type*) (base))->CCC_DEVICE_STATUS)
554 #define I3C_CORE_DEVICE_ADDR_TABLE_POINTER(base)        (((I3C_CORE_Type*) (base))->DEVICE_ADDR_TABLE_POINTER)
555 #define I3C_CORE_DEV_CHAR_TABLE_POINTER(base)           (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE_POINTER)
556 #define I3C_CORE_VENDOR_SPECIFIC_REG_POINTER(base)      (((I3C_CORE_Type*) (base))->VENDOR_SPECIFIC_REG_POINTER)
557 #define I3C_CORE_SLV_PID_VALUE(base)                    (((I3C_CORE_Type*) (base))->SLV_PID_VALUE)
558 #define I3C_CORE_SLV_CHAR_CTRL(base)                    (((I3C_CORE_Type*) (base))->SLV_CHAR_CTRL)
559 #define I3C_CORE_SLV_MAX_LEN(base)                      (((I3C_CORE_Type*) (base))->SLV_MAX_LEN)
560 #define I3C_CORE_MAX_READ_TURNAROUND(base)              (((I3C_CORE_Type*) (base))->MAX_READ_TURNAROUND)
561 #define I3C_CORE_MAX_DATA_SPEED(base)                   (((I3C_CORE_Type*) (base))->MAX_DATA_SPEED)
562 #define I3C_CORE_SLV_INTR_REQ(base)                      (((I3C_CORE_Type*) (base))->SLV_INTR_REQ)
563 #define I3C_CORE_DEVICE_CTRL_EXTENDED(base)             (((I3C_CORE_Type*) (base))->DEVICE_CTRL_EXTENDED)
564 #define I3C_CORE_SCL_I3C_OD_TIMING(base)                (((I3C_CORE_Type*) (base))->SCL_I3C_OD_TIMING)
565 #define I3C_CORE_SCL_I3C_PP_TIMING(base)                (((I3C_CORE_Type*) (base))->SCL_I3C_PP_TIMING)
566 #define I3C_CORE_SCL_I2C_FM_TIMING(base)                (((I3C_CORE_Type*) (base))->SCL_I2C_FM_TIMING)
567 #define I3C_CORE_SCL_I2C_FMP_TIMING(base)               (((I3C_CORE_Type*) (base))->SCL_I2C_FMP_TIMING)
568 #define I3C_CORE_SCL_EXT_LCNT_TIMING(base)              (((I3C_CORE_Type*) (base))->SCL_EXT_LCNT_TIMING)
569 #define I3C_CORE_SCL_EXT_TERMN_LCNT_TIMING(base)        (((I3C_CORE_Type*) (base))->SCL_EXT_TERMN_LCNT_TIMING)
570 #define I3C_CORE_SDA_HOLD_DLY_TIMING(base)              (((I3C_CORE_Type*) (base))->SDA_HOLD_DLY_TIMING)
571 #define I3C_CORE_BUS_FREE_AVAIL_TIMING(base)            (((I3C_CORE_Type*) (base))->BUS_FREE_AVAIL_TIMING)
572 #define I3C_CORE_BUS_IDLE_TIMING(base)                   (((I3C_CORE_Type*) (base))->BUS_IDLE_TIMING)
573 #define I3C_CORE_I3C_VER_ID(base)                       (((I3C_CORE_Type*) (base))->I3C_VER_ID)
574 #define I3C_CORE_I3C_VER_TYPE(base)                     (((I3C_CORE_Type*) (base))->I3C_VER_TYPE)
575 #define I3C_CORE_QUEUE_SIZE_CAPABILITY(base)            (((I3C_CORE_Type*) (base))->QUEUE_SIZE_CAPABILITY)
576 #define I3C_CORE_DEV_CHAR_TABLE1_LOC1(base)                (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC1)
577 #define I3C_CORE_DEV_CHAR_TABLE1_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC2)
578 #define I3C_CORE_DEV_CHAR_TABLE1_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC3)
579 #define I3C_CORE_DEV_CHAR_TABLE1_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC4)
580 #define I3C_CORE_DEV_CHAR_TABLE2_LOC1(base)                (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC1)
581 #define I3C_CORE_DEV_CHAR_TABLE2_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC2)
582 #define I3C_CORE_DEV_CHAR_TABLE2_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC3)
583 #define I3C_CORE_DEV_CHAR_TABLE2_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC4)
584 #define I3C_CORE_DEV_CHAR_TABLE3_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC1)
585 #define I3C_CORE_DEV_CHAR_TABLE3_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC2)
586 #define I3C_CORE_DEV_CHAR_TABLE3_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC3)
587 #define I3C_CORE_DEV_CHAR_TABLE3_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC4)
588 #define I3C_CORE_DEV_CHAR_TABLE4_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC1)
589 #define I3C_CORE_DEV_CHAR_TABLE4_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC2)
590 #define I3C_CORE_DEV_CHAR_TABLE4_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC3)
591 #define I3C_CORE_DEV_CHAR_TABLE4_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC4)
592 #define I3C_CORE_DEV_CHAR_TABLE5_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC1)
593 #define I3C_CORE_DEV_CHAR_TABLE5_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC2)
594 #define I3C_CORE_DEV_CHAR_TABLE5_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC3)
595 #define I3C_CORE_DEV_CHAR_TABLE5_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC4)
596 #define I3C_CORE_DEV_CHAR_TABLE6_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC1)
597 #define I3C_CORE_DEV_CHAR_TABLE6_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC2)
598 #define I3C_CORE_DEV_CHAR_TABLE6_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC3)
599 #define I3C_CORE_DEV_CHAR_TABLE6_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC4)
600 #define I3C_CORE_DEV_CHAR_TABLE7_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC1)
601 #define I3C_CORE_DEV_CHAR_TABLE7_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC2)
602 #define I3C_CORE_DEV_CHAR_TABLE7_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC3)
603 #define I3C_CORE_DEV_CHAR_TABLE7_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC4)
604 #define I3C_CORE_DEV_CHAR_TABLE8_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC1)
605 #define I3C_CORE_DEV_CHAR_TABLE8_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC2)
606 #define I3C_CORE_DEV_CHAR_TABLE8_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC3)
607 #define I3C_CORE_DEV_CHAR_TABLE8_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC4)
608 #define I3C_CORE_DEV_CHAR_TABLE9_LOC1(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC1)
609 #define I3C_CORE_DEV_CHAR_TABLE9_LOC2(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC2)
610 #define I3C_CORE_DEV_CHAR_TABLE9_LOC3(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC3)
611 #define I3C_CORE_DEV_CHAR_TABLE9_LOC4(base)             (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC4)
612 #define I3C_CORE_DEV_CHAR_TABLE10_LOC1(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC1)
613 #define I3C_CORE_DEV_CHAR_TABLE10_LOC2(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC2)
614 #define I3C_CORE_DEV_CHAR_TABLE10_LOC3(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC3)
615 #define I3C_CORE_DEV_CHAR_TABLE10_LOC4(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC4)
616 #define I3C_CORE_DEV_CHAR_TABLE11_LOC1(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC1)
617 #define I3C_CORE_DEV_CHAR_TABLE11_LOC2(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC2)
618 #define I3C_CORE_DEV_CHAR_TABLE11_LOC3(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC3)
619 #define I3C_CORE_DEV_CHAR_TABLE11_LOC4(base)            (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC4)
620 #define I3C_CORE_DEV_ADDR_TABLE_LOC1(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC1)
621 #define I3C_CORE_DEV_ADDR_TABLE_LOC2(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC2)
622 #define I3C_CORE_DEV_ADDR_TABLE_LOC3(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC3)
623 #define I3C_CORE_DEV_ADDR_TABLE_LOC4(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC4)
624 #define I3C_CORE_DEV_ADDR_TABLE_LOC5(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC5)
625 #define I3C_CORE_DEV_ADDR_TABLE_LOC6(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC6)
626 #define I3C_CORE_DEV_ADDR_TABLE_LOC7(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC7)
627 #define I3C_CORE_DEV_ADDR_TABLE_LOC8(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC8)
628 #define I3C_CORE_DEV_ADDR_TABLE_LOC9(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC9)
629 #define I3C_CORE_DEV_ADDR_TABLE_LOC10(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC10)
630 #define I3C_CORE_DEV_ADDR_TABLE_LOC11(base)                (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC11)
631 
632 /*******************************************************************************
633 *                EFUSE
634 ******************************************************************************/
635 
636 #define EFUSE_CTL(base)                              (((EFUSE_Type *) (base))->CTL)
637 #define EFUSE_TEST(base)                             (((EFUSE_Type *) (base))->TEST)
638 #define EFUSE_CMD(base)                              (((EFUSE_Type *) (base))->CMD)
639 #define EFUSE_CONFIG(base)                           (((EFUSE_Type *) (base))->CONFIG)
640 #define EFUSE_SEQ_DEFAULT(base)                      (((EFUSE_Type *) (base))->SEQ_DEFAULT)
641 #define EFUSE_SEQ_READ_CTL_0(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_0)
642 #define EFUSE_SEQ_READ_CTL_1(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_1)
643 #define EFUSE_SEQ_READ_CTL_2(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_2)
644 #define EFUSE_SEQ_READ_CTL_3(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_3)
645 #define EFUSE_SEQ_READ_CTL_4(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_4)
646 #define EFUSE_SEQ_READ_CTL_5(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_5)
647 #define EFUSE_SEQ_READ_CTL_6(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_6)
648 #define EFUSE_SEQ_READ_CTL_7(base)                   (((EFUSE_Type *) (base))->SEQ_READ_CTL_7)
649 #define EFUSE_SEQ_PROGRAM_CTL_0(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_0)
650 #define EFUSE_SEQ_PROGRAM_CTL_1(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_1)
651 #define EFUSE_SEQ_PROGRAM_CTL_2(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_2)
652 #define EFUSE_SEQ_PROGRAM_CTL_3(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_3)
653 #define EFUSE_SEQ_PROGRAM_CTL_4(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_4)
654 #define EFUSE_SEQ_PROGRAM_CTL_5(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_5)
655 #define EFUSE_SEQ_PROGRAM_CTL_6(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_6)
656 #define EFUSE_SEQ_PROGRAM_CTL_7(base)                (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_7)
657 #define EFUSE_BOOTROW(base)                          (((EFUSE_Type *) (base))->BOOTROW)
658 
659 /*******************************************************************************
660 *                FAULT
661 *******************************************************************************/
662 
663 #define FAULT_CTL(base)                         (((FAULT_STRUCT_Type *)(base))->CTL)
664 #define FAULT_STATUS(base)                      (((FAULT_STRUCT_Type *)(base))->STATUS)
665 #define FAULT_DATA(base)                        (((FAULT_STRUCT_Type *)(base))->DATA)
666 #define FAULT_PENDING0(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING0)
667 #define FAULT_PENDING1(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING1)
668 #define FAULT_PENDING2(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING2)
669 #define FAULT_MASK0(base)                       (((FAULT_STRUCT_Type *)(base))->MASK0)
670 #define FAULT_MASK1(base)                       (((FAULT_STRUCT_Type *)(base))->MASK1)
671 #define FAULT_MASK2(base)                       (((FAULT_STRUCT_Type *)(base))->MASK2)
672 #define FAULT_INTR(base)                        (((FAULT_STRUCT_Type *)(base))->INTR)
673 #define FAULT_INTR_SET(base)                    (((FAULT_STRUCT_Type *)(base))->INTR_SET)
674 #define FAULT_INTR_MASK(base)                   (((FAULT_STRUCT_Type *)(base))->INTR_MASK)
675 #define FAULT_INTR_MASKED(base)                 (((FAULT_STRUCT_Type *)(base))->INTR_MASKED)
676 
677 /**
678   * \brief Instances of Fault data register.
679   */
680 typedef enum
681 {
682     CY_SYSFAULT_MPU_0                =   0,     /* Bus master 0 MPU/SMPU. */
683     CY_SYSFAULT_MPU_1                =   1,     /* Bus master 1 MPU. See MPU_0 description. */
684     CY_SYSFAULT_MPU_2                =   2,     /* Bus master 2 MPU. See MPU_0 description. */
685     CY_SYSFAULT_MPU_3                =   3,     /* Bus master 3 MPU. See MPU_0 description. */
686     CY_SYSFAULT_MPU_4                =   4,     /* Bus master 4 MPU. See MPU_0 description. */
687     CY_SYSFAULT_MPU_5                =   5,     /* Bus master 5 MPU. See MPU_0 description. */
688     CY_SYSFAULT_MPU_6                =   6,     /* Bus master 6 MPU. See MPU_0 description. */
689     CY_SYSFAULT_MPU_7                =   7,     /* Bus master 7 MPU. See MPU_0 description. */
690     CY_SYSFAULT_MPU_8                =   8,     /* Bus master 8 MPU. See MPU_0 description. */
691     CY_SYSFAULT_MPU_9                =   9,     /* Bus master 9 MPU. See MPU_0 description. */
692     CY_SYSFAULT_MPU_10               =  10,     /* Bus master 10 MPU. See MPU_0 description. */
693     CY_SYSFAULT_MPU_11               =  11,     /* Bus master 11 MPU. See MPU_0 description. */
694     CY_SYSFAULT_MPU_12               =  12,     /* Bus master 12 MPU. See MPU_0 description. */
695     CY_SYSFAULT_MPU_13               =  13,     /* Bus master 13 MPU. See MPU_0 description. */
696     CY_SYSFAULT_MPU_14               =  14,     /* Bus master 14 MPU. See MPU_0 description. */
697     CY_SYSFAULT_MPU_15               =  15,     /* Bus master 15 MPU. See MPU_0 description. */
698     CY_SYSFAULT_CM4_SYS_MPU          =  16,     /* CM4 system bus AHB-Lite interface MPU. See MPU_0 description. */
699     CY_SYSFAULT_CM4_CODE_MPU         =  17,     /* CM4 code bus AHB-Lite interface MPU for non flash controller accesses. See MPU_0 description. */
700     CM4_CODE_FLASHC_MPU              =  18,     /* CM4 code bus AHB-Lite interface MPU for flash controller accesses. See MPU_0 description. */
701     CY_SYSFAULT_MS_PPU_4             =  25,     /* Peripheral interconnect, master interface 4 PPU. See MS_PPU_0 description. */
702     CY_SYSFAULT_PERI_ECC             =  26,     /* Peripheral interconnect, protection structures SRAM, correctable ECC error: */
703     CY_SYSFAULT_PERI_NC_ECC          =  27,     /* Peripheral interconnect, protection structures SRAM, non-correctable ECC error. */
704     CY_SYSFAULT_MS_PPU_0             =  28,     /* Peripheral interconnect, master interface 0 PPU. */
705     CY_SYSFAULT_MS_PPU_1             =  29,     /* Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description. */
706     CY_SYSFAULT_MS_PPU_2             =  30,     /* Peripheral interconnect, master interface 2 PPU. See MS_PPU_0 description. */
707     CY_SYSFAULT_MS_PPU_3             =  31,     /* Peripheral interconnect, master interface 3 PPU. See MS_PPU_0 description. */
708     CY_SYSFAULT_GROUP_FAULT_0        =  32,     /* Peripheral group 0 fault detection. */
709     CY_SYSFAULT_GROUP_FAULT_1        =  33,     /* Peripheral group 1 fault detection. See GROUP_FAULT_0 description. */
710     CY_SYSFAULT_GROUP_FAULT_2        =  34,     /* Peripheral group 2 fault detection. See GROUP_FAULT_0 description. */
711     CY_SYSFAULT_GROUP_FAULT_3        =  35,     /* Peripheral group 3 fault detection. See GROUP_FAULT_0 description. */
712     CY_SYSFAULT_GROUP_FAULT_4        =  36,     /* Peripheral group 4 fault detection. See GROUP_FAULT_0 description. */
713     CY_SYSFAULT_GROUP_FAULT_5        =  37,     /* Peripheral group 5 fault detection. See GROUP_FAULT_0 description. */
714     CY_SYSFAULT_GROUP_FAULT_6        =  38,     /* Peripheral group 6 fault detection. See GROUP_FAULT_0 description. */
715     CY_SYSFAULT_GROUP_FAULT_7        =  39,     /* Peripheral group 7 fault detection. See GROUP_FAULT_0 description. */
716     CY_SYSFAULT_GROUP_FAULT_8        =  40,     /* Peripheral group 8 fault detection. See GROUP_FAULT_0 description. */
717     CY_SYSFAULT_GROUP_FAULT_9        =  41,     /* Peripheral group 9 fault detection. See GROUP_FAULT_0 description. */
718     CY_SYSFAULT_GROUP_FAULT_10       =  42,     /* Peripheral group 10 fault detection. See GROUP_FAULT_0 description. */
719     CY_SYSFAULT_GROUP_FAULT_11       =  43,     /* Peripheral group 11 fault detection. See GROUP_FAULT_0 description. */
720     CY_SYSFAULT_GROUP_FAULT_12       =  44,     /* Peripheral group 12 fault detection. See GROUP_FAULT_0 description. */
721     CY_SYSFAULT_GROUP_FAULT_13       =  45,     /* Peripheral group 13 fault detection. See GROUP_FAULT_0 description. */
722     CY_SYSFAULT_GROUP_FAULT_14       =  46,     /* Peripheral group 14 fault detection. See GROUP_FAULT_0 description. */
723     CY_SYSFAULT_GROUP_FAULT_15       =  47,     /* Peripheral group 15 fault detection. See GROUP_FAULT_0 description. */
724     CY_SYSFAULT_FLASHC_MAIN_BUS_ERROR  =  48,   /* Flash controller, main interface, bus error: */
725     CY_SYSFAULT_FLASHC_MAIN_C_ECC    =  49,     /* Flash controller, main interface, correctable ECC error: */
726     CY_SYSFAULT_FLASHC_MAIN_NC_ECC   =  50,     /* Flash controller, main interface, non-correctable ECC error.  See FLASHC_MAIN_C_ECC description. */
727     CY_SYSFAULT_FLASHC_WORK_BUS_ERROR  =  51,   /* Flash controller, work interface, bus error. See FLASHC_MAIN_BUS_ERROR description. */
728     CY_SYSFAULT_FLASHC_WORK_C_ECC    =  52,     /* Flash controller, work interface, correctable ECC error: */
729     CY_SYSFAULT_FLASHC_WORK_NC_ECC   =  53,     /* Flash controller, work interface, non-correctable ECC error. See FLASHC_WORK_C_ECC description. */
730     CY_SYSFAULT_FLASHC_CM0_CA_C_ECC  =  54,     /* Flash controller, CM0+ cache, correctable ECC error: */
731     CY_SYSFAULT_FLASHC_CM0_CA_NC_ECC  =  55,    /* Flash controller, CM0+ cache, non-correctable ECC error.  See FLASHC_CM0_CA_C_ECC description. */
732     CY_SYSFAULT_FLASHC_CM4_CA_C_ECC  =  56,     /* Flash controller, CM4 cache, correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */
733     CY_SYSFAULT_FLASHC_CM4_CA_NC_ECC =  57,     /* Flash controller, CM4 cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description.. */
734     CY_SYSFAULT_RAMC0_C_ECC          =  58,     /* System SRAM 0 correctable ECC error: */
735     CY_SYSFAULT_RAMC0_NC_ECC         =  59,     /* System SRAM 0 non-correctable ECC error.  See RAMC0_C_ECC description. */
736     CY_SYSFAULT_RAMC1_C_ECC          =  60,     /* System SRAM 1 correctable ECC error. See RAMC0_C_ECC description. */
737     CY_SYSFAULT_RAMC1_NC_ECC         =  61,     /* System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description. */
738     CY_SYSFAULT_RAMC2_C_ECC          =  62,     /* System SRAM 2 correctable ECC error. See RAMC0_C_ECC description. */
739     CY_SYSFAULT_RAMC2_NC_ECC         =  63,     /* System SRAM 2 non-correctable ECC error. See RAMC0_C_ECC description. */
740     CY_SYSFAULT_CRYPTO_C_ECC         =  64,     /* Cryptography SRAM correctable ECC error. */
741     CY_SYSFAULT_CRYPTO_NC_ECC        =  65,     /* Cryptography SRAM non-correctable ECC error. See CRYPTO_C_ECC description. */
742     CY_SYSFAULT_DW0_C_ECC            =  70,     /* DataWire 0 SRAM 1 correctable ECC error: */
743     CY_SYSFAULT_DW0_NC_ECC           =  71,     /* DataWire 0 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */
744     CY_SYSFAULT_DW1_C_ECC            =  72,     /* DataWire 1 SRAM 1 correctable ECC error. See DW0_C_ECC description. */
745     CY_SYSFAULT_DW1_NC_ECC           =  73,     /* DataWire 1 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */
746     CY_SYSFAULT_FM_SRAM_C_ECC        =  74,     /* eCT Flash SRAM (for embedded operations) correctable ECC error: */
747     CY_SYSFAULT_FM_SRAM_NC_ECC       =  75,     /* eCT Flash SRAM non-correctable ECC error: See FM_SRAM_C_ECC description. */
748     CY_SYSFAULT_CAN0_C_ECC           =  80,     /* CAN controller 0 MRAM correctable ECC error: */
749     CY_SYSFAULT_CAN0_NC_ECC          =  81,     /* CAN controller 0 MRAM non-correctable ECC error: */
750     CY_SYSFAULT_CAN1_C_ECC           =  82,     /* CAN controller 1 MRAM correctable ECC error. See CAN0_C_ECC description. */
751     CY_SYSFAULT_CAN1_NC_ECC          =  83,     /* CAN controller 1 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */
752     CY_SYSFAULT_CAN2_C_ECC           =  84,     /* CAN controller 2 MRAM correctable ECC error. See CAN0_C_ECC description.. */
753     CY_SYSFAULT_CAN2_NC_ECC          =  85,     /* CAN controller 2 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */
754     CY_SYSFAULT_SRSS_CSV             =  90,     /* SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. */
755     CY_SYSFAULT_SRSS_SSV             =  91,     /* SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. */
756     CY_SYSFAULT_SRSS_MCWDT0          =  92,     /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #0 violation detected. Multiple counters can detect a violation at the same time. */
757     CY_SYSFAULT_SRSS_MCWDT1          =  93,     /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #1 violation detected. See SRSS_MCWDT0 description. */
758     CY_SYSFAULT_SRSS_MCWDT2          =  94,     /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #2 violation detected. See SRSS_MCWDT0 description. */
759     CY_SYSFAULT_SRSS_MCWDT3          =  95,     /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #3 violation detected. See SRSS_MCWDT0 description. */
760     CY_SYSFAULT_NO_FAULT             =  96
761 } cy_en_SysFault_source_t;
762 
763 /*******************************************************************************
764 *                PROFILE
765 *******************************************************************************/
766 
767 
768 #define CY_EP_MONITOR_COUNT                 ((uint32_t)(cy_device->epMonitorNr))
769 #define CY_EP_CNT_NR                        (8UL)
770 #define PROFILE_CTL                         (((PROFILE_Type*) PROFILE_BASE)->CTL)
771 #define PROFILE_STATUS                      (((PROFILE_Type*) PROFILE_BASE)->STATUS)
772 #define PROFILE_CMD                         (((PROFILE_Type*) PROFILE_BASE)->CMD)
773 #define PROFILE_INTR                        (((PROFILE_Type*) PROFILE_BASE)->INTR)
774 #define PROFILE_INTR_MASK                   (((PROFILE_Type*) PROFILE_BASE)->INTR_MASK)
775 #define PROFILE_INTR_MASKED                 (((PROFILE_Type*) PROFILE_BASE)->INTR_MASKED)
776 #define PROFILE_CNT_STRUCT                  (((PROFILE_Type*) PROFILE_BASE)->CNT_STRUCT)
777 
778 /*******************************************************************************
779 *                SRSS
780 *******************************************************************************/
781 
782 #define CY_SRSS_NUM_PLL400M                 0
783 #define CY_SRSS_PLL400M_PRESENT             0
784 #if defined (CY_DEVICE_BOY2)
785 #define CY_SRSS_DPLL_LP_PRESENT             SRSS_NUM_DPLL250
786 #define SRSS_NUM_DPLL_LP                    SRSS_NUM_DPLL250
787 #define CY_SYSCLK_HF_MAX_FREQ(hfNum)        (240000000U)
788 #define CY_MXS40SSRSS_VER_1_2               1UL
789 #define SRSS_DPLL_LP_FRAC_BIT_COUNT         (24ULL)
790 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV       SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT
791 #define PWRMODE_PWR_SELECT                  (((PWRMODE_Type *) PWRMODE)->CLK_SELECT)
792 #define SRSS_CLK_DPLL_LP_CONFIG(pllNum)     (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG)
793 #define SRSS_CLK_DPLL_LP_CONFIG2(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG2)
794 #define SRSS_CLK_DPLL_LP_CONFIG3(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG3)
795 #define SRSS_CLK_DPLL_LP_CONFIG4(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG4)
796 #define SRSS_CLK_DPLL_LP_CONFIG5(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG5)
797 #define SRSS_CLK_DPLL_LP_CONFIG6(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG6)
798 #define SRSS_CLK_DPLL_LP_CONFIG7(pllNum)    (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG7)
799 #define SRSS_CLK_DPLL_LP_STATUS(pllNum)     (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].STATUS)
800 #else
801 #define CY_SRSS_DPLL_LP_PRESENT             0
802 #define CY_MXS40SSRSS_VER_1_2               0UL
803 #endif
804 #define CY_SRSS_NUM_CLKPATH                 SRSS_NUM_CLKPATH
805 #define CY_SRSS_NUM_PLL                     SRSS_NUM_TOTAL_PLL
806 #define CY_SRSS_NUM_HFROOT                  SRSS_NUM_HFROOT
807 #define CY_SRSS_ECO_PRESENT                 SRSS_ECO_PRESENT
808 #define CY_SRSS_FLL_PRESENT                 SRSS_FLL_PRESENT
809 #define CY_SRSS_PLL_PRESENT                 SRSS_NUM_TOTAL_PLL
810 #define CY_SRSS_ALTHF_PRESENT               SRSS_ALTHF_PRESENT
811 
812 #if defined (CY_IP_MXS28SRSS)
813 #define CY_SRSS_IHO_PRESENT                 0
814 #define CY_SRSS_MFO_PRESENT                 0
815 #endif
816 
817 #if defined (CY_IP_MXS40SSRSS)
818 #define CY_SRSS_IHO_PRESENT                 1
819 #define CY_SRSS_MFO_PRESENT                 1
820 #define CY_SRSS_PILO_PRESENT                SRSS_S40S_PILO_PRESENT
821 #define CY_SRSS_ILO_PRESENT                 1
822 #define CY_SRSS_IMO_PRESENT                 1
823 #endif
824 
825 
826 /** HF PATH # used for PERI PCLK */
827 #define CY_SYSCLK_CLK_PERI_HF_PATH_NUM     1U
828 
829 /** HF PATH # used for Core */
830 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM     0U
831 
832 /** FLL Max Frequency */
833 #define  CY_SYSCLK_FLL_MAX_OUTPUT_FREQ     (96000000UL)
834 
835 
836 
837 /* HF PATH # Max Allowed Frequencies */
838 #define CY_SYSCLK_MAX_FREQ_HF0             96000000U
839 #define CY_SYSCLK_MAX_FREQ_HF1             96000000U
840 #define CY_SYSCLK_MAX_FREQ_HF2             48000000U
841 #define CY_SYSCLK_MAX_FREQ_HF3             24000000U
842 
843 
844 #if defined (CY_DEVICE_CYW20829)
845 #define CY_SYSCLK_HF_MAX_FREQ(hfNum)       (((hfNum) == 0U) ?  (CY_SYSCLK_MAX_FREQ_HF0) : \
846                                            (((hfNum) == 1U) ?  (CY_SYSCLK_MAX_FREQ_HF1) : \
847                                            (((hfNum) == 2U) ?  (CY_SYSCLK_MAX_FREQ_HF2) : \
848                                            (((hfNum) == 3U) ?  (CY_SYSCLK_MAX_FREQ_HF3) : \
849                                            (0U)))))
850 #endif
851 
852 /* Technology Independant Register set */
853 #define SRSS_CLK_DSI_SELECT                 (((SRSS_Type *) SRSS)->CLK_DSI_SELECT)
854 #define SRSS_CLK_OUTPUT_FAST                (((SRSS_Type *) SRSS)->CLK_OUTPUT_FAST)
855 #define SRSS_CLK_OUTPUT_SLOW                (((SRSS_Type *) SRSS)->CLK_OUTPUT_SLOW)
856 #define SRSS_CLK_CAL_CNT1                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT1)
857 #define SRSS_CLK_CAL_CNT2                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT2)
858 #define SRSS_SRSS_INTR                      (((SRSS_Type *) SRSS)->SRSS_INTR)
859 #define SRSS_SRSS_INTR_SET                  (((SRSS_Type *) SRSS)->SRSS_INTR_SET)
860 #define SRSS_SRSS_INTR_MASK                 (((SRSS_Type *) SRSS)->SRSS_INTR_MASK)
861 #define SRSS_SRSS_INTR_MASKED               (((SRSS_Type *) SRSS)->SRSS_INTR_MASKED)
862 #define SRSS_SRSS_AINTR                     (((SRSS_Type *) SRSS)->SRSS_AINTR)
863 #define SRSS_SRSS_AINTR_SET                 (((SRSS_Type *) SRSS)->SRSS_AINTR_SET)
864 #define SRSS_SRSS_AINTR_MASK                (((SRSS_Type *) SRSS)->SRSS_AINTR_MASK)
865 #define SRSS_SRSS_AINTR_MASKED              (((SRSS_Type *) SRSS)->SRSS_AINTR_MASKED)
866 #define SRSS_PWR_CTL                        (((SRSS_Type *) SRSS)->PWR_CTL)
867 #define SRSS_PWR_CTL2                       (((SRSS_Type *) SRSS)->PWR_CTL2)
868 #define SRSS_PWR_HIBERNATE                  (((SRSS_Type *) SRSS)->PWR_HIBERNATE)
869 #define SRSS_PWR_CTL3                       (((SRSS_Type *) SRSS)->PWR_CTL3)
870 #define SRSS_PWR_STATUS                     (((SRSS_Type *) SRSS)->PWR_STATUS)
871 #define SRSS_PWR_HIB_DATA                   (((SRSS_Type *) SRSS)->PWR_HIB_DATA)
872 #define SRSS_CLK_PATH_SELECT                (((SRSS_Type *) SRSS)->CLK_PATH_SELECT)
873 #define SRSS_CLK_ROOT_SELECT                (((SRSS_Type *) SRSS)->CLK_ROOT_SELECT)
874 #define SRSS_CLK_DIRECT_SELECT              (((SRSS_Type *) SRSS)->CLK_DIRECT_SELECT)
875 #define SRSS_CLK_ECO_STATUS                 (((SRSS_Type *) SRSS)->CLK_ECO_STATUS)
876 #define SRSS_CLK_ILO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO_CONFIG)
877 #define SRSS_CLK_TRIM_ILO_CTL               (((SRSS_Type *) SRSS)->CLK_TRIM_ILO_CTL)
878 #define SRSS_CLK_PILO_CONFIG                (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG)
879 #define SRSS_CLK_ECO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG)
880 #define SRSS_CLK_ECO_CONFIG2                (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG2)
881 #define SRSS_CLK_MFO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_MFO_CONFIG)
882 #define SRSS_CLK_IHO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IHO_CONFIG)
883 #define SRSS_CLK_ALTHF_CTL                  (((SRSS_Type *) SRSS)->CLK_ALTHF_CTL)
884 
885 #if defined (CY_IP_MXS28SRSS)
886 #define SRSS_CLK_ILO_CONFIG2                (((SRSS_Type *) SRSS)->CLK_ILO_CONFIG2)
887 #define SRSS_CLK_PILO_CONFIG2               (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG2)
888 #endif
889 #define SRSS_CSV_HF                         (((SRSS_Type *) SRSS)->CSV_HF)
890 #define SRSS_CLK_SELECT                     (((SRSS_Type *) SRSS)->CLK_SELECT)
891 #define SRSS_CLK_TIMER_CTL                  (((SRSS_Type *) SRSS)->CLK_TIMER_CTL)
892 #define SRSS_CLK_IMO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IMO_CONFIG)
893 #define SRSS_CLK_ECO_PRESCALE               (((SRSS_Type *) SRSS)->CLK_ECO_PRESCALE)
894 #define SRSS_CLK_MF_SELECT                  (((SRSS_Type *) SRSS)->CLK_MF_SELECT)
895 #define SRSS_CSV_REF_SEL                    (((SRSS_Type *) SRSS)->CSV_REF_SEL)
896 #define SRSS_CSV_REF                        (((SRSS_Type *) SRSS)->CSV_REF)
897 #define SRSS_CSV_LF                         (((SRSS_Type *) SRSS)->CSV_LF)
898 #define SRSS_CSV_ILO                        (((SRSS_Type *) SRSS)->CSV_ILO)
899 #define SRSS_RES_CAUSE                      (((SRSS_Type *) SRSS)->RES_CAUSE)
900 #define SRSS_RES_CAUSE2                     (((SRSS_Type *) SRSS)->RES_CAUSE2)
901 #define SRSS_RES_CAUSE_EXTEND               (((SRSS_Type *) SRSS)->RES_CAUSE_EXTEND)
902 #define SRSS_PWR_CBUCK_CTL                  (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL)
903 #define SRSS_PWR_CBUCK_CTL2                 (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL2)
904 #define SRSS_PWR_CBUCK_CTL3                 (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL3)
905 #define SRSS_PWR_CBUCK_STATUS               (((SRSS_Type *) SRSS)->PWR_CBUCK_STATUS)
906 #define SRSS_PWR_SDR0_CTL                   (((SRSS_Type *) SRSS)->PWR_SDR0_CTL)
907 #define SRSS_PWR_SDR1_CTL                   (((SRSS_Type *) SRSS)->PWR_SDR1_CTL)
908 #define SRSS_PWR_HVLDO0_CTL                 (((SRSS_Type *) SRSS)->PWR_HVLDO0_CTL)
909 #define SRSS_CLK_LP_PLL                     (((SRSS_Type *) SRSS)->CLK_LP_PLL)
910 #define SRSS_CLK_IHO                        (((SRSS_Type *) SRSS)->CLK_IHO)
911 #define SRSS_TST_XRES_SECURE                (((SRSS_Type *) SRSS)->TST_XRES_SECURE)
912 #define SRSS_RES_PXRES_CTL                  (((SRSS_Type *) SRSS)->RES_PXRES_CTL)
913 #define SRSS_WDT_CTL                        (((SRSS_Type *) SRSS)->WDT_CTL)
914 #define SRSS_WDT_CNT                        (((SRSS_Type *) SRSS)->WDT_CNT)
915 #define SRSS_WDT_MATCH                      (((SRSS_Type *) SRSS)->WDT_MATCH)
916 #if defined (CY_IP_MXS40SSRSS)
917 #define SRSS_WDT_MATCH2                      (((SRSS_Type *) SRSS)->WDT_MATCH2)
918 #endif
919 
920 #if defined (CY_IP_MXS28SRSS)
921 #define SRSS_CLK_LP_PLL_CONFIG(pllNum)      (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG)
922 #define SRSS_CLK_LP_PLL_CONFIG2(pllNum)     (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG2)
923 #define SRSS_CLK_LP_PLL_CONFIG3(pllNum)     (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG3)
924 #define SRSS_CLK_LP_PLL_CONFIG4(pllNum)     (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG4)
925 #define SRSS_CLK_LP_PLL_CONFIG5(pllNum)     (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG5)
926 #define SRSS_CLK_LP_PLL_STATUS(pllNum)      (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.STATUS)
927 #endif
928 
929 #if defined (CY_IP_MXS40SSRSS)
930 #define SRSS_CLK_FLL_CONFIG                 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG)
931 #define SRSS_CLK_FLL_CONFIG2                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG2)
932 #define SRSS_CLK_FLL_CONFIG3                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3)
933 #define SRSS_CLK_FLL_CONFIG4                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4)
934 #define SRSS_CLK_FLL_STATUS                 (((SRSS_Type *) SRSS)->CLK_FLL_STATUS)
935 
936 #define SRSS_PWR_LVD_CTL                    (((SRSS_Type *) SRSS)->PWR_LVD_CTL)
937 #define SRSS_PWR_LVD_STATUS                 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS)
938 
939 #define SRSS_PWR_HIB_WAKE_CTL               (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL)
940 #define SRSS_PWR_HIB_WAKE_CTL2              (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL2)
941 #define SRSS_PWR_HIB_WAKE_CAUSE             (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CAUSE)
942 #define SRSS_RES_SOFT_CTL                   (((SRSS_Type *) SRSS)->RES_SOFT_CTL)
943 #endif
944 
945 #define SRSS_TST_DDFT_FAST_CTL_REG          (*(volatile uint32_t *) 0x40201104U)
946 #define SRSS_TST_DDFT_SLOW_CTL_REG          (*(volatile uint32_t *) 0x40201108U)
947 
948 #define SRSS_TST_DDFT_SLOW_CTL_MASK         (0x00001F1EU)
949 #define SRSS_TST_DDFT_FAST_CTL_MASK         (62U)
950 
951 #if defined (CY_IP_MXS40SSRSS)
952 /* PPU configurations for DEEPSLEEP */
953 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE        PPU_V1_MODE_FULL_RET
954 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_MODE       PPU_V1_MODE_FULL_RET
955 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_MODE        PPU_V1_MODE_MEM_RET
956 
957 /* PPU configurations for DEEPSLEEP-RAM */
958 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE    PPU_V1_MODE_MEM_RET
959 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_RAM_MODE   PPU_V1_MODE_OFF
960 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_RAM_MODE    PPU_V1_MODE_MEM_RET
961 
962 /* PPU configurations for DEEPSLEEP-OFF */
963 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE    PPU_V1_MODE_OFF
964 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_OFF_MODE   PPU_V1_MODE_OFF
965 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_OFF_MODE    PPU_V1_MODE_OFF
966 
967 /* System DEEPSLEEP Mode = (PPU_MAIN Mode)*/
968 #define CY_SYSTEM_DEEPSLEEP_PPU_MODES        ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE)
969 #define CY_SYSTEM_DEEPSLEEP_RAM_PPU_MODES    ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE)
970 #define CY_SYSTEM_DEEPSLEEP_OFF_PPU_MODES    ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE)
971 #endif
972 
973 
974 /*******************************************************************************
975 *                PERI
976 *******************************************************************************/
977 /*******************************************************************************
978 *                PERI PCLK
979 *******************************************************************************/
980 
981 #define PERI_INSTANCE_COUNT                    (1U)
982 
983 #ifndef PERI0_PCLK_GROUP_NR
984 #define PERI0_PCLK_GROUP_NR     PERI_PCLK_GROUP_NR
985 #endif
986 
987 #ifndef PERI1_PCLK_GROUP_NR
988 #define PERI1_PCLK_GROUP_NR     (0U)
989 #endif
990 
991 
992 #ifndef PERI_PCLK0_BASE
993 #define PERI_PCLK0_BASE     PERI_PCLK_BASE
994 #endif
995 
996 #ifndef PERI_PCLK1_BASE
997 #define PERI_PCLK1_BASE     0U
998 #endif
999 
1000 #if (PERI_INSTANCE_COUNT == 1U)
1001 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
1002 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
1003 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT
1004 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT
1005 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT
1006 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT
1007 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT
1008 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1009 
1010 
1011 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
1012 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
1013 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT
1014 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT
1015 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT
1016 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT
1017 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT
1018 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1019 
1020 
1021 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT
1022 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT
1023 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT
1024 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT
1025 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT
1026 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT
1027 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT
1028 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1029 
1030 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
1031 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
1032 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT
1033 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT
1034 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT
1035 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT
1036 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT
1037 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1038 
1039 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0U
1040 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 0U
1041 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1042 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1043 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1044 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1045 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1046 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1047 
1048 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0U
1049 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 0U
1050 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1051 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1052 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1053 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1054 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1055 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1056 
1057 
1058 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0U
1059 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0U
1060 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1061 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1062 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1063 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1064 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1065 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1066 
1067 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 0U
1068 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 0U
1069 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1070 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1071 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1072 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1073 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1074 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1075 
1076 #endif
1077 
1078 #define PERI_PCLK_PERI_NUM_Msk                 (0x000000FFU)
1079 #define PERI_PCLK_GR_NUM_Msk                   (0x0000FF00U)
1080 #define PERI_PCLK_GR_NUM_Pos                   (8U)
1081 #define PERI_PCLK_PERIPHERAL_GROUP_NUM         (1UL << PERI_PCLK_GR_NUM_Pos)
1082 #define PERI_PCLK_INST_NUM_Msk                 (0x00FF0000U)
1083 #define PERI_PCLK_INST_NUM_Pos                 (16U)
1084 
1085 #define PERI_PCLK_GR_NUM(instNum)              (((instNum) == 0U)? PERI0_PCLK_GROUP_NR : PERI1_PCLK_GROUP_NR)
1086 
1087 #define PERI_PCLK1_OFFSET                      (PERI_PCLK1_BASE - PERI_PCLK0_BASE)
1088 #define PERI_PCLK_REG_BASE(instNum)            ((PERI_PCLK_Type*)(PERI_PCLK0_BASE + ((instNum) * PERI_PCLK1_OFFSET)))
1089 
1090 #define PERI_DIV_8_CTL(instNum, grNum, divNum)                   ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_8_CTL[divNum]
1091 #define PERI_DIV_16_CTL(instNum, grNum, divNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_CTL[divNum]
1092 #define PERI_DIV_16_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_5_CTL[divNum]
1093 #define PERI_DIV_24_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_24_5_CTL[divNum]
1094 #define PERI_CLOCK_CTL(instNum, grNum, periNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1095 #define PERI_DIV_CMD(instNum, grNum)                             ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_CMD
1096 
1097 #define PERI_DIV_8_NR(instNum, grNum)           (((instNum) == 0U) ? \
1098                                                   (((grNum) <= 3U) ? \
1099                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1100                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)         |    \
1101                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)        |    \
1102                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1103                                                   : \
1104                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |        \
1105                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1106                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1107                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1108                                                   : \
1109                                                   (((grNum) <= 3U) ? \
1110                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1111                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)          |    \
1112                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)         |    \
1113                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1114                                                   : \
1115                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |         \
1116                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1117                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1118                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1119 
1120 #define PERI_DIV_16_NR(instNum, grNum)           (((instNum) == 0U) ? \
1121                                                   (((grNum) <= 3U) ? \
1122                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |      \
1123                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)         |    \
1124                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)        |    \
1125                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1126                                                   : \
1127                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1128                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1129                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1130                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1131                                                   : \
1132                                                   (((grNum) <= 3U) ? \
1133                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |       \
1134                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)          |    \
1135                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)         |    \
1136                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1137                                                   : \
1138                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1139                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1140                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1141                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1142 
1143 #define PERI_DIV_16_5_NR(instNum, grNum)         (((instNum) == 0U) ? \
1144                                                   (((grNum) <= 3U) ? \
1145                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |          \
1146                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)    |    \
1147                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)    |    \
1148                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1149                                                   : \
1150                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1151                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1152                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1153                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1154                                                   : \
1155                                                   (((grNum) <= 3U) ? \
1156                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |       \
1157                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)          |    \
1158                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)         |    \
1159                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1160                                                   : \
1161                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1162                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1163                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1164                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1165 
1166 #define PERI_DIV_24_5_NR(instNum, grNum)         (((instNum) == 0U) ? \
1167                                                   (((grNum) <= 3U) ? \
1168                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) |      \
1169                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)         |    \
1170                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)        |    \
1171                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1172                                                   : \
1173                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1174                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1175                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1176                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1177                                                   : \
1178                                                   (((grNum) <= 3U) ? \
1179                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |       \
1180                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)          |    \
1181                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)         |    \
1182                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1183                                                   : \
1184                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1185                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1186                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1187                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1188 
1189 /* PERI_PCLK_GR.DIV_CMD */
1190 #define CY_PERI_DIV_CMD_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1191 #define CY_PERI_DIV_CMD_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1192 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1193 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1194 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1195 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1196 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1197 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1198 #define CY_PERI_DIV_CMD_DISABLE_Pos             PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1199 #define CY_PERI_DIV_CMD_DISABLE_Msk             PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1200 #define CY_PERI_DIV_CMD_ENABLE_Pos              PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1201 #define CY_PERI_DIV_CMD_ENABLE_Msk              PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1202 
1203 
1204 #define PERI_DIV_CMD_DIV_SEL_Pos                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1205 #define PERI_DIV_CMD_DIV_SEL_Msk                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1206 #define PERI_DIV_CMD_TYPE_SEL_Pos               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1207 #define PERI_DIV_CMD_TYPE_SEL_Msk               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1208 #define PERI_DIV_CMD_PA_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1209 #define PERI_DIV_CMD_PA_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1210 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1211 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1212 #define PERI_DIV_CMD_DISABLE_Pos                PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1213 #define PERI_DIV_CMD_DISABLE_Msk                PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1214 #define PERI_DIV_CMD_ENABLE_Pos                 PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1215 #define PERI_DIV_CMD_ENABLE_Msk                 PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1216 
1217 /* PERI_PCLK_GR.CLOCK_CTL */
1218 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos
1219 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk
1220 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos
1221 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk
1222 /* PERI.DIV_8_CTL */
1223 #define PERI_DIV_8_CTL_EN_Pos                   PERI_PCLK_GR_DIV_8_CTL_EN_Pos
1224 #define PERI_DIV_8_CTL_EN_Msk                   PERI_PCLK_GR_DIV_8_CTL_EN_Msk
1225 #define PERI_DIV_8_CTL_INT8_DIV_Pos             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos
1226 #define PERI_DIV_8_CTL_INT8_DIV_Msk             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk
1227 /* PERI.DIV_16_CTL */
1228 #define PERI_DIV_16_CTL_EN_Pos                  PERI_PCLK_GR_DIV_16_CTL_EN_Pos
1229 #define PERI_DIV_16_CTL_EN_Msk                  PERI_PCLK_GR_DIV_16_CTL_EN_Msk
1230 #define PERI_DIV_16_CTL_INT16_DIV_Pos           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos
1231 #define PERI_DIV_16_CTL_INT16_DIV_Msk           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk
1232 /* PERI.DIV_16_5_CTL */
1233 #define PERI_DIV_16_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos
1234 #define PERI_DIV_16_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk
1235 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos
1236 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk
1237 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos
1238 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk
1239 /* PERI.DIV_24_5_CTL */
1240 #define PERI_DIV_24_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos
1241 #define PERI_DIV_24_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk
1242 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos
1243 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk
1244 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos
1245 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk
1246 
1247 /*******************************************************************************
1248 *                PERI-GROUP
1249 *******************************************************************************/
1250 #if defined (CY_DEVICE_BOY2)
1251 #define CY_PERI_GROUP_NR                        6
1252 #else
1253 #define CY_PERI_GROUP_NR                        4
1254 #define CY_PERI_BLESS_GROUP_NR                  3
1255 #endif /* CY_DEVICE_BOY2 */
1256 
1257 #ifndef PERI0_BASE
1258 #define PERI0_BASE PERI_BASE
1259 #endif
1260 
1261 #ifndef PERI1_BASE
1262 #define PERI1_BASE 0U
1263 #endif
1264 
1265 
1266 #define PERI_GR_OFFSET                      (PERI1_BASE - PERI0_BASE)
1267 #define PERI_GR_REG_BASE(instNum)           ((PERI_Type*)(PERI0_BASE + ((instNum) * PERI_GR_OFFSET)))
1268 
1269 #define PERI_GR_INST_NUM_Msk                 (0x0000FF00U)
1270 #define PERI_GR_INST_NUM_Pos                 (8U)
1271 
1272 
1273 #define PERI_GR_CLOCK_CTL(instNum, grNum)   ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1274 #define PERI_GR_SL_CTL(instNum, grNum)      ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL
1275 #define PERI_GR_SL_CTL2(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL2
1276 #define PERI_GR_SL_CTL3(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL3
1277 
1278 /*******************************************************************************
1279 *                PERI-TR
1280 *******************************************************************************/
1281 
1282 #define PERI_TR_CMD                         (((PERI_Type*) (PERI_BASE))->TR_CMD)
1283 #define PERI_TR_GR_TR_CTL(group, trCtl)     (*(volatile uint32_t*) ((uint32_t)PERI_BASE+ (uint32_t)offsetof(PERI_Type,TR_GR) + \
1284                                             ((group) * (uint32_t)sizeof(PERI_TR_GR_Type)) + \
1285                                             ((trCtl) * (uint32_t)sizeof(uint32_t))))
1286 
1287 #if defined (CY_IP_MXSPERI)
1288 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1289 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1290 #define CY_PERI_TR_CTL_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1291 #define CY_PERI_TR_CTL_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1292 #define PERI_V2_TR_CMD_OUT_SEL_Msk PERI_TR_CMD_OUT_SEL_Msk
1293 #define PERI_V2_TR_CMD_OUT_SEL_Pos PERI_TR_CMD_OUT_SEL_Pos
1294 #define PERI_V2_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1295 #define PERI_V2_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1296 #define CY_PERI_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1297 #define CY_PERI_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1298 #define CY_PERI_TR_CTL_SEL PERI_TR_GR_TR_CTL_TR_SEL
1299 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk PERI_TR_GR_TR_CTL_TR_INV_Msk
1300 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos PERI_TR_GR_TR_CTL_TR_INV_Pos
1301 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk PERI_TR_GR_TR_CTL_TR_EDGE_Msk
1302 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos PERI_TR_GR_TR_CTL_TR_EDGE_Pos
1303 #define PERI_V2_TR_CMD_TR_EDGE_Msk PERI_TR_CMD_TR_EDGE_Msk
1304 #define PERI_V2_TR_CMD_TR_EDGE_Pos PERI_TR_CMD_TR_EDGE_Pos
1305 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk
1306 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos
1307 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk
1308 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos
1309 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk
1310 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos
1311 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk
1312 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos
1313 #define CY_PERI_V1 0U
1314 #define PERI_TR_CMD_COUNT_Pos 0UL
1315 #define PERI_TR_CMD_COUNT_Msk 0UL
1316 #endif /* CY_IP_MXSPERI */
1317 
1318 /* CLK_HF* to PERI PCLK Group Mapping */
1319 #define PERI0_PCLK_GR_NUM_0_CLK_HF_NUM              (0U)
1320 #define PERI0_PCLK_GR_NUM_1_CLK_HF_NUM              (1U)
1321 #define PERI0_PCLK_GR_NUM_2_CLK_HF_NUM              (0U)
1322 #define PERI0_PCLK_GR_NUM_3_CLK_HF_NUM              (1U)
1323 #define PERI0_PCLK_GR_NUM_4_CLK_HF_NUM              (2U)
1324 #define PERI0_PCLK_GR_NUM_5_CLK_HF_NUM              (3U)
1325 #if defined (CY_DEVICE_BOY2)
1326 #define PERI0_PCLK_GR_NUM_6_CLK_HF_NUM              (4U)
1327 #else
1328 #define PERI0_PCLK_GR_NUM_6_CLK_HF_NUM              (1U)
1329 #endif
1330 
1331 
1332 #if defined (CY_IP_MXS40SSRSS)
1333 #define CY_SYSPM_BOOTROM_ENTRYPOINT_ADDR        ((uint32_t)(&BACKUP_BREG_SET1[0])) /* Boot ROM will check this address for locating the entry point after Warm Boot */
1334 #define CY_SYSPM_BOOTROM_DSRAM_DBG_ENABLE_MASK 0x00000001U
1335 #endif
1336 #ifndef BOY2_PSVP
1337 #define ENABLE_MEM_VOLTAGE_TRIMS
1338 #endif
1339 
1340 
1341 /*******************************************************************************
1342 *                MXCM33
1343 *******************************************************************************/
1344 #define MXCM33_CM33_NMI_CTL(nmi)              (((volatile uint32_t *) (MXCM33->CM33_NMI_CTL))[(nmi)])
1345 
1346 /*******************************************************************************
1347 *                MCWDT
1348 *******************************************************************************/
1349 
1350 #define MCWDT_CNTLOW(base)      (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTLOW)
1351 #define MCWDT_CNTHIGH(base)     (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTHIGH)
1352 #define MCWDT_MATCH(base)       (((MCWDT_STRUCT_Type *)(base))->MCWDT_MATCH)
1353 #define MCWDT_CONFIG(base)      (((MCWDT_STRUCT_Type *)(base))->MCWDT_CONFIG)
1354 #define MCWDT_CTL(base)         (((MCWDT_STRUCT_Type *)(base))->MCWDT_CTL)
1355 #define MCWDT_INTR(base)        (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR)
1356 #define MCWDT_INTR_SET(base)    (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_SET)
1357 #define MCWDT_INTR_MASK(base)   (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASK)
1358 #define MCWDT_INTR_MASKED(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASKED)
1359 #define MCWDT_LOCK(base)        (((MCWDT_STRUCT_Type *)(base))->MCWDT_LOCK)
1360 #define MCWDT_LOWER_LIMIT(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_LOWER_LIMIT)
1361 
1362 
1363 
1364 /*******************************************************************************
1365 *                CPUSS
1366 *******************************************************************************/
1367 #define CPUSS_SYSTICK_NS_CTL                (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_NS_CTL)
1368 #define CPUSS_SYSTICK_S_CTL                 (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_S_CTL)
1369 #define CPUSS_TRIM_RAM_CTL                  (((CPUSS_Type*) CPUSS_BASE)->TRIM_RAM_CTL)
1370 #define CPUSS_TRIM_ROM_CTL                  (((CPUSS_Type*) CPUSS_BASE)->TRIM_ROM_CTL)
1371 
1372 #define CPUSS_PRODUCT_ID                    (((CPUSS_Type*) CPUSS_BASE)->PRODUCT_ID)
1373 
1374 
1375 /* ARM core registers */
1376 #define SYSTICK_CTRL                        (((SysTick_Type *)SysTick)->CTRL)
1377 #define SYSTICK_LOAD                        (((SysTick_Type *)SysTick)->LOAD)
1378 #define SYSTICK_VAL                         (((SysTick_Type *)SysTick)->VAL)
1379 #define SYSTICK_NS_CTRL                     (((SysTick_Type *)SysTick_NS)->CTRL)
1380 #define SYSTICK_NS_LOAD                     (((SysTick_Type *)SysTick_NS)->LOAD)
1381 #define SYSTICK_NS_VAL                      (((SysTick_Type *)SysTick_NS)->VAL)
1382 #define SCB_SCR                             (((SCB_Type *)SCB)->SCR)
1383 
1384 /*******************************************************************************
1385 *                TCPWM
1386 *******************************************************************************/
1387 
1388 #define TCPWM_CTRL_SET(base)                (((TCPWM_Type *)(base))->CTRL_SET)
1389 #define TCPWM_CTRL_CLR(base)                (((TCPWM_Type *)(base))->CTRL_CLR)
1390 #define TCPWM_CMD_START(base)               (((TCPWM_Type *)(base))->CMD_START)
1391 #define TCPWM_CMD_RELOAD(base)              (((TCPWM_Type *)(base))->CMD_RELOAD)
1392 #define TCPWM_CMD_STOP(base)                (((TCPWM_Type *)(base))->CMD_STOP)
1393 #define TCPWM_CMD_CAPTURE(base)             (((TCPWM_Type *)(base))->CMD_CAPTURE)
1394 
1395 #define TCPWM_CNT_CTRL(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].CTRL)
1396 #define TCPWM_CNT_CC(base, cntNum)           (((TCPWM_Type *)(base))->CNT[cntNum].CC)
1397 #define TCPWM_CNT_CC_BUFF(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].CC_BUFF)
1398 #define TCPWM_CNT_COUNTER(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].COUNTER)
1399 #define TCPWM_CNT_PERIOD(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD)
1400 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD_BUFF)
1401 #define TCPWM_CNT_STATUS(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].STATUS)
1402 #define TCPWM_CNT_INTR(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].INTR)
1403 #define TCPWM_CNT_INTR_SET(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].INTR_SET)
1404 #define TCPWM_CNT_INTR_MASK(base, cntNum)    (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASK)
1405 #define TCPWM_CNT_INTR_MASKED(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASKED)
1406 #define TCPWM_CNT_TR_CTRL0(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0)
1407 #define TCPWM_CNT_TR_CTRL1(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL1)
1408 #define TCPWM_CNT_TR_CTRL2(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2)
1409 
1410 #define TCPWM_GRP_CC1_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1)
1411 #define TCPWM_GRP_AMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1)
1412 #define TCPWM_GRP_SMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1)
1413 
1414 #define TCPWM_GRP_CC1(base, grp) ((bool)((TCPWM_GRP_CC1_PRESENT_STATUS >> (grp)) & 0x01U))
1415 #define TCPWM_GRP_AMC(base, grp) ((bool)((TCPWM_GRP_AMC_PRESENT_STATUS >> (grp)) & 0x01U))
1416 #define TCPWM_GRP_SMC(base, grp) ((bool)((TCPWM_GRP_SMC_PRESENT_STATUS >> (grp)) & 0x01U))
1417 
1418 #define TCPWM_GRP_CNT_GET_GRP(cntNum)        ((cntNum )/ 256U)
1419 
1420 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL)
1421 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS)
1422 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum)        (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER)
1423 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0)
1424 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF)
1425 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1)
1426 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF)
1427 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD)
1428 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF)
1429 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL)
1430 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum)  (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF)
1431 #define TCPWM_GRP_CNT_DT(base, grp, cntNum)             (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT)
1432 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD)
1433 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0)
1434 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1)
1435 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL)
1436 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL)
1437 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL)
1438 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR)
1439 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET)
1440 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum)      (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK)
1441 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED)
1442 
1443 #if (CY_IP_MXTCPWM_VERSION >= 2U)
1444 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos
1445 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk
1446 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos
1447 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk
1448 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos
1449 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk
1450 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos
1451 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk
1452 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos
1453 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk
1454 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos
1455 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk
1456 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos
1457 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk
1458 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos
1459 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk
1460 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos
1461 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk
1462 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos
1463 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk
1464 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos
1465 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk
1466 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos
1467 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk
1468 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos
1469 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk
1470 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos
1471 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk
1472 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos
1473 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk
1474 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos          TCPWM_GRP_CNT_CTRL_MODE_Pos
1475 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk          TCPWM_GRP_CNT_CTRL_MODE_Msk
1476 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos
1477 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk
1478 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos       TCPWM_GRP_CNT_CTRL_ENABLED_Pos
1479 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk       TCPWM_GRP_CNT_CTRL_ENABLED_Msk
1480 /* TCPWM_GRP_CNT.STATUS */
1481 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos        TCPWM_GRP_CNT_STATUS_DOWN_Pos
1482 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk        TCPWM_GRP_CNT_STATUS_DOWN_Msk
1483 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos
1484 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk
1485 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos    TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos
1486 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk    TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk
1487 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos
1488 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk
1489 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos     TCPWM_GRP_CNT_STATUS_TR_STOP_Pos
1490 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk     TCPWM_GRP_CNT_STATUS_TR_STOP_Msk
1491 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos    TCPWM_GRP_CNT_STATUS_TR_START_Pos
1492 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk    TCPWM_GRP_CNT_STATUS_TR_START_Msk
1493 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos
1494 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk
1495 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos    TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos
1496 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk    TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk
1497 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos
1498 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk
1499 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos     TCPWM_GRP_CNT_STATUS_RUNNING_Pos
1500 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk     TCPWM_GRP_CNT_STATUS_RUNNING_Msk
1501 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos
1502 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk
1503 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos
1504 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk
1505 /* TCPWM_GRP_CNT.COUNTER */
1506 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos    TCPWM_GRP_CNT_COUNTER_COUNTER_Pos
1507 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk    TCPWM_GRP_CNT_COUNTER_COUNTER_Msk
1508 /* TCPWM_GRP_CNT.CC0 */
1509 #define TCPWM_GRP_CNT_V2_CC0_CC_Pos             TCPWM_GRP_CNT_CC0_CC_Pos
1510 #define TCPWM_GRP_CNT_V2_CC0_CC_Msk             TCPWM_GRP_CNT_CC0_CC_Msk
1511 /* TCPWM_GRP_CNT.CC0_BUFF */
1512 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos        TCPWM_GRP_CNT_CC0_BUFF_CC_Pos
1513 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk        TCPWM_GRP_CNT_CC0_BUFF_CC_Msk
1514 /* TCPWM_GRP_CNT.CC1 */
1515 #define TCPWM_GRP_CNT_V2_CC1_CC_Pos             TCPWM_GRP_CNT_CC1_CC_Pos
1516 #define TCPWM_GRP_CNT_V2_CC1_CC_Msk             TCPWM_GRP_CNT_CC1_CC_Msk
1517 /* TCPWM_GRP_CNT.CC1_BUFF */
1518 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos        TCPWM_GRP_CNT_CC1_BUFF_CC_Pos
1519 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk        TCPWM_GRP_CNT_CC1_BUFF_CC_Msk
1520 /* TCPWM_GRP_CNT.PERIOD */
1521 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos      TCPWM_GRP_CNT_PERIOD_PERIOD_Pos
1522 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk      TCPWM_GRP_CNT_PERIOD_PERIOD_Msk
1523 /* TCPWM_GRP_CNT.PERIOD_BUFF */
1524 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos
1525 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk
1526 /* TCPWM_GRP_CNT.LINE_SEL */
1527 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos
1528 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk
1529 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos
1530 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk
1531 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */
1532 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos
1533 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk
1534 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos
1535 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk
1536 /* TCPWM_GRP_CNT.DT */
1537 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos
1538 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk
1539 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos
1540 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk
1541 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos
1542 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk
1543 /* TCPWM_GRP_CNT.TR_CMD */
1544 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos
1545 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk
1546 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos      TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos
1547 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk      TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk
1548 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos        TCPWM_GRP_CNT_TR_CMD_STOP_Pos
1549 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk        TCPWM_GRP_CNT_TR_CMD_STOP_Msk
1550 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos       TCPWM_GRP_CNT_TR_CMD_START_Pos
1551 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk       TCPWM_GRP_CNT_TR_CMD_START_Msk
1552 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos
1553 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk
1554 /* TCPWM_GRP_CNT.TR_IN_SEL0 */
1555 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos
1556 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk
1557 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos
1558 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk
1559 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos
1560 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk
1561 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos
1562 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk
1563 /* TCPWM_GRP_CNT.TR_IN_SEL1 */
1564 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos
1565 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk
1566 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos
1567 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk
1568 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */
1569 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos
1570 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk
1571 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos
1572 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk
1573 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos
1574 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk
1575 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos
1576 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk
1577 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos
1578 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk
1579 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos
1580 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk
1581 /* TCPWM_GRP_CNT.TR_PWM_CTRL */
1582 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos
1583 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk
1584 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos
1585 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk
1586 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos
1587 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk
1588 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos
1589 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk
1590 /* TCPWM_GRP_CNT.TR_OUT_SEL */
1591 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos
1592 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk
1593 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos
1594 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk
1595 /* TCPWM_GRP_CNT.INTR */
1596 #define TCPWM_GRP_CNT_V2_INTR_TC_Pos            TCPWM_GRP_CNT_INTR_TC_Pos
1597 #define TCPWM_GRP_CNT_V2_INTR_TC_Msk            TCPWM_GRP_CNT_INTR_TC_Msk
1598 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos
1599 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk
1600 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos
1601 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk
1602 /* TCPWM_GRP_CNT.INTR_SET */
1603 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos        TCPWM_GRP_CNT_INTR_SET_TC_Pos
1604 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk        TCPWM_GRP_CNT_INTR_SET_TC_Msk
1605 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos
1606 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk
1607 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos
1608 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk
1609 /* TCPWM_GRP_CNT.INTR_MASK */
1610 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos       TCPWM_GRP_CNT_INTR_MASK_TC_Pos
1611 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk       TCPWM_GRP_CNT_INTR_MASK_TC_Msk
1612 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos
1613 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk
1614 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos
1615 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk
1616 /* TCPWM_GRP_CNT.INTR_MASKED */
1617 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos     TCPWM_GRP_CNT_INTR_MASKED_TC_Pos
1618 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk     TCPWM_GRP_CNT_INTR_MASKED_TC_Msk
1619 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos
1620 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk
1621 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos
1622 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk
1623 
1624 /* For backward compatibility, we set TCPWM_CNT_STATUS_RUNNING_Pos with TCPWM_GRP_CNT_V2_STATUS_RUNNING
1625 we need to define this for version 2 only. */
1626 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
1627 #endif
1628 
1629 #if (CY_IP_MXTCPWM_VERSION >= 3U)
1630 #define TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED_Pos   TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Pos
1631 #define TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED_Msk   TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Msk
1632 #define TCPWM_GRP_CNT_V3_CTRL_DITHEREN_Pos       TCPWM_GRP_CNT_CTRL_DITHEREN_Pos
1633 #define TCPWM_GRP_CNT_V3_CTRL_DITHEREN_Msk       TCPWM_GRP_CNT_CTRL_DITHEREN_Msk
1634 
1635 #define TCPWM_GRP_CNT_V3_LFSR_PLFSR_Pos          TCPWM_GRP_CNT_LFSR_PLFSR_Pos
1636 #define TCPWM_GRP_CNT_V3_LFSR_PLFSR_Msk          TCPWM_GRP_CNT_LFSR_PLFSR_Msk
1637 #define TCPWM_GRP_CNT_V3_LFSR_DLFSR_Pos          TCPWM_GRP_CNT_LFSR_DLFSR_Pos
1638 #define TCPWM_GRP_CNT_V3_LFSR_DLFSR_Msk          TCPWM_GRP_CNT_LFSR_DLFSR_Msk
1639 #define TCPWM_GRP_CNT_V3_LFSR_LIMITER_Pos        TCPWM_GRP_CNT_LFSR_LIMITER_Pos
1640 #define TCPWM_GRP_CNT_V3_LFSR_LIMITER_Msk        TCPWM_GRP_CNT_LFSR_LIMITER_Msk
1641 
1642 #define TCPWM_GRP_CNT_V3_ONE_GF_GF_DEPTH_Pos     TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Pos
1643 #define TCPWM_GRP_CNT_V3_ONE_GF_GF_DEPTH_Msk     TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Msk
1644 #define TCPWM_GRP_CNT_V3_ONE_GF_GFPS_DIV_Pos     TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Pos
1645 #define TCPWM_GRP_CNT_V3_ONE_GF_GFPS_DIV_Msk     TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Msk
1646 
1647 #define GRP0_DITHERING TCPWM_GRP_NR0_CNT_GRP_DITHERING_PRESENT
1648 #define GRP1_DITHERING TCPWM_GRP_NR1_CNT_GRP_DITHERING_PRESENT
1649 #define GRP2_DITHERING TCPWM_GRP_NR2_CNT_GRP_DITHERING_PRESENT
1650 #define TCPWM_GRP_DITHERING_PRESENT(grp) (((grp) == 0U)? GRP0_DITHERING : (((grp) == 1U)? GRP1_DITHERING : GRP2_DITHERING))
1651 
1652 #define TCPWM_GRP_CNT_LFSR(base, grp, cntNum)        (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LFSR)
1653 #define TCPWM_GRP_CNT_ONE_GF(base, grp, cntNum, onetoone_gf)      (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].ONE_GF[onetoone_gf])
1654 #define TCPWM_GF_FOR_GROUP_TRIGGER(base, gfNum)      (((TCPWM_Type *)(base))->TR_ALL_GF.ALL_GF[((gfNum) % 254U)])
1655 
1656 /* MOTIF */
1657 
1658 #define TCPWM_MOTIF_PCONF(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PCONF)
1659 #define TCPWM_MOTIF_PSUS(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PSUS)
1660 #define TCPWM_MOTIF_PRUNS(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PRUNS)
1661 #define TCPWM_MOTIF_PRUN(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PRUN)
1662 #define TCPWM_MOTIF_MDR(base)                 (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MDR)
1663 #define TCPWM_MOTIF_HIST(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HIST)
1664 #define TCPWM_MOTIF_HMEC(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HMEC)
1665 #define TCPWM_MOTIF_HALP(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HALP)
1666 #define TCPWM_MOTIF_HALPS(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HALPS)
1667 #define TCPWM_MOTIF_HOSC(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HOSC)
1668 #define TCPWM_MOTIF_MCM(base)                 (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCM)
1669 #define TCPWM_MOTIF_MCSM(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM)
1670 #define TCPWM_MOTIF_MCMS(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMS)
1671 #define TCPWM_MOTIF_MCMC(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMC)
1672 #define TCPWM_MOTIF_MCMF(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMF)
1673 #define TCPWM_MOTIF_MCPF(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCPF)
1674 #define TCPWM_MOTIF_MOSC(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MOSC)
1675 #define TCPWM_MOTIF_QDC(base)                 (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->QDC)
1676 #define TCPWM_MOTIF_QOSC(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->QOSC)
1677 #define TCPWM_MOTIF_MCMEC(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMEC)
1678 #define TCPWM_MOTIF_PFLG(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PFLG)
1679 #define TCPWM_MOTIF_PFLGE(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PFLGE)
1680 #define TCPWM_MOTIF_SPFLG(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->SPFLG)
1681 #define TCPWM_MOTIF_RPFLG(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->RPFLG)
1682 #define TCPWM_MOTIF_MCSM1(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM1)
1683 #define TCPWM_MOTIF_MCSM2(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM2)
1684 #define TCPWM_MOTIF_MCSM3(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM3)
1685 #define TCPWM_MOTIF_MCSM4(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM4)
1686 #define TCPWM_MOTIF_MCSM5(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM5)
1687 #define TCPWM_MOTIF_CLUT(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->CLUT)
1688 #define TCPWM_MOTIF_SLUT(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->SLUT)
1689 #define TCPWM_MOTIF_PDBG(base)                (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PDBG)
1690 #define TCPWM_MOTIF_PLP0S(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP0S)
1691 #define TCPWM_MOTIF_PLP1S(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP1S)
1692 #define TCPWM_MOTIF_PLP2S(base)               (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP2S)
1693 
1694 #ifndef TCPWM_TR_ONE_CNT_NR
1695 #define TCPWM_TR_ONE_CNT_NR TCPWM_CNT_TR_ONE_CNT_NR
1696 #endif
1697 #endif /* CY_IP_MXTCPWM_VERSION >= 3U */
1698 /*******************************************************************************
1699 *               TDM
1700 *******************************************************************************/
1701 
1702 #define TDM_STRUCT_Type                                TDM_TDM_STRUCT_Type
1703 #define TDM_TX_STRUCT_Type                            TDM_TDM_STRUCT_TDM_TX_STRUCT_Type
1704 #define TDM_RX_STRUCT_Type                            TDM_TDM_STRUCT_TDM_RX_STRUCT_Type
1705 #define TDM_STRUCT0                                 TDM0_TDM_STRUCT0
1706 #define TDM_STRUCT1                                 TDM0_TDM_STRUCT1
1707 #define TDM_STRUCT0_TX                                TDM0_TDM_STRUCT0_TDM_TX_STRUCT
1708 #define TDM_STRUCT1_TX                                TDM0_TDM_STRUCT1_TDM_TX_STRUCT
1709 #define TDM_STRUCT0_RX                                TDM0_TDM_STRUCT0_TDM_RX_STRUCT
1710 #define TDM_STRUCT1_RX                                TDM0_TDM_STRUCT1_TDM_RX_STRUCT
1711 #define TDM_STRUCT_TX_CTL(base)                     (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CTL)
1712 #define TDM_STRUCT_TX_IF_CTL(base)                     (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_IF_CTL)
1713 #define TDM_STRUCT_TX_CH_CTL(base)                     (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CH_CTL)
1714 #define TDM_STRUCT_TX_TEST_CTL(base)                 (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_TEST_CTL)
1715 #define TDM_STRUCT_TX_ROUTE_CTL(base)                 (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_ROUTE_CTL)
1716 #define TDM_STRUCT_TX_FIFO_CTL(base)                 (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_CTL)
1717 #define TDM_STRUCT_TX_FIFO_STATUS(base)             (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_STATUS)
1718 #define TDM_STRUCT_TX_FIFO_WR(base)                 (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_WR)
1719 #define TDM_STRUCT_TX_INTR_TX(base)                 (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX)
1720 #define TDM_STRUCT_TX_INTR_TX_SET(base)             (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_SET)
1721 #define TDM_STRUCT_TX_INTR_TX_MASK(base)             (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASK)
1722 #define TDM_STRUCT_TX_INTR_TX_MASKED(base)             (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASKED)
1723 
1724 #define TDM_STRUCT_RX_CTL(base)                     (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CTL)
1725 #define TDM_STRUCT_RX_IF_CTL(base)                     (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_IF_CTL)
1726 #define TDM_STRUCT_RX_CH_CTL(base)                     (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CH_CTL)
1727 #define TDM_STRUCT_RX_TEST_CTL(base)                 (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_TEST_CTL)
1728 #define TDM_STRUCT_RX_ROUTE_CTL(base)                 (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_ROUTE_CTL)
1729 #define TDM_STRUCT_RX_FIFO_CTL(base)                 (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_CTL)
1730 #define TDM_STRUCT_RX_FIFO_STATUS(base)             (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_STATUS)
1731 #define TDM_STRUCT_RX_FIFO_RD(base)                 (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD)
1732 #define TDM_STRUCT_RX_FIFO_RD_SILENT(base)             (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD_SILENT)
1733 #define TDM_STRUCT_RX_INTR_RX(base)                 (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX)
1734 #define TDM_STRUCT_RX_INTR_RX_SET(base)             (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_SET)
1735 #define TDM_STRUCT_RX_INTR_RX_MASK(base)             (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASK)
1736 #define TDM_STRUCT_RX_INTR_RX_MASKED(base)             (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASKED)
1737 
1738 
1739 /*******************************************************************************
1740 *                PDM
1741 *******************************************************************************/
1742 
1743 #define PDM_PCM_CTL(base)                               (((PDM_Type*)(base))->CTL)
1744 #define PDM_PCM_CTL_CLR(base)                           (((PDM_Type*)(base))->CTL_CLR)
1745 #define PDM_PCM_CTL_SET(base)                           (((PDM_Type*)(base))->CTL_SET)
1746 #define PDM_PCM_CLOCK_CTL(base)                           (((PDM_Type*)(base))->CLOCK_CTL)
1747 #define PDM_PCM_ROUTE_CTL(base)                           (((PDM_Type*)(base))->ROUTE_CTL)
1748 #define PDM_PCM_TEST_CTL(base)                           (((PDM_Type*)(base))->TEST_CTL)
1749 #define PDM_PCM_FIR0_COEFF0(base)                       (((PDM_Type*)(base))->FIR0_COEFF0)
1750 #define PDM_PCM_FIR0_COEFF1(base)                       (((PDM_Type*)(base))->FIR0_COEFF1)
1751 #define PDM_PCM_FIR0_COEFF2(base)                       (((PDM_Type*)(base))->FIR0_COEFF2)
1752 #define PDM_PCM_FIR0_COEFF3(base)                       (((PDM_Type*)(base))->FIR0_COEFF3)
1753 #define PDM_PCM_FIR0_COEFF4(base)                       (((PDM_Type*)(base))->FIR0_COEFF4)
1754 #define PDM_PCM_FIR0_COEFF5(base)                       (((PDM_Type*)(base))->FIR0_COEFF5)
1755 #define PDM_PCM_FIR0_COEFF6(base)                       (((PDM_Type*)(base))->FIR0_COEFF6)
1756 #define PDM_PCM_FIR0_COEFF7(base)                       (((PDM_Type*)(base))->FIR0_COEFF7)
1757 
1758 #define PDM_PCM_FIR1_COEFF0(base)                       (((PDM_Type*)(base))->FIR1_COEFF0)
1759 #define PDM_PCM_FIR1_COEFF1(base)                       (((PDM_Type*)(base))->FIR1_COEFF1)
1760 #define PDM_PCM_FIR1_COEFF2(base)                       (((PDM_Type*)(base))->FIR1_COEFF2)
1761 #define PDM_PCM_FIR1_COEFF3(base)                       (((PDM_Type*)(base))->FIR1_COEFF3)
1762 #define PDM_PCM_FIR1_COEFF4(base)                       (((PDM_Type*)(base))->FIR1_COEFF4)
1763 #define PDM_PCM_FIR1_COEFF5(base)                       (((PDM_Type*)(base))->FIR1_COEFF5)
1764 #define PDM_PCM_FIR1_COEFF6(base)                       (((PDM_Type*)(base))->FIR1_COEFF6)
1765 #define PDM_PCM_FIR1_COEFF7(base)                       (((PDM_Type*)(base))->FIR1_COEFF7)
1766 #define PDM_PCM_FIR1_COEFF8(base)                       (((PDM_Type*)(base))->FIR1_COEFF8)
1767 #define PDM_PCM_FIR1_COEFF9(base)                       (((PDM_Type*)(base))->FIR1_COEFF9)
1768 #define PDM_PCM_FIR1_COEFF10(base)                       (((PDM_Type*)(base))->FIR1_COEFF10)
1769 #define PDM_PCM_FIR1_COEFF11(base)                       (((PDM_Type*)(base))->FIR1_COEFF11)
1770 #define PDM_PCM_FIR1_COEFF12(base)                       (((PDM_Type*)(base))->FIR1_COEFF12)
1771 #define PDM_PCM_FIR1_COEFF13(base)                       (((PDM_Type*)(base))->FIR1_COEFF13)
1772 
1773 
1774 #define PDM_PCM_CH_CTL(base, chnum)                   (((PDM_Type*)(base))->CH[chnum].CTL)
1775 #define PDM_PCM_CH_IF_CTL(base, chnum)                   (((PDM_Type*)(base))->CH[chnum].IF_CTL)
1776 #define PDM_PCM_CH_CIC_CTL(base, chnum)               (((PDM_Type*)(base))->CH[chnum].CIC_CTL)
1777 #define PDM_PCM_CH_FIR0_CTL(base, chnum)              (((PDM_Type*)(base))->CH[chnum].FIR0_CTL)
1778 #define PDM_PCM_CH_FIR1_CTL(base, chnum)              (((PDM_Type*)(base))->CH[chnum].FIR1_CTL)
1779 #define PDM_PCM_CH_DC_BLOCK_CTL(base, chnum)          (((PDM_Type*)(base))->CH[chnum].DC_BLOCK_CTL)
1780 #define PDM_PCM_INTR_RX_MASK(base, chnum)             (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASK)
1781 #define PDM_PCM_INTR_RX_MASKED(base, chnum)           (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASKED)
1782 #define PDM_PCM_INTR_RX(base, chnum)                  (((PDM_Type*)(base))->CH[chnum].INTR_RX)
1783 #define PDM_PCM_INTR_RX_SET(base, chnum)              (((PDM_Type*)(base))->CH[chnum].INTR_RX_SET)
1784 #define PDM_PCM_RX_FIFO_STATUS(base, chnum)              (((PDM_Type*)(base))->CH[chnum].RX_FIFO_STATUS)
1785 #define PDM_PCM_RX_FIFO_CTL(base, chnum)                 (((PDM_Type*)(base))->CH[chnum].RX_FIFO_CTL)
1786 #define PDM_PCM_RX_FIFO_RD(base, chnum)                  (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD)
1787 #define PDM_PCM_RX_FIFO_RD_SILENT(base, chnum)           (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD_SILENT)
1788 
1789 
1790 /*******************************************************************************
1791 *                BACKUP
1792 *******************************************************************************/
1793 
1794 #if defined (CY_IP_MXS28SRSS)
1795 #define BACKUP_RTC_RW                       (((BACKUP_Type *) BACKUP)->RTC_RW)
1796 #define BACKUP_CAL_CTL                      (((BACKUP_Type *) BACKUP)->CAL_CTL)
1797 #define BACKUP_STATUS                       (((BACKUP_Type *) BACKUP)->STATUS)
1798 #define BACKUP_RTC_TIME                     (((BACKUP_Type *) BACKUP)->RTC_TIME)
1799 #define BACKUP_RTC_DATE                     (((BACKUP_Type *) BACKUP)->RTC_DATE)
1800 #define BACKUP_ALM1_TIME                    (((BACKUP_Type *) BACKUP)->ALM1_TIME)
1801 #define BACKUP_ALM1_DATE                    (((BACKUP_Type *) BACKUP)->ALM1_DATE)
1802 #define BACKUP_ALM2_TIME                    (((BACKUP_Type *) BACKUP)->ALM2_TIME)
1803 #define BACKUP_ALM2_DATE                    (((BACKUP_Type *) BACKUP)->ALM2_DATE)
1804 #define BACKUP_INTR                         (((BACKUP_Type *) BACKUP)->INTR)
1805 #define BACKUP_INTR_SET                     (((BACKUP_Type *) BACKUP)->INTR_SET)
1806 #define BACKUP_INTR_MASK                    (((BACKUP_Type *) BACKUP)->INTR_MASK)
1807 #define BACKUP_INTR_MASKED                  (((BACKUP_Type *) BACKUP)->INTR_MASKED)
1808 #define BACKUP_RESET                        (((BACKUP_Type *) BACKUP)->RESET)
1809 #define BACKUP_CTL                          (((BACKUP_Type *) BACKUP)->CTL)
1810 #define BACKUP_WCO_CTL                      (((BACKUP_Type *) BACKUP)->WCO_CTL)
1811 #define BACKUP_WCO_STATUS                   (((BACKUP_Type *) BACKUP)->WCO_STATUS)
1812 #define BACKUP_LFWL_CTL                     (((BACKUP_Type *) BACKUP)->LFWL_CTL)
1813 #define BACKUP_BREG                         (((BACKUP_Type *) BACKUP)->BREG)
1814 #endif
1815 
1816 #if defined (CY_IP_MXS40SSRSS)
1817 #define BACKUP_CTL                          (((BACKUP_Type *) BACKUP)->CTL)
1818 #define BACKUP_RTC_RW                       (((BACKUP_Type *) BACKUP)->RTC_RW)
1819 #define BACKUP_CAL_CTL                      (((BACKUP_Type *) BACKUP)->CAL_CTL)
1820 #define BACKUP_STATUS                       (((BACKUP_Type *) BACKUP)->STATUS)
1821 #define BACKUP_RTC_TIME                     (((BACKUP_Type *) BACKUP)->RTC_TIME)
1822 #define BACKUP_RTC_DATE                     (((BACKUP_Type *) BACKUP)->RTC_DATE)
1823 #define BACKUP_ALM1_TIME                    (((BACKUP_Type *) BACKUP)->ALM1_TIME)
1824 #define BACKUP_ALM1_DATE                    (((BACKUP_Type *) BACKUP)->ALM1_DATE)
1825 #define BACKUP_ALM2_TIME                    (((BACKUP_Type *) BACKUP)->ALM2_TIME)
1826 #define BACKUP_ALM2_DATE                    (((BACKUP_Type *) BACKUP)->ALM2_DATE)
1827 #define BACKUP_INTR                         (((BACKUP_Type *) BACKUP)->INTR)
1828 #define BACKUP_INTR_SET                     (((BACKUP_Type *) BACKUP)->INTR_SET)
1829 #define BACKUP_INTR_MASK                    (((BACKUP_Type *) BACKUP)->INTR_MASK)
1830 #define BACKUP_INTR_MASKED                  (((BACKUP_Type *) BACKUP)->INTR_MASKED)
1831 #define BACKUP_PMIC_CTL                     (((BACKUP_Type *) BACKUP)->PMIC_CTL)
1832 #define BACKUP_RESET                        (((BACKUP_Type *) BACKUP)->RESET)
1833 #define BACKUP_LPECO_CTL                    (((BACKUP_Type *) BACKUP)->LPECO_CTL)
1834 #define BACKUP_LPECO_PRESCALE               (((BACKUP_Type *) BACKUP)->LPECO_PRESCALE)
1835 #define BACKUP_LPECO_STATUS                 (((BACKUP_Type *) BACKUP)->LPECO_STATUS)
1836 #define BACKUP_WCO_STATUS                   (((BACKUP_Type *) BACKUP)->WCO_STATUS)
1837 #define BACKUP_BREG_SET0                    (((BACKUP_Type *) BACKUP)->BREG_SET0)
1838 #define BACKUP_BREG_SET1                    (((BACKUP_Type *) BACKUP)->BREG_SET1)
1839 #define BACKUP_BREG_SET2                    (((BACKUP_Type *) BACKUP)->BREG_SET2)
1840 #define BACKUP_BREG_SET3                    (((BACKUP_Type *) BACKUP)->BREG_SET3)
1841 
1842 
1843 #define CY_SRSS_BACKUP_NUM_BREG             (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1 + SRSS_BACKUP_NUM_BREG2 + SRSS_BACKUP_NUM_BREG3)
1844 #define CY_SRSS_BACKUP_BREG0_START_POS      (0UL)
1845 #define CY_SRSS_BACKUP_BREG1_START_POS      (SRSS_BACKUP_NUM_BREG0)
1846 #define CY_SRSS_BACKUP_BREG2_START_POS      (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1)
1847 #define CY_SRSS_BACKUP_BREG3_START_POS      (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1 + SRSS_BACKUP_NUM_BREG2)
1848 
1849 #endif
1850 
1851 
1852 /*******************************************************************************
1853 *                CANFD
1854 *******************************************************************************/
1855 
1856 #define CANFD_CTL(base)                           (((CANFD_Type *)(base))->CTL)
1857 #define CANFD_STATUS(base)                        (((CANFD_Type *)(base))->STATUS)
1858 #define CANFD_NBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NBTP)
1859 #define CANFD_IR(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IR)
1860 #define CANFD_IE(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IE)
1861 #define CANFD_ILS(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILS)
1862 #define CANFD_ILE(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILE)
1863 #define CANFD_CCCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CCCR)
1864 #define CANFD_SIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.SIDFC)
1865 #define CANFD_XIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDFC)
1866 #define CANFD_XIDAM(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDAM)
1867 #define CANFD_RXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXESC)
1868 #define CANFD_RXF0C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0C)
1869 #define CANFD_RXF1C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1C)
1870 #define CANFD_RXFTOP_CTL(base, chan)              (((CANFD_Type *)(base))->CH[chan].RXFTOP_CTL)
1871 #define CANFD_RXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXBC)
1872 #define CANFD_TXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXESC)
1873 #define CANFD_TXEFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXEFC)
1874 #define CANFD_TXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBC)
1875 #define CANFD_DBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.DBTP)
1876 #define CANFD_TDCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TDCR)
1877 #define CANFD_GFC(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.GFC)
1878 #define CANFD_TXBRP(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBRP)
1879 #define CANFD_TXBAR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBAR)
1880 #define CANFD_TXBCR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCR)
1881 #define CANFD_TXBTO(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTO)
1882 #define CANFD_TXBCF(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCF)
1883 #define CANFD_TXBTIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTIE)
1884 #define CANFD_TXBCIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCIE)
1885 #define CANFD_NDAT1(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT1)
1886 #define CANFD_NDAT2(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT2)
1887 #define CANFD_RXF0S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0S)
1888 #define CANFD_RXFTOP0_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP0_DATA)
1889 #define CANFD_RXFTOP1_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP1_DATA)
1890 #define CANFD_RXF0A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0A)
1891 #define CANFD_RXF1S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1S)
1892 #define CANFD_RXF1A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1A)
1893 #define CANFD_PSR(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.PSR)
1894 #define CANFD_TEST(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TEST)
1895 #define CANFD_CREL(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CREL)
1896 
1897 #define CY_CANFD_CHANNELS_NUM                     (0x1UL)
1898 
1899 /*******************************************************************************
1900 *                MXOTPC
1901 *******************************************************************************/
1902 #define CY_MXOTPC_BASE                      (uint32_t)GET_ALIAS_ADDRESS(MXOTPC)
1903 
1904 #define MXOTPC_CTL                          (((MXOTPC_Type *) CY_MXOTPC_BASE)->CTL)
1905 #define MXOTPC_OTP_STATUS                   (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_STATUS)
1906 #define MXOTPC_OTP_CTL                      (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_CTL)
1907 #define MXOTPC_OTP_CMD                      (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_CMD)
1908 #define MXOTPC_LAYOUT                       (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT)
1909 #define MXOTPC_LAYOUT_EXT                   (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT)
1910 #define MXOTPC_OTP_PROGDATA                 (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_PROGDATA)
1911 #define MXOTPC_FOUT_ECC_STATUS              (((MXOTPC_Type *) CY_MXOTPC_BASE)->FOUT_ECC_STATUS)
1912 #define MXOTPC_ECC_STATUS                   (((MXOTPC_Type *) CY_MXOTPC_BASE)->ECC_STATUS)
1913 #define MXOTPC_CC312_ECC_STATUS             (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_ECC_STATUS)
1914 #define MXOTPC_CC312_ERROR_LOG              (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_ERROR_LOG)
1915 #define MXOTPC_CC312_CMD_SEL_LO             (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_CMD_SEL_LO)
1916 #define MXOTPC_CC312_CMD_SEL_HI             (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_CMD_SEL_HI)
1917 #define MXOTPC_LAYOUT_EXT1                  (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT1)
1918 #define MXOTPC_LAYOUT_EXT2                  (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT2)
1919 #define MXOTPC_LAYOUT_EXT3                  (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT3)
1920 #define MXOTPC_LAYOUT_EXT4                  (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT4)
1921 #define MXOTPC_CPU_PROG_CMD                 (((MXOTPC_Type *) CY_MXOTPC_BASE)->CPU_PROG_CMD)
1922 #define MXOTPC_BOOTROW                      (((MXOTPC_Type *) CY_MXOTPC_BASE)->BOOTROW)
1923 #define MXOTPC_CC312_RGN_LOCK_CTL           (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_RGN_LOCK_CTL)
1924 #define MXOTPC_ERR_RESP_CTL                 (((MXOTPC_Type *) CY_MXOTPC_BASE)->ERR_RESP_CTL)
1925 #define MXOTPC_INTR_OTPC                    (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC)
1926 #define MXOTPC_INTR_OTPC_SET                (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_SET)
1927 #define MXOTPC_INTR_OTPC_MASK               (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_MASK)
1928 #define MXOTPC_INTR_OTPC_MASKED             (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_MASKED)
1929 #define MXOTPC_CPU_ERROR_LOG                (((MXOTPC_Type *) CY_MXOTPC_BASE)->CPU_ERROR_LOG)
1930 
1931 #define MXOTPC_BOOT_ROW_FOUT_ECC_DED_STATUS_Msk    0x00070000UL
1932 
1933 /*******************************************************************************
1934 *                MXCONNBRIDGE
1935 *******************************************************************************/
1936 
1937 #define MXCONNBRIDGE_CTL(base)                    (((MXCONNBRIDGE_Type *)(base))->CTL)
1938 #define MXCONNBRIDGE_INTR_STATUS(base)            (((MXCONNBRIDGE_Type *)(base))->INTERRUPT_STATUS)
1939 #define MXCONNBRIDGE_INTR_MASK(base)              (((MXCONNBRIDGE_Type *)(base))->INTERRUPT_MASK)
1940 #define MXCONNBRIDGE_RF_SWITCH_CTRL(base)         (((MXCONNBRIDGE_Type *)(base))->RF_SWITCH_CTRL)
1941 #define MXCONNBRIDGE_GPIO_IN(base)                (((MXCONNBRIDGE_Type *)(base))->GPIO_IN)
1942 #define MXCONNBRIDGE_GPIO_OUT(base)               (((MXCONNBRIDGE_Type *)(base))->GPIO_OUT)
1943 #define MXCONNBRIDGE_DEV_WAKE(base)               (((MXCONNBRIDGE_Type *)(base))->DEV_WAKE)
1944 #define MXCONNBRIDGE_AP_WLAN_CTL(base)               (((MXCONNBRIDGE_Type *)(base))->AP_WLAN_CTL)
1945 
1946 /*******************************************************************************
1947 *                MXSDIODEV
1948 *******************************************************************************/
1949 
1950 #define MXSDIO_CORECONTROL(base)         (((MXSDIO_Type *)(base))->CORECONTROL)
1951 #define MXSDIO_CORESTATUS(base)              (((MXSDIO_Type *)(base))->CORESTATUS)
1952 #define MXSDIO_BISTSTATUS(base)              (((MXSDIO_Type *)(base))->BISTSTATUS)
1953 #define MXSDIO_INTSTATUS(base)               (((MXSDIO_Type *)(base))->INTSTATUS)
1954 #define MXSDIO_INTHOSTMASK(base)             (((MXSDIO_Type *)(base))->INTHOSTMASK)
1955 #define MXSDIO_INTSBMASK(base)               (((MXSDIO_Type *)(base))->INTSBMASK)
1956 #define MXSDIO_SBINTSTATUS(base)             (((MXSDIO_Type *)(base))->SBINTSTATUS)
1957 #define MXSDIO_SBINTMASK(base)               (((MXSDIO_Type *)(base))->SBINTMASK)
1958 #define MXSDIO_SDIOFUNCINTMASK(base)         (((MXSDIO_Type *)(base))->SDIOFUNCINTMASK)
1959 #define MXSDIO_TOSBMAILBOX(base)             (((MXSDIO_Type *)(base))->TOSBMAILBOX)
1960 #define MXSDIO_TOHOSTMAILBOX(base)           (((MXSDIO_Type *)(base))->TOHOSTMAILBOX)
1961 #define MXSDIO_TOSBMAILDATA(base)            (((MXSDIO_Type *)(base))->TOSBMAILDATA)
1962 #define MXSDIO_TOHOSTMAILDATA(base)          (((MXSDIO_Type *)(base))->TOHOSTMAILDATA)
1963 #define MXSDIO_SDIOACCESS(base)              (((MXSDIO_Type *)(base))->SDIOACCESS)
1964 #define MXSDIO_UNUSEDINTFCTRL(base)          (((MXSDIO_Type *)(base))->UNUSEDINTFCTRL)
1965 #define MXSDIO_INTRCVLAZY(base)              (((MXSDIO_Type *)(base))->INTRCVLAZY)
1966 #define MXSDIO_CMD52RDCOUNT(base)            (((MXSDIO_Type *)(base))->CMD52RDCOUNT)
1967 #define MXSDIO_CMD52WRCOUNT(base)            (((MXSDIO_Type *)(base))->CMD52WRCOUNT)
1968 #define MXSDIO_CMD53RDCOUNT(base)            (((MXSDIO_Type *)(base))->CMD53RDCOUNT)
1969 #define MXSDIO_CMD53WRCOUNT(base)            (((MXSDIO_Type *)(base))->CMD53WRCOUNT)
1970 #define MXSDIO_ABORTCOUNT(base)              (((MXSDIO_Type *)(base))->ABORTCOUNT)
1971 #define MXSDIO_CRCERRORCOUNT(base)           (((MXSDIO_Type *)(base))->CRCERRORCOUNT)
1972 #define MXSDIO_RDOUTOFSYNCCOUNT(base)        (((MXSDIO_Type *)(base))->RDOUTOFSYNCCOUNT)
1973 #define MXSDIO_WROUTOFSYNCCOUNT(base)        (((MXSDIO_Type *)(base))->WROUTOFSYNCCOUNT)
1974 #define MXSDIO_WRITEBUSYCOUNT(base)          (((MXSDIO_Type *)(base))->WRITEBUSYCOUNT)
1975 #define MXSDIO_READWAITCOUNT(base)         (((MXSDIO_Type *)(base))->READWAITCOUNT)
1976 #define MXSDIO_RDTERMCOUNT(base)             (((MXSDIO_Type *)(base))->RDTERMCOUNT)
1977 #define MXSDIO_WRTERMCOUNT(base)             (((MXSDIO_Type *)(base))->WRTERMCOUNT)
1978 #define MXSDIO_CLOCKCTRLSTATUS(base)         (((MXSDIO_Type *)(base))->CLOCKCTRLSTATUS)
1979 #define MXSDIO_WORKARND(base)                (((MXSDIO_Type *)(base))->WORKARND)
1980 #define MXSDIO_PWRCTRL(base)                 (((MXSDIO_Type *)(base))->PWRCTRL)
1981 #define MXSDIO_XMTCONTROL(base)              (((MXSDIO_Type *)(base))->XMTCONTROL)
1982 #define MXSDIO_XMTPTR(base)                  (((MXSDIO_Type *)(base))->XMTPTR)
1983 #define MXSDIO_XMTADDRESSLOW(base)           (((MXSDIO_Type *)(base))->XMTADDRESSLOW)
1984 #define MXSDIO_XMTADDRESSHI(base)            (((MXSDIO_Type *)(base))->XMTADDRESSHI)
1985 #define MXSDIO_XMTSTATUS0(base)              (((MXSDIO_Type *)(base))->XMTSTATUS0)
1986 #define MXSDIO_XMTSTATUS1(base)              (((MXSDIO_Type *)(base))->XMTSTATUS1)
1987 #define MXSDIO_RCVCONTROL(base)              (((MXSDIO_Type *)(base))->RCVCONTROL)
1988 #define MXSDIO_RCVPTR(base)                  (((MXSDIO_Type *)(base))->RCVPTR)
1989 #define MXSDIO_RCVADDRESSLOW(base)           (((MXSDIO_Type *)(base))->RCVADDRESSLOW)
1990 #define MXSDIO_RCVADDRESSHI(base)            (((MXSDIO_Type *)(base))->RCVADDRESSHI)
1991 #define MXSDIO_RCVSTATUS0(base)              (((MXSDIO_Type *)(base))->RCVSTATUS0)
1992 #define MXSDIO_RCVSTATUS1(base)              (((MXSDIO_Type *)(base))->RCVSTATUS1)
1993 #define MXSDIO_FIFOADDRESS(base)             (((MXSDIO_Type *)(base))->FIFOADDRESS)
1994 #define MXSDIO_FIFODATAL(base)               (((MXSDIO_Type *)(base))->FIFODATAL)
1995 #define MXSDIO_FIFODATAH(base)               (((MXSDIO_Type *)(base))->FIFODATAH)
1996 #define MXSDIO_SDIOCLKRESETCTRLREG(base)     (((MXSDIO_Type *)(base))->SDIOCLKRESETCTRLREG)
1997 #define MXSDIO_OTPSTATUSSHADOWREG(base)      (((MXSDIO_Type *)(base))->OTPSTATUSSHADOWREG)
1998 #define MXSDIO_OTPLAYOUTSHADOWREG(base)      (((MXSDIO_Type *)(base))->OTPLAYOUTSHADOWREG)
1999 #define MXSDIO_OTPSHADOWREG1(base)           (((MXSDIO_Type *)(base))->OTPSHADOWREG1)
2000 #define MXSDIO_OTPSHADOWREG2(base)           (((MXSDIO_Type *)(base))->OTPSHADOWREG2)
2001 #define MXSDIO_OTPSHADOWREG3(base)           (((MXSDIO_Type *)(base))->OTPSHADOWREG3)
2002 
2003 /******************************************************************************
2004 *                MXETH
2005 *******************************************************************************/
2006 #define ETH_CTL(base)                       (((ETH_Type*)(base))->CTL)
2007 #define ETH_TX_Q_PTR(base)                  (((ETH_Type*)(base))->TRANSMIT_Q_PTR)
2008 #define ETH_TX_Q1_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q1_PTR)
2009 #define ETH_TX_Q2_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q2_PTR)
2010 #define ETH_RX_Q_PTR(base)                  (((ETH_Type*)(base))->RECEIVE_Q_PTR)
2011 #define ETH_RX_Q1_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q1_PTR)
2012 #define ETH_RX_Q2_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q2_PTR)
2013 
2014 /*******************************************************************************
2015 *                PPU
2016 *******************************************************************************/
2017 #define CY_PPU_MAIN_BASE                             ((uint32_t)PWRMODE_PPU_MAIN)
2018 #define CY_PPU_CPUSS_BASE                            ((uint32_t)CPUSS_PPU_BASE)
2019 #define CY_PPU_SRAM_BASE                             ((uint32_t)RAMC_PPU0_BASE)
2020 
2021 /*******************************************************************************
2022 *                PDCM
2023 *******************************************************************************/
2024 
2025 #define CY_PDCM_PD_SENSE(pd_id)                        (((PWRMODE_PD_Type*) &PWRMODE->PD[pd_id])->PD_SENSE)
2026 #define CY_PDCM_PD_SPT(pd_id)                          (((PWRMODE_PD_Type*) &PWRMODE->PD[pd_id])->PD_SPT)
2027 
2028 /*******************************************************************************
2029 *                IPC
2030 *******************************************************************************/
2031 
2032 #define REG_IPC_STRUCT_ACQUIRE(base)           (((IPC_STRUCT_Type*)(base))->ACQUIRE)
2033 #define REG_IPC_STRUCT_RELEASE(base)           (((IPC_STRUCT_Type*)(base))->RELEASE)
2034 #define REG_IPC_STRUCT_NOTIFY(base)            (((IPC_STRUCT_Type*)(base))->NOTIFY)
2035 #define REG_IPC_STRUCT_DATA(base)              (((IPC_STRUCT_Type*)(base))->DATA0)
2036 #define REG_IPC_STRUCT_DATA1(base)             (((IPC_STRUCT_Type*)(base))->DATA1)
2037 #define REG_IPC_STRUCT_LOCK_STATUS(base)       (*(volatile uint32_t*)((uint32_t)(base) + offsetof(IPC_STRUCT_Type, LOCK_STATUS)))
2038 
2039 #define REG_IPC_INTR_STRUCT_INTR(base)         (((IPC_INTR_STRUCT_Type*)(base))->INTR)
2040 #define REG_IPC_INTR_STRUCT_INTR_SET(base)     (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET)
2041 #define REG_IPC_INTR_STRUCT_INTR_MASK(base)    (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK)
2042 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base)  (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED)
2043 
2044 #ifdef BTSS
2045 #define CY_IPC_STRUCT_PTR(ipcIndex)            ((IPC_STRUCT_Type*)((void *)(((uint8_t*)&(BTSS_DATA_RAM_IPC->MXIPC_0_ACQUIRE)) + (sizeof(IPC_STRUCT_Type) * (ipcIndex)))))
2046 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex)   ((IPC_INTR_STRUCT_Type *)((void*)(((uint8_t*)&(BTSS_DATA_RAM_IPC->MXIPC_INTR_0)) + (sizeof(IPC_INTR_STRUCT_Type) * (ipcIntrIndex)))))
2047 #else
2048 #define CY_IPC_STRUCT_PTR(ipcIndex)            ((IPC_STRUCT_Type*)(IPC_BASE + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
2049 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex)   (&(((IPC_Type *)IPC_BASE)->INTR_STRUCT[ipcIntrIndex]))
2050 #endif
2051 
2052 #define CY_IPC_STRUCT_PTR_FOR_IP(ipcIndex, base)            ((IPC_STRUCT_Type*)((uint32_t)(base) + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
2053 #define CY_IPC_INTR_STRUCT_PTR_FOR_IP(ipcIntrIndex, base)   (&(((IPC_Type *)base)->INTR_STRUCT[ipcIntrIndex]))
2054 
2055 #define CY_IPC_INSTANCES                       (1U)
2056 #define CY_IPC_CHANNELS                        ((uint32_t)4)
2057 #define CY_IPC_INTERRUPTS                      ((uint32_t)2)
2058 #define CY_IPC_CHANNELS_PER_INSTANCE           CY_IPC_CHANNELS
2059 #define CY_IPC_INTERRUPTS_PER_INSTANCE         CY_IPC_INTERRUPTS
2060 
2061 /* ipcChannel comprises of total number of channels present in all IPC IP instances */
2062 #define CY_IPC_PIPE_CHANNEL_NUMBER_WITHIN_INSTANCE(ipcChannel)  (ipcChannel%CY_IPC_CHANNELS_PER_INSTANCE)
2063 #define CY_IPC_PIPE_INTR_NUMBER_WITHIN_INSTANCE(ipcIntr)        (ipcIntr%CY_IPC_INTERRUPTS_PER_INSTANCE)
2064 
2065 #define CY_IPC_CH_MASK(chIndex)         (0x1u << (chIndex % CY_IPC_CHANNELS_PER_INSTANCE))
2066 #define CY_IPC_INTR_MASK(intrIndex)     (0x1u << (intrIndex % CY_IPC_INTERRUPTS_PER_INSTANCE))
2067 /*******************************************************************************
2068 *                LIN
2069 *******************************************************************************/
2070 #if defined (CY_IP_MXLIN)
2071 #define LIN0_CH1                                ((LIN_CH_Type*) &LIN0->CH[1])
2072 #define LIN0_CH2                                ((LIN_CH_Type*) &LIN0->CH[2])
2073 #define LIN0_CH3                                ((LIN_CH_Type*) &LIN0->CH[3])
2074 #define LIN0_CH4                                ((LIN_CH_Type*) &LIN0->CH[4])
2075 #define LIN0_CH5                                ((LIN_CH_Type*) &LIN0->CH[5])
2076 #define LIN0_CH6                                ((LIN_CH_Type*) &LIN0->CH[6])
2077 #define LIN0_CH7                                ((LIN_CH_Type*) &LIN0->CH[7])
2078 #define LIN0_CH8                                ((LIN_CH_Type*) &LIN0->CH[8])
2079 #define LIN0_CH9                                ((LIN_CH_Type*) &LIN0->CH[9])
2080 #define LIN0_CH10                               ((LIN_CH_Type*) &LIN0->CH[10])
2081 #define LIN0_CH11                               ((LIN_CH_Type*) &LIN0->CH[11])
2082 #define LIN0_CH12                               ((LIN_CH_Type*) &LIN0->CH[12])
2083 #define LIN0_CH13                               ((LIN_CH_Type*) &LIN0->CH[13])
2084 #define LIN0_CH14                               ((LIN_CH_Type*) &LIN0->CH[14])
2085 #define LIN0_CH15                               ((LIN_CH_Type*) &LIN0->CH[15])
2086 #define LIN0_CH16                               ((LIN_CH_Type*) &LIN0->CH[16])
2087 #define LIN0_CH17                               ((LIN_CH_Type*) &LIN0->CH[17])
2088 #define LIN0_CH18                               ((LIN_CH_Type*) &LIN0->CH[18])
2089 #define LIN0_CH19                               ((LIN_CH_Type*) &LIN0->CH[19])
2090 #define LIN0_CH20                               ((LIN_CH_Type*) &LIN0->CH[20])
2091 #define LIN0_CH21                               ((LIN_CH_Type*) &LIN0->CH[21])
2092 #define LIN0_CH22                               ((LIN_CH_Type*) &LIN0->CH[22])
2093 #define LIN0_CH23                               ((LIN_CH_Type*) &LIN0->CH[23])
2094 #define LIN0_CH24                               ((LIN_CH_Type*) &LIN0->CH[24])
2095 #define LIN0_CH25                               ((LIN_CH_Type*) &LIN0->CH[25])
2096 #define LIN0_CH26                               ((LIN_CH_Type*) &LIN0->CH[26])
2097 #define LIN0_CH27                               ((LIN_CH_Type*) &LIN0->CH[27])
2098 #define LIN0_CH28                               ((LIN_CH_Type*) &LIN0->CH[28])
2099 #define LIN0_CH29                               ((LIN_CH_Type*) &LIN0->CH[29])
2100 #define LIN0_CH30                               ((LIN_CH_Type*) &LIN0->CH[30])
2101 #define LIN0_CH31                               ((LIN_CH_Type*) &LIN0->CH[31])
2102 
2103 #define LIN_CH_CTL0(base)                       (((LIN_CH_Type *)(base))->CTL0)
2104 #define LIN_CH_CTL1(base)                       (((LIN_CH_Type *)(base))->CTL1)
2105 #define LIN_CH_STATUS(base)                     (((LIN_CH_Type *)(base))->STATUS)
2106 #define LIN_CH_CMD(base)                        (((LIN_CH_Type *)(base))->CMD)
2107 #define LIN_CH_TX_RX_STATUS(base)               (((LIN_CH_Type *)(base))->TX_RX_STATUS)
2108 #define LIN_CH_PID_CHECKSUM(base)               (((LIN_CH_Type *)(base))->PID_CHECKSUM)
2109 #define LIN_CH_DATA0(base)                      (((LIN_CH_Type *)(base))->DATA0)
2110 #define LIN_CH_DATA1(base)                      (((LIN_CH_Type *)(base))->DATA1)
2111 #define LIN_CH_INTR(base)                       (((LIN_CH_Type *)(base))->INTR)
2112 #define LIN_CH_INTR_SET(base)                   (((LIN_CH_Type *)(base))->INTR_SET)
2113 #define LIN_CH_INTR_MASK(base)                  (((LIN_CH_Type *)(base))->INTR_MASK)
2114 #define LIN_CH_INTR_MASKED(base)                (((LIN_CH_Type *)(base))->INTR_MASKED)
2115 
2116 #define LIN_ERROR_CTL(base)                     (((LIN_Type *)(base))->ERROR_CTL)
2117 #define LIN_TEST_CTL(base)                      (((LIN_Type *)(base))->TEST_CTL)
2118 #endif /* CY_IP_MXLIN */
2119 
2120 /*******************************************************************************
2121 *                MXKEYSCAN
2122 *******************************************************************************/
2123 #if defined (CY_IP_MXKEYSCAN)
2124 
2125 #define KEYSCAN_CTL(base)                       (((MXKEYSCAN_Type *)(base))->KEYSCAN_CTL)
2126 #define KEYSCAN_DEBOUNCE(base)                  (((MXKEYSCAN_Type *)(base))->DEBOUNCE)
2127 #define KEYSCAN_KEYFIFO_CNT(base)               (((MXKEYSCAN_Type *)(base))->KEYFIFO_CNT)
2128 #define KEYSCAN_KEYFIFO(base)                   (((MXKEYSCAN_Type *)(base))->KEYFIFO)
2129 #define KEYSCAN_MIA_CTL(base)                   (((MXKEYSCAN_Type *)(base))->MIA_CTL)
2130 #define KEYSCAN_MIA_STATUS(base)                (((MXKEYSCAN_Type *)(base))->MIA_STATUS)
2131 #define KEYSCAN_KSI_USED(base)                  (((MXKEYSCAN_Type *)(base))->KSI_USED)
2132 #define KEYSCAN_INTR(base)                      (((MXKEYSCAN_Type *)(base))->INTR)
2133 #define KEYSCAN_INTR_SET(base)                  (((MXKEYSCAN_Type *)(base))->INTR_SET)
2134 #define KEYSCAN_INTR_MASK(base)                 (((MXKEYSCAN_Type *)(base))->INTR_MASK)
2135 #define KEYSCAN_INTR_MASKED(base)               (((MXKEYSCAN_Type *)(base))->INTR_MASKED)
2136 
2137 #endif /* CY_IP_MXKEYSCAN */
2138 
2139 #define MPC_Type                                 RAMC_MPC_Type
2140 #ifdef CPUSS_PC_NR
2141 #define MPC_PC_NR                                CPUSS_PC_NR
2142 #else
2143 #define MPC_PC_NR                                RAMC0_MPC_PC_NR
2144 #endif
2145 
2146 /*******************************************************************************
2147 *                MS_CTL
2148 *******************************************************************************/
2149 #ifdef _CYIP_MS_CTL_2_1_V2_H_
2150 
2151 #define MS_CTL_PC_CTL_VX(index)          (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS[(index)].CTL)
2152 #define MS_CTL_PC_VAL_VX(index)          (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS_PC[(index)].PC)
2153 #define MS_CTL_PC_READ_MIRROR_VX(index)  (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS_PC[(index)].PC_READ_MIR)
2154 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_VX   (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->CODE_MS0_MSC_ACG_CTL)
2155 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_VX    (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->SYS_MS0_MSC_ACG_CTL)
2156 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_VX    (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->SYS_MS1_MSC_ACG_CTL)
2157 #define MS_CTL_EXP_MS_MSC_ACG_CTL_VX     (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->EXP_MS_MSC_ACG_CTL)
2158 #define MS_CTL_DMAC0_MSC_ACG_CTL_VX      (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->DMAC0_MSC_ACG_CTL)
2159 #define MS_CTL_DMAC1_MSC_ACG_CTL_VX      (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->DMAC1_MSC_ACG_CTL)
2160 
2161 /* MS_CTL.CODE_MS0_MSC_ACG_CTL */
2162 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos   MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2163 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk   MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2164 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos        MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2165 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk        MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2166 /* MS_CTL.SYS_MS0_MSC_ACG_CTL */
2167 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos    MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2168 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk    MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2169 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos         MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2170 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk         MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2171 /* MS_CTL.SYS_MS1_MSC_ACG_CTL */
2172 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos    MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2173 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk    MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2174 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Pos         MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Pos
2175 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Msk         MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Msk
2176 /* MS_CTL.EXP_MS_MSC_ACG_CTL */
2177 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos     MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2178 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk     MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2179 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Pos          MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_SEC_RESP_Pos
2180 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Msk          MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_SEC_RESP_Msk
2181 /* MS_CTL.DMAC0_MSC_ACG_CTL */
2182 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos      MS_CTL_2_1_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2183 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk      MS_CTL_2_1_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2184 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Pos           MS_CTL_2_1_DMAC0_MSC_ACG_CTL_SEC_RESP_Pos
2185 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Msk           MS_CTL_2_1_DMAC0_MSC_ACG_CTL_SEC_RESP_Msk
2186 /* MS_CTL.DMAC1_MSC_ACG_CTL */
2187 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos      MS_CTL_2_1_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2188 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk      MS_CTL_2_1_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2189 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Pos           MS_CTL_2_1_DMAC1_MSC_ACG_CTL_SEC_RESP_Pos
2190 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Msk           MS_CTL_2_1_DMAC1_MSC_ACG_CTL_SEC_RESP_Msk
2191 
2192 #else
2193 
2194 #define MS_CTL_PC_CTL_VX(index)          (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS[(index)].CTL)
2195 #define MS_CTL_PC_VAL_VX(index)          (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS_PC[(index)].PC)
2196 #define MS_CTL_PC_READ_MIRROR_VX(index)  (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS_PC[(index)].PC_READ_MIR)
2197 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_VX   (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->CODE_MS0_MSC_ACG_CTL)
2198 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_VX    (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->SYS_MS0_MSC_ACG_CTL)
2199 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_VX    (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->SYS_MS1_MSC_ACG_CTL)
2200 #define MS_CTL_EXP_MS_MSC_ACG_CTL_VX     (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->EXP_MS_MSC_ACG_CTL)
2201 #define MS_CTL_DMAC0_MSC_ACG_CTL_VX      (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->DMAC0_MSC_ACG_CTL)
2202 #define MS_CTL_DMAC1_MSC_ACG_CTL_VX      (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->DMAC1_MSC_ACG_CTL)
2203 
2204 /* MS_CTL.CODE_MS0_MSC_ACG_CTL */
2205 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos   MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2206 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk   MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2207 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos        MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2208 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk        MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2209 /* MS_CTL.SYS_MS0_MSC_ACG_CTL */
2210 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos    MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2211 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk    MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2212 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos         MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2213 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk         MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2214 /* MS_CTL.SYS_MS1_MSC_ACG_CTL */
2215 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos    MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2216 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk    MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2217 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Pos         MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Pos
2218 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Msk         MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Msk
2219 /* MS_CTL.EXP_MS_MSC_ACG_CTL */
2220 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos     MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2221 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk     MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2222 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Pos          MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Pos
2223 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Msk          MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Msk
2224 /* MS_CTL.DMAC0_MSC_ACG_CTL */
2225 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos      MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2226 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk      MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2227 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Pos           MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Pos
2228 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Msk           MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Msk
2229 /* MS_CTL.DMAC1_MSC_ACG_CTL */
2230 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos      MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2231 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk      MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2232 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Pos           MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Pos
2233 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Msk           MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Msk
2234 
2235 #endif
2236 
2237 
2238 /*******************************************************************************
2239 *                MXSRAMC
2240 *******************************************************************************/
2241 #define MXSRAMC_STATUS                                 (((RAMC_Type *) RAMC0_BASE)->STATUS)
2242 #define MXSRAMC_PWR_MACRO_CTL                          (((RAMC_Type *) RAMC0_BASE)->PWR_MACRO_CTL)
2243 #define MXSRAMC_PWR_MACRO_CTL_LOCK                     (((RAMC_Type *) RAMC0_BASE)->PWR_MACRO_CTL_LOCK)
2244 
2245 
2246 #define MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0                0X00000001U
2247 #define MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1                0X00000002U
2248 #define MXSRAMC_PWR_MACRO_CTL_LOCK_SET01               0X00000003U
2249 #define CY_CPUSS_RAMC0_MACRO_NR                        CPUSS_RAMC0_MACRO_NR
2250 
2251 /*******************************************************************************
2252 *                PPC
2253 *******************************************************************************/
2254 
2255 #ifdef _CYIP_PPC_V2_H_
2256 #define PPC_Type PPC_PPC_Type
2257 #define PPC_CTL_RESP_CFG_Msk PPC_PPC_CTL_RESP_CFG_Msk
2258 #endif
2259 
2260 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
2261 
2262 #endif /* CY_DEVICE_H_ */
2263 
2264 /* [] END OF FILE */
2265 
2266