1 /***************************************************************************//** 2 * \file cyip_tcpwm_v3.h 3 * 4 * \brief 5 * TCPWM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_TCPWM_V3_H_ 28 #define _CYIP_TCPWM_V3_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * TCPWM 34 *******************************************************************************/ 35 36 #define TCPWM_GRP_CNT_SECTION_SIZE 0x00000100UL 37 #define TCPWM_GRP_SECTION_SIZE 0x00010000UL 38 #define TCPWM_TR_ALL_GF_SECTION_SIZE 0x00000400UL 39 #define TCPWM_TR_ALL_SYNC_BYPASS_SECTION_SIZE 0x00000040UL 40 #define TCPWM_MOTIF_GRP_MOTIF_SECTION_SIZE 0x00000200UL 41 #define TCPWM_MOTIF_GRP_SECTION_SIZE 0x00004000UL 42 #define TCPWM_SECTION_SIZE 0x00100000UL 43 44 /** 45 * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT) 46 */ 47 typedef struct { 48 __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ 49 __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ 50 __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ 51 __IM uint32_t RESERVED; 52 __IOM uint32_t CC0; /*!< 0x00000010 Counter compare/capture 0 register */ 53 __IOM uint32_t CC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */ 54 __IOM uint32_t CC1; /*!< 0x00000018 Counter compare/capture 1 register */ 55 __IOM uint32_t CC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */ 56 __IOM uint32_t PERIOD; /*!< 0x00000020 Counter period register */ 57 __IOM uint32_t PERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */ 58 __IOM uint32_t LINE_SEL; /*!< 0x00000028 Counter line selection register */ 59 __IOM uint32_t LINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */ 60 __IOM uint32_t DT; /*!< 0x00000030 Counter PWM dead time register */ 61 __IOM uint32_t DT_BUFF; /*!< 0x00000034 Counter buffered PWM dead time register */ 62 __IOM uint32_t PS; /*!< 0x00000038 Counter prescalar register */ 63 __IM uint32_t RESERVED1; 64 __IOM uint32_t TR_CMD; /*!< 0x00000040 Counter trigger command register */ 65 __IOM uint32_t TR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */ 66 __IOM uint32_t TR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */ 67 __IOM uint32_t TR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */ 68 __IOM uint32_t TR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */ 69 __IOM uint32_t TR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */ 70 __IM uint32_t RESERVED2[6]; 71 __IOM uint32_t INTR; /*!< 0x00000070 Interrupt request register */ 72 __IOM uint32_t INTR_SET; /*!< 0x00000074 Interrupt set request register */ 73 __IOM uint32_t INTR_MASK; /*!< 0x00000078 Interrupt mask register */ 74 __IM uint32_t INTR_MASKED; /*!< 0x0000007C Interrupt masked request register */ 75 __IOM uint32_t LFSR; /*!< 0x00000080 LFSR register */ 76 __IOM uint32_t ONE_GF[8]; /*!< 0x00000084 Glitch filter register for one to one trigger */ 77 __IOM uint32_t TR_ONE_SYNC_BYPASS; /*!< 0x000000A4 Sync bypass register for one to one trigger */ 78 __IM uint32_t RESERVED3[22]; 79 } TCPWM_GRP_CNT_Type; /*!< Size = 256 (0x100) */ 80 81 /** 82 * \brief Group of counters (TCPWM_GRP) 83 */ 84 typedef struct { 85 TCPWM_GRP_CNT_Type CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */ 86 } TCPWM_GRP_Type; /*!< Size = 65536 (0x10000) */ 87 88 /** 89 * \brief Glitch filter module for group trigger (TCPWM_TR_ALL_GF) 90 */ 91 typedef struct { 92 __IOM uint32_t ALL_GF[254]; /*!< 0x00000000 Glitch filter register for All Group Triggers */ 93 __IM uint32_t RESERVED[2]; 94 } TCPWM_TR_ALL_GF_Type; /*!< Size = 1024 (0x400) */ 95 96 /** 97 * \brief Glitch filter module for group trigger (TCPWM_TR_ALL_SYNC_BYPASS) 98 */ 99 typedef struct { 100 __IOM uint32_t TR_ALL_SYNC_BYPASS[8]; /*!< 0x00000000 Trigger Sync bypass for group trigger */ 101 __IM uint32_t RESERVED[8]; 102 } TCPWM_TR_ALL_SYNC_BYPASS_Type; /*!< Size = 64 (0x40) */ 103 104 /** 105 * \brief MOTIF Module (TCPWM_MOTIF_GRP_MOTIF) 106 */ 107 typedef struct { 108 __IOM uint32_t PCONF; /*!< 0x00000000 Global control register */ 109 __IOM uint32_t PSUS; /*!< 0x00000004 Suspend Configuration */ 110 __IOM uint32_t PRUNS; /*!< 0x00000008 MOTIF run bit set */ 111 __IM uint32_t RESERVED; 112 __IM uint32_t PRUN; /*!< 0x00000010 MOTIF run bit status */ 113 __IM uint32_t RESERVED1[3]; 114 __IM uint32_t MIDR; /*!< 0x00000020 Module Identification register */ 115 __OM uint32_t HIST; /*!< 0x00000024 Hall Inputs Sample Trigger */ 116 __IOM uint32_t HMEC; /*!< 0x00000028 Hall Mode Extra Config */ 117 __IM uint32_t RESERVED2; 118 __IM uint32_t HALP; /*!< 0x00000030 Hall Current and Expected patterns */ 119 __IOM uint32_t HALPS; /*!< 0x00000034 Hall Current and Expected shadow patterns */ 120 __IOM uint32_t HOSC; /*!< 0x00000038 Hall Sensor Output Config */ 121 __IM uint32_t RESERVED3; 122 __IM uint32_t MCM; /*!< 0x00000040 Multi-Channel Mode Pattern */ 123 __IOM uint32_t MCSM; /*!< 0x00000044 Multi-Channel Mode shadow Pattern LUT0 */ 124 __OM uint32_t MCMS; /*!< 0x00000048 Multi-Channel Mode Control set */ 125 __OM uint32_t MCMC; /*!< 0x0000004C Multi-Channel Mode Control clear */ 126 __IM uint32_t MCMF; /*!< 0x00000050 Multi-Channel Mode flag status */ 127 __IOM uint32_t MCPF; /*!< 0x00000054 Multi-Channel Pattern Fault */ 128 __IOM uint32_t MOSC; /*!< 0x00000058 Multi-Channel Output Config */ 129 __IM uint32_t RESERVED4; 130 __IOM uint32_t QDC; /*!< 0x00000060 Quadrature Decoder Configuration */ 131 __IOM uint32_t QOSC; /*!< 0x00000064 Quadrature Output Config */ 132 __IOM uint32_t MCMEC; /*!< 0x00000068 Multi-Channel Extra Config */ 133 __IM uint32_t RESERVED5; 134 __IM uint32_t PFLG; /*!< 0x00000070 MOTIF interrupt status */ 135 __IOM uint32_t PFLGE; /*!< 0x00000074 MOTIF interrupt enable */ 136 __OM uint32_t SPFLG; /*!< 0x00000078 Interrupt set register */ 137 __OM uint32_t RPFLG; /*!< 0x0000007C Interrupt clear register */ 138 __IOM uint32_t MCSM1; /*!< 0x00000080 Multi-Channel Mode shadow pattern LUT1 */ 139 __IOM uint32_t MCSM2; /*!< 0x00000084 Multi-Channel Mode shadow pattern LUT2 */ 140 __IOM uint32_t MCSM3; /*!< 0x00000088 Multi-Channel Mode shadow pattern LUT3 */ 141 __IOM uint32_t MCSM4; /*!< 0x0000008C Multi-Channel Mode shadow pattern LUT4 */ 142 __IOM uint32_t MCSM5; /*!< 0x00000090 Multi-Channel Mode shadow pattern LUT5 */ 143 __IOM uint32_t CLUT; /*!< 0x00000094 Hall Mode LUT config */ 144 __IM uint32_t SLUT; /*!< 0x00000098 Hall Mode LUT status */ 145 __IM uint32_t RESERVED6[25]; 146 __IM uint32_t PDBG; /*!< 0x00000100 MOTIF Debug Register */ 147 __IM uint32_t PLP0S; /*!< 0x00000104 MOTIF Low Pass 0 Status */ 148 __IM uint32_t PLP1S; /*!< 0x00000108 MOTIF Low Pass 1 Status */ 149 __IM uint32_t PLP2S; /*!< 0x0000010C MOTIF Low Pass 2 Status */ 150 __IM uint32_t RESERVED7[60]; 151 } TCPWM_MOTIF_GRP_MOTIF_Type; /*!< Size = 512 (0x200) */ 152 153 /** 154 * \brief Group of MOTIF module (TCPWM_MOTIF_GRP) 155 */ 156 typedef struct { 157 TCPWM_MOTIF_GRP_MOTIF_Type MOTIF[32]; /*!< 0x00000000 MOTIF Module */ 158 } TCPWM_MOTIF_GRP_Type; /*!< Size = 16384 (0x4000) */ 159 160 /** 161 * \brief Timer/Counter/PWM (TCPWM) 162 */ 163 typedef struct { 164 TCPWM_GRP_Type GRP[8]; /*!< 0x00000000 Group of counters */ 165 TCPWM_TR_ALL_GF_Type TR_ALL_GF; /*!< 0x00080000 Glitch filter module for group trigger */ 166 __IM uint32_t RESERVED[16128]; 167 TCPWM_TR_ALL_SYNC_BYPASS_Type TR_ALL_SYNC_BYPASS; /*!< 0x00090000 Glitch filter module for group trigger */ 168 __IM uint32_t RESERVED1[16368]; 169 TCPWM_MOTIF_GRP_Type MOTIF_GRP[8]; /*!< 0x000A0000 Group of MOTIF module */ 170 } TCPWM_Type; /*!< Size = 786432 (0xC0000) */ 171 172 173 /* TCPWM_GRP_CNT.CTRL */ 174 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos 0UL 175 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL 176 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos 1UL 177 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL 178 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL 179 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL 180 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL 181 #define TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL 182 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos 4UL 183 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL 184 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL 185 #define TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL 186 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos 6UL 187 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL 188 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL 189 #define TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL 190 #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos 8UL 191 #define TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk 0x100UL 192 #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos 9UL 193 #define TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL 194 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos 10UL 195 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk 0x400UL 196 #define TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Pos 11UL 197 #define TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Msk 0x800UL 198 #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos 12UL 199 #define TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL 200 #define TCPWM_GRP_CNT_CTRL_PWM_TC_SYNC_KILL_DT_Pos 14UL 201 #define TCPWM_GRP_CNT_CTRL_PWM_TC_SYNC_KILL_DT_Msk 0x4000UL 202 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_DT_Pos 15UL 203 #define TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_DT_Msk 0x8000UL 204 #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos 16UL 205 #define TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL 206 #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos 18UL 207 #define TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk 0x40000UL 208 #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos 20UL 209 #define TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL 210 #define TCPWM_GRP_CNT_CTRL_DITHEREN_Pos 22UL 211 #define TCPWM_GRP_CNT_CTRL_DITHEREN_Msk 0xC00000UL 212 #define TCPWM_GRP_CNT_CTRL_MODE_Pos 24UL 213 #define TCPWM_GRP_CNT_CTRL_MODE_Msk 0x7000000UL 214 #define TCPWM_GRP_CNT_CTRL_KILL_LINE_POLARITY_Pos 27UL 215 #define TCPWM_GRP_CNT_CTRL_KILL_LINE_POLARITY_Msk 0x18000000UL 216 #define TCPWM_GRP_CNT_CTRL_DBG_SUS_EN_Pos 29UL 217 #define TCPWM_GRP_CNT_CTRL_DBG_SUS_EN_Msk 0x20000000UL 218 #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos 30UL 219 #define TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL 220 #define TCPWM_GRP_CNT_CTRL_ENABLED_Pos 31UL 221 #define TCPWM_GRP_CNT_CTRL_ENABLED_Msk 0x80000000UL 222 /* TCPWM_GRP_CNT.STATUS */ 223 #define TCPWM_GRP_CNT_STATUS_DOWN_Pos 0UL 224 #define TCPWM_GRP_CNT_STATUS_DOWN_Msk 0x1UL 225 #define TCPWM_GRP_CNT_STATUS_CC0_READ_MISS_Pos 1UL 226 #define TCPWM_GRP_CNT_STATUS_CC0_READ_MISS_Msk 0x2UL 227 #define TCPWM_GRP_CNT_STATUS_CC1_READ_MISS_Pos 2UL 228 #define TCPWM_GRP_CNT_STATUS_CC1_READ_MISS_Msk 0x4UL 229 #define TCPWM_GRP_CNT_STATUS_KILL_STATUS_Pos 3UL 230 #define TCPWM_GRP_CNT_STATUS_KILL_STATUS_Msk 0x8UL 231 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos 4UL 232 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk 0x10UL 233 #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos 5UL 234 #define TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk 0x20UL 235 #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos 6UL 236 #define TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk 0x40UL 237 #define TCPWM_GRP_CNT_STATUS_TR_STOP_Pos 7UL 238 #define TCPWM_GRP_CNT_STATUS_TR_STOP_Msk 0x80UL 239 #define TCPWM_GRP_CNT_STATUS_TR_START_Pos 8UL 240 #define TCPWM_GRP_CNT_STATUS_TR_START_Msk 0x100UL 241 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos 9UL 242 #define TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk 0x200UL 243 #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos 10UL 244 #define TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk 0x400UL 245 #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos 11UL 246 #define TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk 0x800UL 247 #define TCPWM_GRP_CNT_STATUS_RUNNING_Pos 15UL 248 #define TCPWM_GRP_CNT_STATUS_RUNNING_Msk 0x8000UL 249 #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos 16UL 250 #define TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk 0xFF0000UL 251 #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos 24UL 252 #define TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk 0xFF000000UL 253 /* TCPWM_GRP_CNT.COUNTER */ 254 #define TCPWM_GRP_CNT_COUNTER_COUNTER_Pos 0UL 255 #define TCPWM_GRP_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL 256 /* TCPWM_GRP_CNT.CC0 */ 257 #define TCPWM_GRP_CNT_CC0_CC_Pos 0UL 258 #define TCPWM_GRP_CNT_CC0_CC_Msk 0xFFFFFFFFUL 259 /* TCPWM_GRP_CNT.CC0_BUFF */ 260 #define TCPWM_GRP_CNT_CC0_BUFF_CC_Pos 0UL 261 #define TCPWM_GRP_CNT_CC0_BUFF_CC_Msk 0xFFFFFFFFUL 262 /* TCPWM_GRP_CNT.CC1 */ 263 #define TCPWM_GRP_CNT_CC1_CC_Pos 0UL 264 #define TCPWM_GRP_CNT_CC1_CC_Msk 0xFFFFFFFFUL 265 /* TCPWM_GRP_CNT.CC1_BUFF */ 266 #define TCPWM_GRP_CNT_CC1_BUFF_CC_Pos 0UL 267 #define TCPWM_GRP_CNT_CC1_BUFF_CC_Msk 0xFFFFFFFFUL 268 /* TCPWM_GRP_CNT.PERIOD */ 269 #define TCPWM_GRP_CNT_PERIOD_PERIOD_Pos 0UL 270 #define TCPWM_GRP_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL 271 /* TCPWM_GRP_CNT.PERIOD_BUFF */ 272 #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos 0UL 273 #define TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL 274 /* TCPWM_GRP_CNT.LINE_SEL */ 275 #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos 0UL 276 #define TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk 0x7UL 277 #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos 4UL 278 #define TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL 279 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */ 280 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos 0UL 281 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL 282 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL 283 #define TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL 284 /* TCPWM_GRP_CNT.DT */ 285 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos 0UL 286 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk 0xFFUL 287 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos 8UL 288 #define TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk 0xFF00UL 289 #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos 16UL 290 #define TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL 291 /* TCPWM_GRP_CNT.DT_BUFF */ 292 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_OUT_L_Pos 0UL 293 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_OUT_L_Msk 0xFFUL 294 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_OUT_H_Pos 8UL 295 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_OUT_H_Msk 0xFF00UL 296 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_COMPL_OUT_Pos 16UL 297 #define TCPWM_GRP_CNT_DT_BUFF_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL 298 /* TCPWM_GRP_CNT.PS */ 299 #define TCPWM_GRP_CNT_PS_PS_DIV_Pos 0UL 300 #define TCPWM_GRP_CNT_PS_PS_DIV_Msk 0x7UL 301 /* TCPWM_GRP_CNT.TR_CMD */ 302 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos 0UL 303 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk 0x1UL 304 #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos 2UL 305 #define TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk 0x4UL 306 #define TCPWM_GRP_CNT_TR_CMD_STOP_Pos 3UL 307 #define TCPWM_GRP_CNT_TR_CMD_STOP_Msk 0x8UL 308 #define TCPWM_GRP_CNT_TR_CMD_START_Pos 4UL 309 #define TCPWM_GRP_CNT_TR_CMD_START_Msk 0x10UL 310 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos 5UL 311 #define TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk 0x20UL 312 /* TCPWM_GRP_CNT.TR_IN_SEL0 */ 313 #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL 314 #define TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL 315 #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos 8UL 316 #define TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL 317 #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos 16UL 318 #define TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL 319 #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos 24UL 320 #define TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL 321 /* TCPWM_GRP_CNT.TR_IN_SEL1 */ 322 #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos 0UL 323 #define TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk 0xFFUL 324 #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL 325 #define TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL 326 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ 327 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL 328 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL 329 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL 330 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL 331 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL 332 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL 333 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL 334 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL 335 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL 336 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL 337 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL 338 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL 339 /* TCPWM_GRP_CNT.TR_PWM_CTRL */ 340 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL 341 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL 342 #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL 343 #define TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL 344 #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL 345 #define TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL 346 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL 347 #define TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL 348 /* TCPWM_GRP_CNT.TR_OUT_SEL */ 349 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos 0UL 350 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk 0x7UL 351 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos 4UL 352 #define TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk 0x70UL 353 /* TCPWM_GRP_CNT.INTR */ 354 #define TCPWM_GRP_CNT_INTR_TC_Pos 0UL 355 #define TCPWM_GRP_CNT_INTR_TC_Msk 0x1UL 356 #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos 1UL 357 #define TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk 0x2UL 358 #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos 2UL 359 #define TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk 0x4UL 360 /* TCPWM_GRP_CNT.INTR_SET */ 361 #define TCPWM_GRP_CNT_INTR_SET_TC_Pos 0UL 362 #define TCPWM_GRP_CNT_INTR_SET_TC_Msk 0x1UL 363 #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos 1UL 364 #define TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk 0x2UL 365 #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos 2UL 366 #define TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk 0x4UL 367 /* TCPWM_GRP_CNT.INTR_MASK */ 368 #define TCPWM_GRP_CNT_INTR_MASK_TC_Pos 0UL 369 #define TCPWM_GRP_CNT_INTR_MASK_TC_Msk 0x1UL 370 #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos 1UL 371 #define TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk 0x2UL 372 #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos 2UL 373 #define TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk 0x4UL 374 /* TCPWM_GRP_CNT.INTR_MASKED */ 375 #define TCPWM_GRP_CNT_INTR_MASKED_TC_Pos 0UL 376 #define TCPWM_GRP_CNT_INTR_MASKED_TC_Msk 0x1UL 377 #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos 1UL 378 #define TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk 0x2UL 379 #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos 2UL 380 #define TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk 0x4UL 381 /* TCPWM_GRP_CNT.LFSR */ 382 #define TCPWM_GRP_CNT_LFSR_PLFSR_Pos 0UL 383 #define TCPWM_GRP_CNT_LFSR_PLFSR_Msk 0xFFUL 384 #define TCPWM_GRP_CNT_LFSR_DLFSR_Pos 8UL 385 #define TCPWM_GRP_CNT_LFSR_DLFSR_Msk 0xFF00UL 386 #define TCPWM_GRP_CNT_LFSR_LIMITER_Pos 16UL 387 #define TCPWM_GRP_CNT_LFSR_LIMITER_Msk 0x70000UL 388 /* TCPWM_GRP_CNT.ONE_GF */ 389 #define TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Pos 0UL 390 #define TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Msk 0x7UL 391 #define TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Pos 3UL 392 #define TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Msk 0x18UL 393 /* TCPWM_GRP_CNT.TR_ONE_SYNC_BYPASS */ 394 #define TCPWM_GRP_CNT_TR_ONE_SYNC_BYPASS_SYNC_BYPASS_Pos 0UL 395 #define TCPWM_GRP_CNT_TR_ONE_SYNC_BYPASS_SYNC_BYPASS_Msk 0xFFUL 396 397 398 /* TCPWM_TR_ALL_GF.ALL_GF */ 399 #define TCPWM_TR_ALL_GF_ALL_GF_GF_DEPTH_Pos 0UL 400 #define TCPWM_TR_ALL_GF_ALL_GF_GF_DEPTH_Msk 0x7UL 401 #define TCPWM_TR_ALL_GF_ALL_GF_GFPS_DIV_Pos 3UL 402 #define TCPWM_TR_ALL_GF_ALL_GF_GFPS_DIV_Msk 0x18UL 403 404 405 /* TCPWM_TR_ALL_SYNC_BYPASS.TR_ALL_SYNC_BYPASS */ 406 #define TCPWM_TR_ALL_SYNC_BYPASS_TR_ALL_SYNC_BYPASS_SYNC_BYPASS_Pos 0UL 407 #define TCPWM_TR_ALL_SYNC_BYPASS_TR_ALL_SYNC_BYPASS_SYNC_BYPASS_Msk 0xFFFFFFFFUL 408 409 410 /* TCPWM_MOTIF_GRP_MOTIF.PCONF */ 411 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_ENABLE_Pos 0UL 412 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_ENABLE_Msk 0x1UL 413 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_FSEL_Pos 1UL 414 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_FSEL_Msk 0x6UL 415 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_QDCM_Pos 3UL 416 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_QDCM_Msk 0x8UL 417 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_HIDG_Pos 4UL 418 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_HIDG_Msk 0x10UL 419 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MCUE_Pos 5UL 420 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MCUE_Msk 0x20UL 421 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_FTS_Pos 6UL 422 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_FTS_Msk 0xC0UL 423 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_CHEC_Pos 14UL 424 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_CHEC_Msk 0xC000UL 425 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_SPES_Pos 17UL 426 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_SPES_Msk 0x20000UL 427 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MSES_Pos 21UL 428 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MSES_Msk 0x200000UL 429 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MSYES_Pos 22UL 430 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_MSYES_Msk 0x400000UL 431 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_EWIE_Pos 26UL 432 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_EWIE_Msk 0x4000000UL 433 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_EWIL_Pos 27UL 434 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_EWIL_Msk 0x8000000UL 435 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_LPC_Pos 28UL 436 #define TCPWM_MOTIF_GRP_MOTIF_PCONF_LPC_Msk 0xF0000000UL 437 /* TCPWM_MOTIF_GRP_MOTIF.PSUS */ 438 #define TCPWM_MOTIF_GRP_MOTIF_PSUS_SUS_Pos 0UL 439 #define TCPWM_MOTIF_GRP_MOTIF_PSUS_SUS_Msk 0x7UL 440 /* TCPWM_MOTIF_GRP_MOTIF.PRUNS */ 441 #define TCPWM_MOTIF_GRP_MOTIF_PRUNS_SRB_Pos 0UL 442 #define TCPWM_MOTIF_GRP_MOTIF_PRUNS_SRB_Msk 0x1UL 443 /* TCPWM_MOTIF_GRP_MOTIF.PRUN */ 444 #define TCPWM_MOTIF_GRP_MOTIF_PRUN_RB_Pos 0UL 445 #define TCPWM_MOTIF_GRP_MOTIF_PRUN_RB_Msk 0x1UL 446 /* TCPWM_MOTIF_GRP_MOTIF.MIDR */ 447 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODR_Pos 0UL 448 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODR_Msk 0xFFUL 449 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODT_Pos 8UL 450 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODT_Msk 0xFF00UL 451 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODN_Pos 16UL 452 #define TCPWM_MOTIF_GRP_MOTIF_MIDR_MODN_Msk 0xFFFF0000UL 453 /* TCPWM_MOTIF_GRP_MOTIF.HIST */ 454 #define TCPWM_MOTIF_GRP_MOTIF_HIST_HIS_Pos 0UL 455 #define TCPWM_MOTIF_GRP_MOTIF_HIST_HIS_Msk 0x1UL 456 /* TCPWM_MOTIF_GRP_MOTIF.HMEC */ 457 #define TCPWM_MOTIF_GRP_MOTIF_HMEC_HDBP_Pos 0UL 458 #define TCPWM_MOTIF_GRP_MOTIF_HMEC_HDBP_Msk 0x1UL 459 #define TCPWM_MOTIF_GRP_MOTIF_HMEC_HPPE_Pos 1UL 460 #define TCPWM_MOTIF_GRP_MOTIF_HMEC_HPPE_Msk 0x2UL 461 /* TCPWM_MOTIF_GRP_MOTIF.HALP */ 462 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HCP_Pos 0UL 463 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HCP_Msk 0x7UL 464 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HEP_Pos 3UL 465 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HEP_Msk 0x38UL 466 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HPP_Pos 8UL 467 #define TCPWM_MOTIF_GRP_MOTIF_HALP_HPP_Msk 0x700UL 468 /* TCPWM_MOTIF_GRP_MOTIF.HALPS */ 469 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HCPS0_Pos 0UL 470 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HCPS0_Msk 0x7UL 471 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HEPS1_Pos 3UL 472 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HEPS1_Msk 0x38UL 473 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HPPS2_Pos 8UL 474 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HPPS2_Msk 0x700UL 475 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT3_Pos 16UL 476 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT3_Msk 0x70000UL 477 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT4_Pos 19UL 478 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT4_Msk 0x380000UL 479 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT5_Pos 24UL 480 #define TCPWM_MOTIF_GRP_MOTIF_HALPS_HLUT5_Msk 0x7000000UL 481 /* TCPWM_MOTIF_GRP_MOTIF.HOSC */ 482 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_EDN_Pos 0UL 483 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_EDN_Msk 0x7UL 484 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_CHN_Pos 4UL 485 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_CHN_Msk 0x70UL 486 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_IDN_Pos 8UL 487 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_IDN_Msk 0x700UL 488 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_HSTN_Pos 12UL 489 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_HSTN_Msk 0x7000UL 490 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_SPN_Pos 16UL 491 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_SPN_Msk 0x70000UL 492 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_CPN_Pos 20UL 493 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_CPN_Msk 0x700000UL 494 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_PPN_Pos 24UL 495 #define TCPWM_MOTIF_GRP_MOTIF_HOSC_PPN_Msk 0x7000000UL 496 /* TCPWM_MOTIF_GRP_MOTIF.MCM */ 497 #define TCPWM_MOTIF_GRP_MOTIF_MCM_MCMP_Pos 0UL 498 #define TCPWM_MOTIF_GRP_MOTIF_MCM_MCMP_Msk 0xFFFFFFFFUL 499 /* TCPWM_MOTIF_GRP_MOTIF.MCSM */ 500 #define TCPWM_MOTIF_GRP_MOTIF_MCSM_MCMPS_Pos 0UL 501 #define TCPWM_MOTIF_GRP_MOTIF_MCSM_MCMPS_Msk 0xFFFFFFFFUL 502 /* TCPWM_MOTIF_GRP_MOTIF.MCMS */ 503 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_MNPS_Pos 0UL 504 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_MNPS_Msk 0x1UL 505 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_STHR_Pos 1UL 506 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_STHR_Msk 0x2UL 507 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_STMR_Pos 2UL 508 #define TCPWM_MOTIF_GRP_MOTIF_MCMS_STMR_Msk 0x4UL 509 /* TCPWM_MOTIF_GRP_MOTIF.MCMC */ 510 #define TCPWM_MOTIF_GRP_MOTIF_MCMC_MNPC_Pos 0UL 511 #define TCPWM_MOTIF_GRP_MOTIF_MCMC_MNPC_Msk 0x1UL 512 #define TCPWM_MOTIF_GRP_MOTIF_MCMC_MPC_Pos 1UL 513 #define TCPWM_MOTIF_GRP_MOTIF_MCMC_MPC_Msk 0x2UL 514 /* TCPWM_MOTIF_GRP_MOTIF.MCMF */ 515 #define TCPWM_MOTIF_GRP_MOTIF_MCMF_MSS_Pos 0UL 516 #define TCPWM_MOTIF_GRP_MOTIF_MCMF_MSS_Msk 0x1UL 517 /* TCPWM_MOTIF_GRP_MOTIF.MCPF */ 518 #define TCPWM_MOTIF_GRP_MOTIF_MCPF_MCFV_Pos 0UL 519 #define TCPWM_MOTIF_GRP_MOTIF_MCPF_MCFV_Msk 0xFFFFFFFFUL 520 /* TCPWM_MOTIF_GRP_MOTIF.MOSC */ 521 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_PUN_Pos 0UL 522 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_PUN_Msk 0x7UL 523 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_SHN_Pos 4UL 524 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_SHN_Msk 0x70UL 525 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_MSTN_Pos 8UL 526 #define TCPWM_MOTIF_GRP_MOTIF_MOSC_MSTN_Msk 0x700UL 527 /* TCPWM_MOTIF_GRP_MOTIF.QDC */ 528 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PALS_Pos 0UL 529 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PALS_Msk 0x1UL 530 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBLS_Pos 1UL 531 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBLS_Msk 0x2UL 532 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PHS_Pos 2UL 533 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PHS_Msk 0x4UL 534 #define TCPWM_MOTIF_GRP_MOTIF_QDC_INDS_Pos 3UL 535 #define TCPWM_MOTIF_GRP_MOTIF_QDC_INDS_Msk 0x8UL 536 #define TCPWM_MOTIF_GRP_MOTIF_QDC_ICM_Pos 4UL 537 #define TCPWM_MOTIF_GRP_MOTIF_QDC_ICM_Msk 0x30UL 538 #define TCPWM_MOTIF_GRP_MOTIF_QDC_DVAL_Pos 8UL 539 #define TCPWM_MOTIF_GRP_MOTIF_QDC_DVAL_Msk 0x100UL 540 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PAEM_Pos 12UL 541 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PAEM_Msk 0x3000UL 542 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBEM_Pos 14UL 543 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBEM_Msk 0xC000UL 544 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PACS_Pos 16UL 545 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PACS_Msk 0x30000UL 546 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBDS_Pos 20UL 547 #define TCPWM_MOTIF_GRP_MOTIF_QDC_PBDS_Msk 0x300000UL 548 #define TCPWM_MOTIF_GRP_MOTIF_QDC_IDS_Pos 24UL 549 #define TCPWM_MOTIF_GRP_MOTIF_QDC_IDS_Msk 0x3000000UL 550 /* TCPWM_MOTIF_GRP_MOTIF.QOSC */ 551 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_QCN_Pos 0UL 552 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_QCN_Msk 0x7UL 553 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_DON_Pos 4UL 554 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_DON_Msk 0x70UL 555 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_PCN_Pos 8UL 556 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_PCN_Msk 0x700UL 557 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_CCN_Pos 12UL 558 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_CCN_Msk 0x7000UL 559 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_IXN_Pos 16UL 560 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_IXN_Msk 0x70000UL 561 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_QSTN_Pos 20UL 562 #define TCPWM_MOTIF_GRP_MOTIF_QOSC_QSTN_Msk 0x700000UL 563 /* TCPWM_MOTIF_GRP_MOTIF.MCMEC */ 564 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MSBP_Pos 0UL 565 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MSBP_Msk 0x1UL 566 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MEBP_Pos 1UL 567 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MEBP_Msk 0x2UL 568 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MFCE_Pos 4UL 569 #define TCPWM_MOTIF_GRP_MOTIF_MCMEC_MFCE_Msk 0x10UL 570 /* TCPWM_MOTIF_GRP_MOTIF.PFLG */ 571 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CHES_Pos 0UL 572 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CHES_Msk 0x1UL 573 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_WHES_Pos 1UL 574 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_WHES_Msk 0x2UL 575 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_HIES_Pos 2UL 576 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_HIES_Msk 0x4UL 577 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_MSTS_Pos 4UL 578 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_MSTS_Msk 0x10UL 579 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_INDXS_Pos 8UL 580 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_INDXS_Msk 0x100UL 581 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_ERRS_Pos 9UL 582 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_ERRS_Msk 0x200UL 583 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CNTS_Pos 10UL 584 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CNTS_Msk 0x400UL 585 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_DIRS_Pos 11UL 586 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_DIRS_Msk 0x800UL 587 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_PCLKS_Pos 12UL 588 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_PCLKS_Msk 0x1000UL 589 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CPES_Pos 13UL 590 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_CPES_Msk 0x2000UL 591 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_PPES_Pos 14UL 592 #define TCPWM_MOTIF_GRP_MOTIF_PFLG_PPES_Msk 0x4000UL 593 /* TCPWM_MOTIF_GRP_MOTIF.PFLGE */ 594 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECHE_Pos 0UL 595 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECHE_Msk 0x1UL 596 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EWHE_Pos 1UL 597 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EWHE_Msk 0x2UL 598 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EHIE_Pos 2UL 599 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EHIE_Msk 0x4UL 600 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EMST_Pos 4UL 601 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EMST_Msk 0x10UL 602 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EINDX_Pos 8UL 603 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EINDX_Msk 0x100UL 604 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EERR_Pos 9UL 605 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EERR_Msk 0x200UL 606 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECNT_Pos 10UL 607 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECNT_Msk 0x400UL 608 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EDIR_Pos 11UL 609 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EDIR_Msk 0x800UL 610 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EPCLK_Pos 12UL 611 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EPCLK_Msk 0x1000UL 612 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECPE_Pos 13UL 613 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ECPE_Msk 0x2000UL 614 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EPPE_Pos 14UL 615 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_EPPE_Msk 0x4000UL 616 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CHESEL_Pos 16UL 617 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CHESEL_Msk 0x10000UL 618 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_WHESEL_Pos 17UL 619 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_WHESEL_Msk 0x20000UL 620 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_HIESEL_Pos 18UL 621 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_HIESEL_Msk 0x40000UL 622 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_MSTSEL_Pos 20UL 623 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_MSTSEL_Msk 0x100000UL 624 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_INDSEL_Pos 24UL 625 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_INDSEL_Msk 0x1000000UL 626 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ERRSEL_Pos 25UL 627 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_ERRSEL_Msk 0x2000000UL 628 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CNTSEL_Pos 26UL 629 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CNTSEL_Msk 0x4000000UL 630 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_DIRSEL_Pos 27UL 631 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_DIRSEL_Msk 0x8000000UL 632 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_PCLSEL_Pos 28UL 633 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_PCLSEL_Msk 0x10000000UL 634 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CPSEL_Pos 29UL 635 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_CPSEL_Msk 0x20000000UL 636 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_PPSEL_Pos 30UL 637 #define TCPWM_MOTIF_GRP_MOTIF_PFLGE_PPSEL_Msk 0x40000000UL 638 /* TCPWM_MOTIF_GRP_MOTIF.SPFLG */ 639 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCHE_Pos 0UL 640 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCHE_Msk 0x1UL 641 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SWHE_Pos 1UL 642 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SWHE_Msk 0x2UL 643 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SHIE_Pos 2UL 644 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SHIE_Msk 0x4UL 645 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SMST_Pos 4UL 646 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SMST_Msk 0x10UL 647 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SINDX_Pos 8UL 648 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SINDX_Msk 0x100UL 649 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SERR_Pos 9UL 650 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SERR_Msk 0x200UL 651 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCNT_Pos 10UL 652 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCNT_Msk 0x400UL 653 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SDIR_Pos 11UL 654 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SDIR_Msk 0x800UL 655 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SPCLK_Pos 12UL 656 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SPCLK_Msk 0x1000UL 657 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCP_Pos 13UL 658 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SCP_Msk 0x2000UL 659 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SPP_Pos 14UL 660 #define TCPWM_MOTIF_GRP_MOTIF_SPFLG_SPP_Msk 0x4000UL 661 /* TCPWM_MOTIF_GRP_MOTIF.RPFLG */ 662 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCHE_Pos 0UL 663 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCHE_Msk 0x1UL 664 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RWHE_Pos 1UL 665 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RWHE_Msk 0x2UL 666 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RHIE_Pos 2UL 667 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RHIE_Msk 0x4UL 668 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RMST_Pos 4UL 669 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RMST_Msk 0x10UL 670 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RINDX_Pos 8UL 671 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RINDX_Msk 0x100UL 672 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RERR_Pos 9UL 673 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RERR_Msk 0x200UL 674 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCNT_Pos 10UL 675 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCNT_Msk 0x400UL 676 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RDIR_Pos 11UL 677 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RDIR_Msk 0x800UL 678 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RPCLK_Pos 12UL 679 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RPCLK_Msk 0x1000UL 680 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCP_Pos 13UL 681 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RCP_Msk 0x2000UL 682 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RPP_Pos 14UL 683 #define TCPWM_MOTIF_GRP_MOTIF_RPFLG_RPP_Msk 0x4000UL 684 /* TCPWM_MOTIF_GRP_MOTIF.MCSM1 */ 685 #define TCPWM_MOTIF_GRP_MOTIF_MCSM1_MLUT1_Pos 0UL 686 #define TCPWM_MOTIF_GRP_MOTIF_MCSM1_MLUT1_Msk 0xFFFFFFFFUL 687 /* TCPWM_MOTIF_GRP_MOTIF.MCSM2 */ 688 #define TCPWM_MOTIF_GRP_MOTIF_MCSM2_MLUT2_Pos 0UL 689 #define TCPWM_MOTIF_GRP_MOTIF_MCSM2_MLUT2_Msk 0xFFFFFFFFUL 690 /* TCPWM_MOTIF_GRP_MOTIF.MCSM3 */ 691 #define TCPWM_MOTIF_GRP_MOTIF_MCSM3_MLUT3_Pos 0UL 692 #define TCPWM_MOTIF_GRP_MOTIF_MCSM3_MLUT3_Msk 0xFFFFFFFFUL 693 /* TCPWM_MOTIF_GRP_MOTIF.MCSM4 */ 694 #define TCPWM_MOTIF_GRP_MOTIF_MCSM4_MLUT4_Pos 0UL 695 #define TCPWM_MOTIF_GRP_MOTIF_MCSM4_MLUT4_Msk 0xFFFFFFFFUL 696 /* TCPWM_MOTIF_GRP_MOTIF.MCSM5 */ 697 #define TCPWM_MOTIF_GRP_MOTIF_MCSM5_MLUT5_Pos 0UL 698 #define TCPWM_MOTIF_GRP_MOTIF_MCSM5_MLUT5_Msk 0xFFFFFFFFUL 699 /* TCPWM_MOTIF_GRP_MOTIF.CLUT */ 700 #define TCPWM_MOTIF_GRP_MOTIF_CLUT_LUTEN_Pos 0UL 701 #define TCPWM_MOTIF_GRP_MOTIF_CLUT_LUTEN_Msk 0x1UL 702 /* TCPWM_MOTIF_GRP_MOTIF.SLUT */ 703 #define TCPWM_MOTIF_GRP_MOTIF_SLUT_PTR_Pos 0UL 704 #define TCPWM_MOTIF_GRP_MOTIF_SLUT_PTR_Msk 0x7UL 705 /* TCPWM_MOTIF_GRP_MOTIF.PDBG */ 706 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_QCSV_Pos 0UL 707 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_QCSV_Msk 0x7UL 708 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_QPSV_Pos 3UL 709 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_QPSV_Msk 0x38UL 710 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_IVAL_Pos 6UL 711 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_IVAL_Msk 0x40UL 712 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_HSP_Pos 8UL 713 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_HSP_Msk 0x700UL 714 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF0V_Pos 12UL 715 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF0V_Msk 0x1000UL 716 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF1V_Pos 13UL 717 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF1V_Msk 0x2000UL 718 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF2V_Pos 14UL 719 #define TCPWM_MOTIF_GRP_MOTIF_PDBG_LPF2V_Msk 0x4000UL 720 /* TCPWM_MOTIF_GRP_MOTIF.PLP0S */ 721 #define TCPWM_MOTIF_GRP_MOTIF_PLP0S_LPP0_Pos 0UL 722 #define TCPWM_MOTIF_GRP_MOTIF_PLP0S_LPP0_Msk 0x3FFUL 723 /* TCPWM_MOTIF_GRP_MOTIF.PLP1S */ 724 #define TCPWM_MOTIF_GRP_MOTIF_PLP1S_LPP1_Pos 0UL 725 #define TCPWM_MOTIF_GRP_MOTIF_PLP1S_LPP1_Msk 0x3FFUL 726 /* TCPWM_MOTIF_GRP_MOTIF.PLP2S */ 727 #define TCPWM_MOTIF_GRP_MOTIF_PLP2S_LPP2_Pos 0UL 728 #define TCPWM_MOTIF_GRP_MOTIF_PLP2S_LPP2_Msk 0x3FFUL 729 730 731 #endif /* _CYIP_TCPWM_V3_H_ */ 732 733 734 /* [] END OF FILE */ 735
