Home
last modified time | relevance | path

Searched refs:SYSTICK_CTL (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c138 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V1_Type, SYSTICK_CTL),
255 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
371 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
487 /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL),
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h89 __IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */ member
Dcyip_cpuss_v2.h105 __IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h115 __IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */ member
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h437 #define CPUSS_SYSTICK_CTL (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_CTL)