1 /***************************************************************************//** 2 * \file cyip_smif_v3.h 3 * 4 * \brief 5 * SMIF IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SMIF_V3_H_ 28 #define _CYIP_SMIF_V3_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SMIF 34 *******************************************************************************/ 35 36 #define SMIF_SMIF_CRYPTO_SECTION_SIZE 0x00000080UL 37 #define SMIF_DEVICE_SECTION_SIZE 0x00000080UL 38 #define SMIF_MPC_SECTION_SIZE 0x00001000UL 39 #define SMIF_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief Cryptography registers (one set for each key) (SMIF_SMIF_CRYPTO) 43 */ 44 typedef struct { 45 __IOM uint32_t CRYPTO_CMD; /*!< 0x00000000 Cryptography command */ 46 __IOM uint32_t CRYPTO_ADDR; /*!< 0x00000004 Cryptography base address */ 47 __IOM uint32_t CRYPTO_MASK; /*!< 0x00000008 Cryptography mask */ 48 __IOM uint32_t CRYPTO_SUBREGION; /*!< 0x0000000C Cryptography subregion disable */ 49 __IM uint32_t RESERVED[4]; 50 __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000020 Cryptography input 0 */ 51 __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000024 Cryptography input 1 */ 52 __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000028 Cryptography input 2 */ 53 __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000002C Cryptography input 3 */ 54 __IM uint32_t RESERVED1[4]; 55 __OM uint32_t CRYPTO_KEY0; /*!< 0x00000040 Cryptography key 0 */ 56 __OM uint32_t CRYPTO_KEY1; /*!< 0x00000044 Cryptography key 1 */ 57 __OM uint32_t CRYPTO_KEY2; /*!< 0x00000048 Cryptography key 2 */ 58 __OM uint32_t CRYPTO_KEY3; /*!< 0x0000004C Cryptography key 3 */ 59 __IM uint32_t RESERVED2[4]; 60 __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000060 Cryptography output 0 */ 61 __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000064 Cryptography output 1 */ 62 __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000068 Cryptography output 2 */ 63 __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000006C Cryptography output 3 */ 64 __IM uint32_t RESERVED3[4]; 65 } SMIF_SMIF_CRYPTO_Type; /*!< Size = 128 (0x80) */ 66 67 /** 68 * \brief Device (only used for XIP acceses) (SMIF_DEVICE) 69 */ 70 typedef struct { 71 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 72 __IM uint32_t RESERVED; 73 __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */ 74 __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */ 75 __IM uint32_t RESERVED1[4]; 76 __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */ 77 __IM uint32_t RESERVED2[2]; 78 __IOM uint32_t DELAY_TAP_SEL; /*!< 0x0000002C RX Clock Delay Tap Select Register */ 79 __IM uint32_t RD_STATUS; /*!< 0x00000030 Read status */ 80 __IM uint32_t RESERVED3[3]; 81 __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */ 82 __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */ 83 __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */ 84 __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */ 85 __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */ 86 __IOM uint32_t RD_CRC_CTL; /*!< 0x00000054 Read Bus CRC control */ 87 __IOM uint32_t RD_BOUND_CTL; /*!< 0x00000058 Read boundary control */ 88 __IM uint32_t RESERVED4; 89 __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */ 90 __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */ 91 __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */ 92 __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */ 93 __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */ 94 __IOM uint32_t WR_CRC_CTL; /*!< 0x00000074 Write Bus CRC control */ 95 __IM uint32_t RESERVED5[2]; 96 } SMIF_DEVICE_Type; /*!< Size = 128 (0x80) */ 97 98 /** 99 * \brief MPC Memory Protection Controller registers (SMIF_MPC) 100 */ 101 typedef struct { 102 __IOM uint32_t CFG; /*!< 0x00000000 Config register with error response, RegionID PPC_MPC_MAIN is 103 the security owner PC. The error response configuration is 104 located in CFG.RESPONSE, only one such configuration exists 105 applying to all protection contexts in the system. */ 106 __IM uint32_t RESERVED[3]; 107 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 108 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 109 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 110 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 111 __IM uint32_t INTR_INFO1; /*!< 0x00000020 Infor about violation */ 112 __IM uint32_t INTR_INFO2; /*!< 0x00000024 Infor about violation */ 113 __IM uint32_t RESERVED1[54]; 114 __IOM uint32_t CTRL; /*!< 0x00000100 Control register with lock bit and auto-increment only 115 (Separate CTRL for each PC depends on access_pc) */ 116 __IM uint32_t BLK_MAX; /*!< 0x00000104 Max value of block-based index register */ 117 __IM uint32_t BLK_CFG; /*!< 0x00000108 Block size & initialization in progress */ 118 __IOM uint32_t BLK_IDX; /*!< 0x0000010C Index of 32-block group accessed through BLK_LUT (Separate IDX 119 for each PC depending on access_pc) */ 120 __IOM uint32_t BLK_LUT; /*!< 0x00000110 NS status for 32 blocks at BLK_IDX with PC=<access_pc> */ 121 __IM uint32_t RESERVED2[59]; 122 __IOM uint32_t ROT_CTRL; /*!< 0x00000200 Control register with lock bit and auto-increment only */ 123 __IOM uint32_t ROT_CFG; /*!< 0x00000204 Sets block-size to match memory size (external memory only) */ 124 __IM uint32_t ROT_BLK_MAX; /*!< 0x00000208 Max value of block-based index register for ROT */ 125 __IM uint32_t ROT_BLK_CFG; /*!< 0x0000020C Same as BLK_CFG */ 126 __IOM uint32_t ROT_BLK_IDX; /*!< 0x00000210 Index of 8-block group accessed through ROT_BLK_LUT_* */ 127 __IOM uint32_t ROT_BLK_PC; /*!< 0x00000214 Protection context of 8-block group accesses through 128 ROT_BLK_LUT */ 129 __IOM uint32_t ROT_BLK_LUT; /*!< 0x00000218 (R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC */ 130 __IM uint32_t RESERVED3[889]; 131 } SMIF_MPC_Type; /*!< Size = 4096 (0x1000) */ 132 133 /** 134 * \brief Serial Memory Interface (SMIF) 135 */ 136 typedef struct { 137 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 138 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 139 __IM uint32_t RESERVED[2]; 140 __IOM uint32_t INT_CLOCK_DELAY_TAP_SEL0; /*!< 0x00000010 Internal Clocking Delay Tap Select Register 0 */ 141 __IOM uint32_t INT_CLOCK_DELAY_TAP_SEL1; /*!< 0x00000014 Internal Clocking Delay Tap Select Register 1 */ 142 __IOM uint32_t DL_CTL; /*!< 0x00000018 Data Learning Control Register */ 143 __IM uint32_t RESERVED1; 144 __IM uint32_t DL_STATUS0; /*!< 0x00000020 Data Learning Status Register 0 */ 145 __IM uint32_t DL_STATUS1; /*!< 0x00000024 Data Learning Status Register 1 */ 146 __IM uint32_t RESERVED2[7]; 147 __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */ 148 __IM uint32_t TX_CMD_MMIO_FIFO_STATUS; /*!< 0x00000048 Transmitter command MMIO FIFO status */ 149 __IM uint32_t RESERVED3; 150 __OM uint32_t TX_CMD_MMIO_FIFO_WR; /*!< 0x00000050 Transmitter command MMIO FIFO write */ 151 __IM uint32_t RESERVED4[11]; 152 __IOM uint32_t TX_DATA_MMIO_FIFO_CTL; /*!< 0x00000080 Transmitter data MMIO FIFO control */ 153 __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */ 154 __IM uint32_t TX_DATA_MMIO_FIFO_STATUS; /*!< 0x00000088 Transmitter data MMIO FIFO status */ 155 __IM uint32_t RESERVED5; 156 __OM uint32_t TX_DATA_MMIO_FIFO_WR1; /*!< 0x00000090 Transmitter data MMIO FIFO write */ 157 __OM uint32_t TX_DATA_MMIO_FIFO_WR2; /*!< 0x00000094 Transmitter data MMIO FIFO write */ 158 __OM uint32_t TX_DATA_MMIO_FIFO_WR4; /*!< 0x00000098 Transmitter data MMIO FIFO write */ 159 __OM uint32_t TX_DATA_MMIO_FIFO_WR1ODD; /*!< 0x0000009C Transmitter data MMIO FIFO write */ 160 __IM uint32_t RESERVED6[8]; 161 __IOM uint32_t RX_DATA_MMIO_FIFO_CTL; /*!< 0x000000C0 Receiver data MMIO FIFO control */ 162 __IM uint32_t RX_DATA_MMIO_FIFO_STATUS; /*!< 0x000000C4 Receiver data MMIO FIFO status */ 163 __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C8 Receiver data FIFO status */ 164 __IM uint32_t RESERVED7; 165 __IM uint32_t RX_DATA_MMIO_FIFO_RD1; /*!< 0x000000D0 Receiver data MMIO FIFO read */ 166 __IM uint32_t RX_DATA_MMIO_FIFO_RD2; /*!< 0x000000D4 Receiver data MMIO FIFO read */ 167 __IM uint32_t RX_DATA_MMIO_FIFO_RD4; /*!< 0x000000D8 Receiver data MMIO FIFO read */ 168 __IM uint32_t RESERVED8; 169 __IM uint32_t RX_DATA_MMIO_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data MMIO FIFO silent read */ 170 __IM uint32_t RESERVED9[7]; 171 __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */ 172 __IM uint32_t RESERVED10; 173 __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */ 174 __IM uint32_t RESERVED11[29]; 175 __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */ 176 __IM uint32_t RESERVED12; 177 __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */ 178 __IM uint32_t RESERVED13[29]; 179 SMIF_SMIF_CRYPTO_Type SMIF_CRYPTO_BLOCK[8]; /*!< 0x00000200 Cryptography registers (one set for each key) */ 180 __IOM uint32_t CRC_CMD; /*!< 0x00000600 CRC Command */ 181 __IM uint32_t RESERVED14[7]; 182 __IOM uint32_t CRC_INPUT0; /*!< 0x00000620 CRC input 0 */ 183 __IOM uint32_t CRC_INPUT1; /*!< 0x00000624 CRC input 1 */ 184 __IM uint32_t RESERVED15[6]; 185 __IM uint32_t CRC_OUTPUT; /*!< 0x00000640 CRC output */ 186 __IM uint32_t RESERVED16[95]; 187 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 188 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 189 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 190 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 191 __IM uint32_t INTR_CAUSE; /*!< 0x000007D0 Distinguishes normal vs. MPC interrupt */ 192 __IM uint32_t RESERVED17[11]; 193 SMIF_DEVICE_Type DEVICE[4]; /*!< 0x00000800 Device (only used for XIP acceses) */ 194 __IM uint32_t RESERVED18[384]; 195 SMIF_MPC_Type MPC[1]; /*!< 0x00001000 MPC Memory Protection Controller registers */ 196 } SMIF_Type; /*!< Size = 8192 (0x2000) */ 197 198 199 /* SMIF_SMIF_CRYPTO.CRYPTO_CMD */ 200 #define SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Pos 0UL 201 #define SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Msk 0x1UL 202 /* SMIF_SMIF_CRYPTO.CRYPTO_ADDR */ 203 #define SMIF_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Pos 8UL 204 #define SMIF_SMIF_CRYPTO_CRYPTO_ADDR_ADDR_Msk 0xFFFFFF00UL 205 /* SMIF_SMIF_CRYPTO.CRYPTO_MASK */ 206 #define SMIF_SMIF_CRYPTO_CRYPTO_MASK_MASK_Pos 8UL 207 #define SMIF_SMIF_CRYPTO_CRYPTO_MASK_MASK_Msk 0xFFFFFF00UL 208 /* SMIF_SMIF_CRYPTO.CRYPTO_SUBREGION */ 209 #define SMIF_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Pos 0UL 210 #define SMIF_SMIF_CRYPTO_CRYPTO_SUBREGION_SUBREGION_DISABLE_Msk 0xFFUL 211 /* SMIF_SMIF_CRYPTO.CRYPTO_INPUT0 */ 212 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Pos 0UL 213 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_LSB_Msk 0xFUL 214 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Pos 4UL 215 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT0_INPUT_MSB_Msk 0xFFFFFFF0UL 216 /* SMIF_SMIF_CRYPTO.CRYPTO_INPUT1 */ 217 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Pos 0UL 218 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL 219 /* SMIF_SMIF_CRYPTO.CRYPTO_INPUT2 */ 220 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Pos 0UL 221 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL 222 /* SMIF_SMIF_CRYPTO.CRYPTO_INPUT3 */ 223 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Pos 0UL 224 #define SMIF_SMIF_CRYPTO_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL 225 /* SMIF_SMIF_CRYPTO.CRYPTO_KEY0 */ 226 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Pos 0UL 227 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL 228 /* SMIF_SMIF_CRYPTO.CRYPTO_KEY1 */ 229 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Pos 0UL 230 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL 231 /* SMIF_SMIF_CRYPTO.CRYPTO_KEY2 */ 232 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Pos 0UL 233 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL 234 /* SMIF_SMIF_CRYPTO.CRYPTO_KEY3 */ 235 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Pos 0UL 236 #define SMIF_SMIF_CRYPTO_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL 237 /* SMIF_SMIF_CRYPTO.CRYPTO_OUTPUT0 */ 238 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL 239 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL 240 /* SMIF_SMIF_CRYPTO.CRYPTO_OUTPUT1 */ 241 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL 242 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL 243 /* SMIF_SMIF_CRYPTO.CRYPTO_OUTPUT2 */ 244 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL 245 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL 246 /* SMIF_SMIF_CRYPTO.CRYPTO_OUTPUT3 */ 247 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL 248 #define SMIF_SMIF_CRYPTO_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL 249 250 251 /* SMIF_DEVICE.CTL */ 252 #define SMIF_DEVICE_CTL_WR_EN_Pos 0UL 253 #define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL 254 #define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 4UL 255 #define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x10UL 256 #define SMIF_DEVICE_CTL_DATA_SEL_Pos 8UL 257 #define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x300UL 258 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Pos 12UL 259 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Msk 0x7000UL 260 #define SMIF_DEVICE_CTL_MERGE_EN_Pos 15UL 261 #define SMIF_DEVICE_CTL_MERGE_EN_Msk 0x8000UL 262 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Pos 16UL 263 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Msk 0x3FFF0000UL 264 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos 30UL 265 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk 0x40000000UL 266 #define SMIF_DEVICE_CTL_ENABLED_Pos 31UL 267 #define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL 268 /* SMIF_DEVICE.ADDR */ 269 #define SMIF_DEVICE_ADDR_ADDR_Pos 8UL 270 #define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL 271 /* SMIF_DEVICE.MASK */ 272 #define SMIF_DEVICE_MASK_MASK_Pos 8UL 273 #define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL 274 /* SMIF_DEVICE.ADDR_CTL */ 275 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Pos 0UL 276 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Msk 0x7UL 277 #define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL 278 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL 279 /* SMIF_DEVICE.DELAY_TAP_SEL */ 280 #define SMIF_DEVICE_DELAY_TAP_SEL_SEL_Pos 0UL 281 #define SMIF_DEVICE_DELAY_TAP_SEL_SEL_Msk 0xFFUL 282 /* SMIF_DEVICE.RD_STATUS */ 283 #define SMIF_DEVICE_RD_STATUS_FS_STATUS_Pos 0UL 284 #define SMIF_DEVICE_RD_STATUS_FS_STATUS_Msk 0xFFUL 285 /* SMIF_DEVICE.RD_CMD_CTL */ 286 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL 287 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL 288 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Pos 8UL 289 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Msk 0xFF00UL 290 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL 291 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL 292 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Pos 18UL 293 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Msk 0x40000UL 294 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Pos 30UL 295 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Msk 0xC0000000UL 296 /* SMIF_DEVICE.RD_ADDR_CTL */ 297 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL 298 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL 299 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos 18UL 300 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk 0x40000UL 301 /* SMIF_DEVICE.RD_MODE_CTL */ 302 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL 303 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL 304 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Pos 8UL 305 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Msk 0xFF00UL 306 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL 307 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL 308 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Pos 18UL 309 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Msk 0x40000UL 310 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Pos 30UL 311 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Msk 0xC0000000UL 312 /* SMIF_DEVICE.RD_DUMMY_CTL */ 313 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL 314 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL 315 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos 30UL 316 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 317 /* SMIF_DEVICE.RD_DATA_CTL */ 318 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL 319 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL 320 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Pos 18UL 321 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Msk 0x40000UL 322 /* SMIF_DEVICE.RD_CRC_CTL */ 323 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Pos 0UL 324 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_CHECK_MASK_Msk 0xFFUL 325 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Pos 8UL 326 #define SMIF_DEVICE_RD_CRC_CTL_STATUS_ERROR_POL_Msk 0xFF00UL 327 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 328 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 329 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 330 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 331 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 332 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 333 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 334 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 335 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Pos 28UL 336 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_CHECK_Msk 0x10000000UL 337 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 338 #define SMIF_DEVICE_RD_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 339 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 340 #define SMIF_DEVICE_RD_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 341 /* SMIF_DEVICE.RD_BOUND_CTL */ 342 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Pos 0UL 343 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Msk 0x1FUL 344 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos 16UL 345 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk 0x30000UL 346 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos 20UL 347 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk 0x300000UL 348 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos 28UL 349 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk 0x10000000UL 350 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Pos 31UL 351 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Msk 0x80000000UL 352 /* SMIF_DEVICE.WR_CMD_CTL */ 353 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL 354 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL 355 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Pos 8UL 356 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Msk 0xFF00UL 357 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL 358 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL 359 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Pos 18UL 360 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Msk 0x40000UL 361 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Pos 30UL 362 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Msk 0xC0000000UL 363 /* SMIF_DEVICE.WR_ADDR_CTL */ 364 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL 365 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL 366 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos 18UL 367 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk 0x40000UL 368 /* SMIF_DEVICE.WR_MODE_CTL */ 369 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL 370 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL 371 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Pos 8UL 372 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Msk 0xFF00UL 373 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL 374 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL 375 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Pos 18UL 376 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Msk 0x40000UL 377 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Pos 30UL 378 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Msk 0xC0000000UL 379 /* SMIF_DEVICE.WR_DUMMY_CTL */ 380 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL 381 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL 382 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos 17UL 383 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk 0x20000UL 384 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos 30UL 385 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk 0xC0000000UL 386 /* SMIF_DEVICE.WR_DATA_CTL */ 387 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL 388 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL 389 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Pos 18UL 390 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Msk 0x40000UL 391 /* SMIF_DEVICE.WR_CRC_CTL */ 392 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Pos 16UL 393 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_INPUT_SIZE_Msk 0xFF0000UL 394 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Pos 24UL 395 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_WIDTH_Msk 0x3000000UL 396 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Pos 26UL 397 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_DDR_MODE_Msk 0x4000000UL 398 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Pos 27UL 399 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_INPUT_Msk 0x8000000UL 400 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Pos 30UL 401 #define SMIF_DEVICE_WR_CRC_CTL_CMD_ADDR_CRC_PRESENT_Msk 0x40000000UL 402 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Pos 31UL 403 #define SMIF_DEVICE_WR_CRC_CTL_DATA_CRC_PRESENT_Msk 0x80000000UL 404 405 406 /* SMIF_MPC.CFG */ 407 #define SMIF_MPC_CFG_RESPONSE_Pos 4UL 408 #define SMIF_MPC_CFG_RESPONSE_Msk 0x10UL 409 /* SMIF_MPC.INTR */ 410 #define SMIF_MPC_INTR_VIOLATION_Pos 0UL 411 #define SMIF_MPC_INTR_VIOLATION_Msk 0x1UL 412 /* SMIF_MPC.INTR_SET */ 413 #define SMIF_MPC_INTR_SET_VIOLATION_Pos 0UL 414 #define SMIF_MPC_INTR_SET_VIOLATION_Msk 0x1UL 415 /* SMIF_MPC.INTR_MASK */ 416 #define SMIF_MPC_INTR_MASK_VIOLATION_Pos 0UL 417 #define SMIF_MPC_INTR_MASK_VIOLATION_Msk 0x1UL 418 /* SMIF_MPC.INTR_MASKED */ 419 #define SMIF_MPC_INTR_MASKED_VIOLATION_Pos 0UL 420 #define SMIF_MPC_INTR_MASKED_VIOLATION_Msk 0x1UL 421 /* SMIF_MPC.INTR_INFO1 */ 422 #define SMIF_MPC_INTR_INFO1_VALUE_Pos 0UL 423 #define SMIF_MPC_INTR_INFO1_VALUE_Msk 0xFFFFFFFFUL 424 /* SMIF_MPC.INTR_INFO2 */ 425 #define SMIF_MPC_INTR_INFO2_HMASTER_Pos 0UL 426 #define SMIF_MPC_INTR_INFO2_HMASTER_Msk 0xFFFFUL 427 #define SMIF_MPC_INTR_INFO2_HNONSEC_Pos 16UL 428 #define SMIF_MPC_INTR_INFO2_HNONSEC_Msk 0x10000UL 429 #define SMIF_MPC_INTR_INFO2_CFG_NS_Pos 17UL 430 #define SMIF_MPC_INTR_INFO2_CFG_NS_Msk 0x20000UL 431 #define SMIF_MPC_INTR_INFO2_HWRITE_Pos 18UL 432 #define SMIF_MPC_INTR_INFO2_HWRITE_Msk 0x40000UL 433 #define SMIF_MPC_INTR_INFO2_HAUSER_Pos 24UL 434 #define SMIF_MPC_INTR_INFO2_HAUSER_Msk 0xF000000UL 435 #define SMIF_MPC_INTR_INFO2_SECURITY_VIOLATION_Pos 30UL 436 #define SMIF_MPC_INTR_INFO2_SECURITY_VIOLATION_Msk 0x40000000UL 437 #define SMIF_MPC_INTR_INFO2_ACCESS_VIOLATION_Pos 31UL 438 #define SMIF_MPC_INTR_INFO2_ACCESS_VIOLATION_Msk 0x80000000UL 439 /* SMIF_MPC.CTRL */ 440 #define SMIF_MPC_CTRL_AUTO_INC_Pos 8UL 441 #define SMIF_MPC_CTRL_AUTO_INC_Msk 0x100UL 442 #define SMIF_MPC_CTRL_LOCK_Pos 31UL 443 #define SMIF_MPC_CTRL_LOCK_Msk 0x80000000UL 444 /* SMIF_MPC.BLK_MAX */ 445 #define SMIF_MPC_BLK_MAX_VALUE_Pos 0UL 446 #define SMIF_MPC_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 447 /* SMIF_MPC.BLK_CFG */ 448 #define SMIF_MPC_BLK_CFG_BLOCK_SIZE_Pos 0UL 449 #define SMIF_MPC_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 450 #define SMIF_MPC_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 451 #define SMIF_MPC_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 452 /* SMIF_MPC.BLK_IDX */ 453 #define SMIF_MPC_BLK_IDX_VALUE_Pos 0UL 454 #define SMIF_MPC_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 455 /* SMIF_MPC.BLK_LUT */ 456 #define SMIF_MPC_BLK_LUT_ATTR_NS0_Pos 0UL 457 #define SMIF_MPC_BLK_LUT_ATTR_NS0_Msk 0x1UL 458 #define SMIF_MPC_BLK_LUT_ATTR_NS1_Pos 1UL 459 #define SMIF_MPC_BLK_LUT_ATTR_NS1_Msk 0x2UL 460 #define SMIF_MPC_BLK_LUT_ATTR_NS2_Pos 2UL 461 #define SMIF_MPC_BLK_LUT_ATTR_NS2_Msk 0x4UL 462 #define SMIF_MPC_BLK_LUT_ATTR_NS3_Pos 3UL 463 #define SMIF_MPC_BLK_LUT_ATTR_NS3_Msk 0x8UL 464 #define SMIF_MPC_BLK_LUT_ATTR_NS4_Pos 4UL 465 #define SMIF_MPC_BLK_LUT_ATTR_NS4_Msk 0x10UL 466 #define SMIF_MPC_BLK_LUT_ATTR_NS5_Pos 5UL 467 #define SMIF_MPC_BLK_LUT_ATTR_NS5_Msk 0x20UL 468 #define SMIF_MPC_BLK_LUT_ATTR_NS6_Pos 6UL 469 #define SMIF_MPC_BLK_LUT_ATTR_NS6_Msk 0x40UL 470 #define SMIF_MPC_BLK_LUT_ATTR_NS7_Pos 7UL 471 #define SMIF_MPC_BLK_LUT_ATTR_NS7_Msk 0x80UL 472 #define SMIF_MPC_BLK_LUT_ATTR_NS8_Pos 8UL 473 #define SMIF_MPC_BLK_LUT_ATTR_NS8_Msk 0x100UL 474 #define SMIF_MPC_BLK_LUT_ATTR_NS9_Pos 9UL 475 #define SMIF_MPC_BLK_LUT_ATTR_NS9_Msk 0x200UL 476 #define SMIF_MPC_BLK_LUT_ATTR_NS10_Pos 10UL 477 #define SMIF_MPC_BLK_LUT_ATTR_NS10_Msk 0x400UL 478 #define SMIF_MPC_BLK_LUT_ATTR_NS11_Pos 11UL 479 #define SMIF_MPC_BLK_LUT_ATTR_NS11_Msk 0x800UL 480 #define SMIF_MPC_BLK_LUT_ATTR_NS12_Pos 12UL 481 #define SMIF_MPC_BLK_LUT_ATTR_NS12_Msk 0x1000UL 482 #define SMIF_MPC_BLK_LUT_ATTR_NS13_Pos 13UL 483 #define SMIF_MPC_BLK_LUT_ATTR_NS13_Msk 0x2000UL 484 #define SMIF_MPC_BLK_LUT_ATTR_NS14_Pos 14UL 485 #define SMIF_MPC_BLK_LUT_ATTR_NS14_Msk 0x4000UL 486 #define SMIF_MPC_BLK_LUT_ATTR_NS15_Pos 15UL 487 #define SMIF_MPC_BLK_LUT_ATTR_NS15_Msk 0x8000UL 488 #define SMIF_MPC_BLK_LUT_ATTR_NS16_Pos 16UL 489 #define SMIF_MPC_BLK_LUT_ATTR_NS16_Msk 0x10000UL 490 #define SMIF_MPC_BLK_LUT_ATTR_NS17_Pos 17UL 491 #define SMIF_MPC_BLK_LUT_ATTR_NS17_Msk 0x20000UL 492 #define SMIF_MPC_BLK_LUT_ATTR_NS18_Pos 18UL 493 #define SMIF_MPC_BLK_LUT_ATTR_NS18_Msk 0x40000UL 494 #define SMIF_MPC_BLK_LUT_ATTR_NS19_Pos 19UL 495 #define SMIF_MPC_BLK_LUT_ATTR_NS19_Msk 0x80000UL 496 #define SMIF_MPC_BLK_LUT_ATTR_NS20_Pos 20UL 497 #define SMIF_MPC_BLK_LUT_ATTR_NS20_Msk 0x100000UL 498 #define SMIF_MPC_BLK_LUT_ATTR_NS21_Pos 21UL 499 #define SMIF_MPC_BLK_LUT_ATTR_NS21_Msk 0x200000UL 500 #define SMIF_MPC_BLK_LUT_ATTR_NS22_Pos 22UL 501 #define SMIF_MPC_BLK_LUT_ATTR_NS22_Msk 0x400000UL 502 #define SMIF_MPC_BLK_LUT_ATTR_NS23_Pos 23UL 503 #define SMIF_MPC_BLK_LUT_ATTR_NS23_Msk 0x800000UL 504 #define SMIF_MPC_BLK_LUT_ATTR_NS24_Pos 24UL 505 #define SMIF_MPC_BLK_LUT_ATTR_NS24_Msk 0x1000000UL 506 #define SMIF_MPC_BLK_LUT_ATTR_NS25_Pos 25UL 507 #define SMIF_MPC_BLK_LUT_ATTR_NS25_Msk 0x2000000UL 508 #define SMIF_MPC_BLK_LUT_ATTR_NS26_Pos 26UL 509 #define SMIF_MPC_BLK_LUT_ATTR_NS26_Msk 0x4000000UL 510 #define SMIF_MPC_BLK_LUT_ATTR_NS27_Pos 27UL 511 #define SMIF_MPC_BLK_LUT_ATTR_NS27_Msk 0x8000000UL 512 #define SMIF_MPC_BLK_LUT_ATTR_NS28_Pos 28UL 513 #define SMIF_MPC_BLK_LUT_ATTR_NS28_Msk 0x10000000UL 514 #define SMIF_MPC_BLK_LUT_ATTR_NS29_Pos 29UL 515 #define SMIF_MPC_BLK_LUT_ATTR_NS29_Msk 0x20000000UL 516 #define SMIF_MPC_BLK_LUT_ATTR_NS30_Pos 30UL 517 #define SMIF_MPC_BLK_LUT_ATTR_NS30_Msk 0x40000000UL 518 #define SMIF_MPC_BLK_LUT_ATTR_NS31_Pos 31UL 519 #define SMIF_MPC_BLK_LUT_ATTR_NS31_Msk 0x80000000UL 520 /* SMIF_MPC.ROT_CTRL */ 521 #define SMIF_MPC_ROT_CTRL_AUTO_INC_Pos 8UL 522 #define SMIF_MPC_ROT_CTRL_AUTO_INC_Msk 0x100UL 523 #define SMIF_MPC_ROT_CTRL_LOCK_Pos 31UL 524 #define SMIF_MPC_ROT_CTRL_LOCK_Msk 0x80000000UL 525 /* SMIF_MPC.ROT_CFG */ 526 #define SMIF_MPC_ROT_CFG_BLOCK_SIZE_Pos 0UL 527 #define SMIF_MPC_ROT_CFG_BLOCK_SIZE_Msk 0xFUL 528 /* SMIF_MPC.ROT_BLK_MAX */ 529 #define SMIF_MPC_ROT_BLK_MAX_VALUE_Pos 0UL 530 #define SMIF_MPC_ROT_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 531 /* SMIF_MPC.ROT_BLK_CFG */ 532 #define SMIF_MPC_ROT_BLK_CFG_BLOCK_SIZE_Pos 0UL 533 #define SMIF_MPC_ROT_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 534 #define SMIF_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 535 #define SMIF_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 536 /* SMIF_MPC.ROT_BLK_IDX */ 537 #define SMIF_MPC_ROT_BLK_IDX_VALUE_Pos 0UL 538 #define SMIF_MPC_ROT_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 539 /* SMIF_MPC.ROT_BLK_PC */ 540 #define SMIF_MPC_ROT_BLK_PC_PC_Pos 0UL 541 #define SMIF_MPC_ROT_BLK_PC_PC_Msk 0xFUL 542 /* SMIF_MPC.ROT_BLK_LUT */ 543 #define SMIF_MPC_ROT_BLK_LUT_ATTR0_Pos 0UL 544 #define SMIF_MPC_ROT_BLK_LUT_ATTR0_Msk 0x7UL 545 #define SMIF_MPC_ROT_BLK_LUT_ATTR1_Pos 4UL 546 #define SMIF_MPC_ROT_BLK_LUT_ATTR1_Msk 0x70UL 547 #define SMIF_MPC_ROT_BLK_LUT_ATTR2_Pos 8UL 548 #define SMIF_MPC_ROT_BLK_LUT_ATTR2_Msk 0x700UL 549 #define SMIF_MPC_ROT_BLK_LUT_ATTR3_Pos 12UL 550 #define SMIF_MPC_ROT_BLK_LUT_ATTR3_Msk 0x7000UL 551 #define SMIF_MPC_ROT_BLK_LUT_ATTR4_Pos 16UL 552 #define SMIF_MPC_ROT_BLK_LUT_ATTR4_Msk 0x70000UL 553 #define SMIF_MPC_ROT_BLK_LUT_ATTR5_Pos 20UL 554 #define SMIF_MPC_ROT_BLK_LUT_ATTR5_Msk 0x700000UL 555 #define SMIF_MPC_ROT_BLK_LUT_ATTR6_Pos 24UL 556 #define SMIF_MPC_ROT_BLK_LUT_ATTR6_Msk 0x7000000UL 557 #define SMIF_MPC_ROT_BLK_LUT_ATTR7_Pos 28UL 558 #define SMIF_MPC_ROT_BLK_LUT_ATTR7_Msk 0x70000000UL 559 560 561 /* SMIF.CTL */ 562 #define SMIF_CTL_XIP_MODE_Pos 0UL 563 #define SMIF_CTL_XIP_MODE_Msk 0x1UL 564 #define SMIF_CTL_CLOCK_IF_TX_SEL_Pos 4UL 565 #define SMIF_CTL_CLOCK_IF_TX_SEL_Msk 0x10UL 566 #define SMIF_CTL_DELAY_LINE_SEL_Pos 5UL 567 #define SMIF_CTL_DELAY_LINE_SEL_Msk 0xE0UL 568 #define SMIF_CTL_DELAY_TAP_ENABLED_Pos 8UL 569 #define SMIF_CTL_DELAY_TAP_ENABLED_Msk 0x100UL 570 #define SMIF_CTL_INT_CLOCK_DL_ENABLED_Pos 9UL 571 #define SMIF_CTL_INT_CLOCK_DL_ENABLED_Msk 0x200UL 572 #define SMIF_CTL_INT_CLOCK_CAPTURE_CYCLE_Pos 10UL 573 #define SMIF_CTL_INT_CLOCK_CAPTURE_CYCLE_Msk 0xC00UL 574 #define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL 575 #define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x7000UL 576 #define SMIF_CTL_DESELECT_DELAY_Pos 16UL 577 #define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL 578 #define SMIF_CTL_SELECT_SETUP_DELAY_Pos 20UL 579 #define SMIF_CTL_SELECT_SETUP_DELAY_Msk 0x300000UL 580 #define SMIF_CTL_SELECT_HOLD_DELAY_Pos 22UL 581 #define SMIF_CTL_SELECT_HOLD_DELAY_Msk 0xC00000UL 582 #define SMIF_CTL_BLOCK_Pos 24UL 583 #define SMIF_CTL_BLOCK_Msk 0x1000000UL 584 #define SMIF_CTL_CLOCK_IF_SEL_Pos 25UL 585 #define SMIF_CTL_CLOCK_IF_SEL_Msk 0x2000000UL 586 #define SMIF_CTL_ENABLED_Pos 31UL 587 #define SMIF_CTL_ENABLED_Msk 0x80000000UL 588 /* SMIF.STATUS */ 589 #define SMIF_STATUS_BUSY_Pos 31UL 590 #define SMIF_STATUS_BUSY_Msk 0x80000000UL 591 /* SMIF.INT_CLOCK_DELAY_TAP_SEL0 */ 592 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT0_Pos 0UL 593 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT0_Msk 0xFFUL 594 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT1_Pos 8UL 595 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT1_Msk 0xFF00UL 596 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT2_Pos 16UL 597 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT2_Msk 0xFF0000UL 598 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT3_Pos 24UL 599 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0_DATA_BIT3_Msk 0xFF000000UL 600 /* SMIF.INT_CLOCK_DELAY_TAP_SEL1 */ 601 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT4_Pos 0UL 602 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT4_Msk 0xFFUL 603 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT5_Pos 8UL 604 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT5_Msk 0xFF00UL 605 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT6_Pos 16UL 606 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT6_Msk 0xFF0000UL 607 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT7_Pos 24UL 608 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1_DATA_BIT7_Msk 0xFF000000UL 609 /* SMIF.DL_CTL */ 610 #define SMIF_DL_CTL_DLP_Pos 0UL 611 #define SMIF_DL_CTL_DLP_Msk 0xFFFFUL 612 #define SMIF_DL_CTL_DLP_SIZE_Pos 16UL 613 #define SMIF_DL_CTL_DLP_SIZE_Msk 0xF0000UL 614 #define SMIF_DL_CTL_DL_WARNING_LEVEL_Pos 24UL 615 #define SMIF_DL_CTL_DL_WARNING_LEVEL_Msk 0xF000000UL 616 /* SMIF.DL_STATUS0 */ 617 #define SMIF_DL_STATUS0_DATA_BIT0_Pos 0UL 618 #define SMIF_DL_STATUS0_DATA_BIT0_Msk 0xFFUL 619 #define SMIF_DL_STATUS0_DATA_BIT1_Pos 8UL 620 #define SMIF_DL_STATUS0_DATA_BIT1_Msk 0xFF00UL 621 #define SMIF_DL_STATUS0_DATA_BIT2_Pos 16UL 622 #define SMIF_DL_STATUS0_DATA_BIT2_Msk 0xFF0000UL 623 #define SMIF_DL_STATUS0_DATA_BIT3_Pos 24UL 624 #define SMIF_DL_STATUS0_DATA_BIT3_Msk 0xFF000000UL 625 /* SMIF.DL_STATUS1 */ 626 #define SMIF_DL_STATUS1_DATA_BIT4_Pos 0UL 627 #define SMIF_DL_STATUS1_DATA_BIT4_Msk 0xFFUL 628 #define SMIF_DL_STATUS1_DATA_BIT5_Pos 8UL 629 #define SMIF_DL_STATUS1_DATA_BIT5_Msk 0xFF00UL 630 #define SMIF_DL_STATUS1_DATA_BIT6_Pos 16UL 631 #define SMIF_DL_STATUS1_DATA_BIT6_Msk 0xFF0000UL 632 #define SMIF_DL_STATUS1_DATA_BIT7_Pos 24UL 633 #define SMIF_DL_STATUS1_DATA_BIT7_Msk 0xFF000000UL 634 /* SMIF.TX_CMD_FIFO_STATUS */ 635 #define SMIF_TX_CMD_FIFO_STATUS_USED4_Pos 0UL 636 #define SMIF_TX_CMD_FIFO_STATUS_USED4_Msk 0xFUL 637 /* SMIF.TX_CMD_MMIO_FIFO_STATUS */ 638 #define SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4_Pos 0UL 639 #define SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 640 /* SMIF.TX_CMD_MMIO_FIFO_WR */ 641 #define SMIF_TX_CMD_MMIO_FIFO_WR_DATA27_Pos 0UL 642 #define SMIF_TX_CMD_MMIO_FIFO_WR_DATA27_Msk 0x7FFFFFFUL 643 /* SMIF.TX_DATA_MMIO_FIFO_CTL */ 644 #define SMIF_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Pos 0UL 645 #define SMIF_TX_DATA_MMIO_FIFO_CTL_TX_TRIGGER_LEVEL_Msk 0x7UL 646 /* SMIF.TX_DATA_FIFO_STATUS */ 647 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL 648 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 649 /* SMIF.TX_DATA_MMIO_FIFO_STATUS */ 650 #define SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL 651 #define SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 652 /* SMIF.TX_DATA_MMIO_FIFO_WR1 */ 653 #define SMIF_TX_DATA_MMIO_FIFO_WR1_DATA0_Pos 0UL 654 #define SMIF_TX_DATA_MMIO_FIFO_WR1_DATA0_Msk 0xFFUL 655 /* SMIF.TX_DATA_MMIO_FIFO_WR2 */ 656 #define SMIF_TX_DATA_MMIO_FIFO_WR2_DATA0_Pos 0UL 657 #define SMIF_TX_DATA_MMIO_FIFO_WR2_DATA0_Msk 0xFFUL 658 #define SMIF_TX_DATA_MMIO_FIFO_WR2_DATA1_Pos 8UL 659 #define SMIF_TX_DATA_MMIO_FIFO_WR2_DATA1_Msk 0xFF00UL 660 /* SMIF.TX_DATA_MMIO_FIFO_WR4 */ 661 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA0_Pos 0UL 662 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA0_Msk 0xFFUL 663 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA1_Pos 8UL 664 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA1_Msk 0xFF00UL 665 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA2_Pos 16UL 666 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA2_Msk 0xFF0000UL 667 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA3_Pos 24UL 668 #define SMIF_TX_DATA_MMIO_FIFO_WR4_DATA3_Msk 0xFF000000UL 669 /* SMIF.TX_DATA_MMIO_FIFO_WR1ODD */ 670 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Pos 0UL 671 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD_DATA0_Msk 0xFFUL 672 /* SMIF.RX_DATA_MMIO_FIFO_CTL */ 673 #define SMIF_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Pos 0UL 674 #define SMIF_RX_DATA_MMIO_FIFO_CTL_RX_TRIGGER_LEVEL_Msk 0x7UL 675 /* SMIF.RX_DATA_MMIO_FIFO_STATUS */ 676 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos 0UL 677 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk 0xFUL 678 /* SMIF.RX_DATA_FIFO_STATUS */ 679 #define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos 0UL 680 #define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 681 #define SMIF_RX_DATA_FIFO_STATUS_RX_SR_USED_Pos 8UL 682 #define SMIF_RX_DATA_FIFO_STATUS_RX_SR_USED_Msk 0x100UL 683 /* SMIF.RX_DATA_MMIO_FIFO_RD1 */ 684 #define SMIF_RX_DATA_MMIO_FIFO_RD1_DATA0_Pos 0UL 685 #define SMIF_RX_DATA_MMIO_FIFO_RD1_DATA0_Msk 0xFFUL 686 /* SMIF.RX_DATA_MMIO_FIFO_RD2 */ 687 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA0_Pos 0UL 688 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA0_Msk 0xFFUL 689 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA1_Pos 8UL 690 #define SMIF_RX_DATA_MMIO_FIFO_RD2_DATA1_Msk 0xFF00UL 691 /* SMIF.RX_DATA_MMIO_FIFO_RD4 */ 692 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA0_Pos 0UL 693 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA0_Msk 0xFFUL 694 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA1_Pos 8UL 695 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA1_Msk 0xFF00UL 696 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA2_Pos 16UL 697 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA2_Msk 0xFF0000UL 698 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA3_Pos 24UL 699 #define SMIF_RX_DATA_MMIO_FIFO_RD4_DATA3_Msk 0xFF000000UL 700 /* SMIF.RX_DATA_MMIO_FIFO_RD1_SILENT */ 701 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Pos 0UL 702 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL 703 /* SMIF.SLOW_CA_CTL */ 704 #define SMIF_SLOW_CA_CTL_WAY_Pos 16UL 705 #define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL 706 #define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL 707 #define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL 708 #define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL 709 #define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL 710 #define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL 711 #define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL 712 /* SMIF.SLOW_CA_CMD */ 713 #define SMIF_SLOW_CA_CMD_INV_Pos 0UL 714 #define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL 715 /* SMIF.FAST_CA_CTL */ 716 #define SMIF_FAST_CA_CTL_WAY_Pos 16UL 717 #define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL 718 #define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL 719 #define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL 720 #define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL 721 #define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL 722 #define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL 723 #define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL 724 /* SMIF.FAST_CA_CMD */ 725 #define SMIF_FAST_CA_CMD_INV_Pos 0UL 726 #define SMIF_FAST_CA_CMD_INV_Msk 0x1UL 727 /* SMIF.CRC_CMD */ 728 #define SMIF_CRC_CMD_START_Pos 0UL 729 #define SMIF_CRC_CMD_START_Msk 0x1UL 730 #define SMIF_CRC_CMD_CONTINUE_Pos 1UL 731 #define SMIF_CRC_CMD_CONTINUE_Msk 0x2UL 732 /* SMIF.CRC_INPUT0 */ 733 #define SMIF_CRC_INPUT0_INPUT_Pos 0UL 734 #define SMIF_CRC_INPUT0_INPUT_Msk 0xFFFFFFFFUL 735 /* SMIF.CRC_INPUT1 */ 736 #define SMIF_CRC_INPUT1_INPUT_Pos 0UL 737 #define SMIF_CRC_INPUT1_INPUT_Msk 0xFFFFFFFFUL 738 /* SMIF.CRC_OUTPUT */ 739 #define SMIF_CRC_OUTPUT_CRC_OUTPUT_Pos 0UL 740 #define SMIF_CRC_OUTPUT_CRC_OUTPUT_Msk 0xFFUL 741 /* SMIF.INTR */ 742 #define SMIF_INTR_TR_TX_REQ_Pos 0UL 743 #define SMIF_INTR_TR_TX_REQ_Msk 0x1UL 744 #define SMIF_INTR_TR_RX_REQ_Pos 1UL 745 #define SMIF_INTR_TR_RX_REQ_Msk 0x2UL 746 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL 747 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL 748 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL 749 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 750 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL 751 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 752 #define SMIF_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 753 #define SMIF_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 754 #define SMIF_INTR_DL_FAIL_Pos 8UL 755 #define SMIF_INTR_DL_FAIL_Msk 0x100UL 756 #define SMIF_INTR_DL_WARNING_Pos 12UL 757 #define SMIF_INTR_DL_WARNING_Msk 0x1000UL 758 #define SMIF_INTR_CRC_ERROR_Pos 16UL 759 #define SMIF_INTR_CRC_ERROR_Msk 0x10000UL 760 #define SMIF_INTR_FS_STATUS_ERROR_Pos 17UL 761 #define SMIF_INTR_FS_STATUS_ERROR_Msk 0x20000UL 762 /* SMIF.INTR_SET */ 763 #define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL 764 #define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL 765 #define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL 766 #define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL 767 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL 768 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL 769 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL 770 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 771 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL 772 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 773 #define SMIF_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 774 #define SMIF_INTR_SET_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 775 #define SMIF_INTR_SET_DL_FAIL_Pos 8UL 776 #define SMIF_INTR_SET_DL_FAIL_Msk 0x100UL 777 #define SMIF_INTR_SET_DL_WARNING_Pos 12UL 778 #define SMIF_INTR_SET_DL_WARNING_Msk 0x1000UL 779 #define SMIF_INTR_SET_CRC_ERROR_Pos 16UL 780 #define SMIF_INTR_SET_CRC_ERROR_Msk 0x10000UL 781 #define SMIF_INTR_SET_FS_STATUS_ERROR_Pos 17UL 782 #define SMIF_INTR_SET_FS_STATUS_ERROR_Msk 0x20000UL 783 /* SMIF.INTR_MASK */ 784 #define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL 785 #define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL 786 #define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL 787 #define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL 788 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL 789 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL 790 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL 791 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 792 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL 793 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 794 #define SMIF_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 795 #define SMIF_INTR_MASK_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 796 #define SMIF_INTR_MASK_DL_FAIL_Pos 8UL 797 #define SMIF_INTR_MASK_DL_FAIL_Msk 0x100UL 798 #define SMIF_INTR_MASK_DL_WARNING_Pos 12UL 799 #define SMIF_INTR_MASK_DL_WARNING_Msk 0x1000UL 800 #define SMIF_INTR_MASK_CRC_ERROR_Pos 16UL 801 #define SMIF_INTR_MASK_CRC_ERROR_Msk 0x10000UL 802 #define SMIF_INTR_MASK_FS_STATUS_ERROR_Pos 17UL 803 #define SMIF_INTR_MASK_FS_STATUS_ERROR_Msk 0x20000UL 804 /* SMIF.INTR_MASKED */ 805 #define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL 806 #define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL 807 #define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL 808 #define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL 809 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL 810 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL 811 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL 812 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 813 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL 814 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 815 #define SMIF_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Pos 5UL 816 #define SMIF_INTR_MASKED_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk 0x20UL 817 #define SMIF_INTR_MASKED_DL_FAIL_Pos 8UL 818 #define SMIF_INTR_MASKED_DL_FAIL_Msk 0x100UL 819 #define SMIF_INTR_MASKED_DL_WARNING_Pos 12UL 820 #define SMIF_INTR_MASKED_DL_WARNING_Msk 0x1000UL 821 #define SMIF_INTR_MASKED_CRC_ERROR_Pos 16UL 822 #define SMIF_INTR_MASKED_CRC_ERROR_Msk 0x10000UL 823 #define SMIF_INTR_MASKED_FS_STATUS_ERROR_Pos 17UL 824 #define SMIF_INTR_MASKED_FS_STATUS_ERROR_Msk 0x20000UL 825 /* SMIF.INTR_CAUSE */ 826 #define SMIF_INTR_CAUSE_NORMAL_Pos 0UL 827 #define SMIF_INTR_CAUSE_NORMAL_Msk 0x1UL 828 #define SMIF_INTR_CAUSE_MPC_Pos 1UL 829 #define SMIF_INTR_CAUSE_MPC_Msk 0x2UL 830 831 832 #endif /* _CYIP_SMIF_V3_H_ */ 833 834 835 /* [] END OF FILE */ 836
