1 /***************************************************************************//** 2 * \file cyip_smif.h 3 * 4 * \brief 5 * SMIF IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SMIF_H_ 28 #define _CYIP_SMIF_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SMIF 34 *******************************************************************************/ 35 36 #define SMIF_DEVICE_SECTION_SIZE 0x00000080UL 37 #define SMIF_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Device (only used in XIP mode) (SMIF_DEVICE) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t RESERVED; 45 __IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */ 46 __IOM uint32_t MASK; /*!< 0x0000000C Device region mask */ 47 __IM uint32_t RESERVED1[4]; 48 __IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */ 49 __IM uint32_t RESERVED2[7]; 50 __IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */ 51 __IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */ 52 __IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */ 53 __IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */ 54 __IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */ 55 __IM uint32_t RESERVED3[3]; 56 __IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */ 57 __IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */ 58 __IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */ 59 __IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */ 60 __IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */ 61 __IM uint32_t RESERVED4[3]; 62 } SMIF_DEVICE_V1_Type; /*!< Size = 128 (0x80) */ 63 64 /** 65 * \brief Serial Memory Interface (SMIF) 66 */ 67 typedef struct { 68 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 69 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 70 __IM uint32_t RESERVED[15]; 71 __IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */ 72 __IM uint32_t RESERVED1[2]; 73 __OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */ 74 __IM uint32_t RESERVED2[11]; 75 __IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */ 76 __IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */ 77 __IM uint32_t RESERVED3[2]; 78 __OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */ 79 __OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */ 80 __OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */ 81 __IM uint32_t RESERVED4[9]; 82 __IOM uint32_t RX_DATA_FIFO_CTL; /*!< 0x000000C0 Receiver data FIFO control */ 83 __IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C4 Receiver data FIFO status */ 84 __IM uint32_t RESERVED5[2]; 85 __IM uint32_t RX_DATA_FIFO_RD1; /*!< 0x000000D0 Receiver data FIFO read */ 86 __IM uint32_t RX_DATA_FIFO_RD2; /*!< 0x000000D4 Receiver data FIFO read */ 87 __IM uint32_t RX_DATA_FIFO_RD4; /*!< 0x000000D8 Receiver data FIFO read */ 88 __IM uint32_t RESERVED6; 89 __IM uint32_t RX_DATA_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data FIFO silent read */ 90 __IM uint32_t RESERVED7[7]; 91 __IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */ 92 __IM uint32_t RESERVED8; 93 __IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */ 94 __IM uint32_t RESERVED9[29]; 95 __IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */ 96 __IM uint32_t RESERVED10; 97 __IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */ 98 __IM uint32_t RESERVED11[29]; 99 __IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */ 100 __IM uint32_t RESERVED12[7]; 101 __IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */ 102 __IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */ 103 __IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */ 104 __IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */ 105 __IM uint32_t RESERVED13[4]; 106 __OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */ 107 __OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */ 108 __OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */ 109 __OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */ 110 __IM uint32_t RESERVED14[4]; 111 __IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */ 112 __IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */ 113 __IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */ 114 __IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */ 115 __IM uint32_t RESERVED15[340]; 116 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 117 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 118 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 119 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 120 __IM uint32_t RESERVED16[12]; 121 SMIF_DEVICE_V1_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */ 122 } SMIF_V1_Type; /*!< Size = 2560 (0xA00) */ 123 124 125 /* SMIF_DEVICE.CTL */ 126 #define SMIF_DEVICE_CTL_WR_EN_Pos 0UL 127 #define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL 128 #define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 8UL 129 #define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x100UL 130 #define SMIF_DEVICE_CTL_DATA_SEL_Pos 16UL 131 #define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x30000UL 132 #define SMIF_DEVICE_CTL_ENABLED_Pos 31UL 133 #define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL 134 /* SMIF_DEVICE.ADDR */ 135 #define SMIF_DEVICE_ADDR_ADDR_Pos 8UL 136 #define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL 137 /* SMIF_DEVICE.MASK */ 138 #define SMIF_DEVICE_MASK_MASK_Pos 8UL 139 #define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL 140 /* SMIF_DEVICE.ADDR_CTL */ 141 #define SMIF_DEVICE_ADDR_CTL_SIZE2_Pos 0UL 142 #define SMIF_DEVICE_ADDR_CTL_SIZE2_Msk 0x3UL 143 #define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL 144 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL 145 /* SMIF_DEVICE.RD_CMD_CTL */ 146 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL 147 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL 148 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL 149 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL 150 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos 31UL 151 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk 0x80000000UL 152 /* SMIF_DEVICE.RD_ADDR_CTL */ 153 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL 154 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL 155 /* SMIF_DEVICE.RD_MODE_CTL */ 156 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL 157 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL 158 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL 159 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL 160 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos 31UL 161 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Msk 0x80000000UL 162 /* SMIF_DEVICE.RD_DUMMY_CTL */ 163 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL 164 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL 165 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos 31UL 166 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk 0x80000000UL 167 /* SMIF_DEVICE.RD_DATA_CTL */ 168 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL 169 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL 170 /* SMIF_DEVICE.WR_CMD_CTL */ 171 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL 172 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL 173 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL 174 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL 175 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Pos 31UL 176 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk 0x80000000UL 177 /* SMIF_DEVICE.WR_ADDR_CTL */ 178 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL 179 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL 180 /* SMIF_DEVICE.WR_MODE_CTL */ 181 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL 182 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL 183 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL 184 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL 185 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Pos 31UL 186 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Msk 0x80000000UL 187 /* SMIF_DEVICE.WR_DUMMY_CTL */ 188 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL 189 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL 190 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Pos 31UL 191 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk 0x80000000UL 192 /* SMIF_DEVICE.WR_DATA_CTL */ 193 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL 194 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL 195 196 197 /* SMIF.CTL */ 198 #define SMIF_CTL_XIP_MODE_Pos 0UL 199 #define SMIF_CTL_XIP_MODE_Msk 0x1UL 200 #define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL 201 #define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x3000UL 202 #define SMIF_CTL_DESELECT_DELAY_Pos 16UL 203 #define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL 204 #define SMIF_CTL_BLOCK_Pos 24UL 205 #define SMIF_CTL_BLOCK_Msk 0x1000000UL 206 #define SMIF_CTL_ENABLED_Pos 31UL 207 #define SMIF_CTL_ENABLED_Msk 0x80000000UL 208 /* SMIF.STATUS */ 209 #define SMIF_STATUS_BUSY_Pos 31UL 210 #define SMIF_STATUS_BUSY_Msk 0x80000000UL 211 /* SMIF.TX_CMD_FIFO_STATUS */ 212 #define SMIF_TX_CMD_FIFO_STATUS_USED3_Pos 0UL 213 #define SMIF_TX_CMD_FIFO_STATUS_USED3_Msk 0x7UL 214 /* SMIF.TX_CMD_FIFO_WR */ 215 #define SMIF_TX_CMD_FIFO_WR_DATA20_Pos 0UL 216 #define SMIF_TX_CMD_FIFO_WR_DATA20_Msk 0xFFFFFUL 217 /* SMIF.TX_DATA_FIFO_CTL */ 218 #define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 219 #define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL 220 /* SMIF.TX_DATA_FIFO_STATUS */ 221 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL 222 #define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 223 /* SMIF.TX_DATA_FIFO_WR1 */ 224 #define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos 0UL 225 #define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk 0xFFUL 226 /* SMIF.TX_DATA_FIFO_WR2 */ 227 #define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos 0UL 228 #define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk 0xFFUL 229 #define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos 8UL 230 #define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk 0xFF00UL 231 /* SMIF.TX_DATA_FIFO_WR4 */ 232 #define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos 0UL 233 #define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk 0xFFUL 234 #define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos 8UL 235 #define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk 0xFF00UL 236 #define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos 16UL 237 #define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk 0xFF0000UL 238 #define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos 24UL 239 #define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk 0xFF000000UL 240 /* SMIF.RX_DATA_FIFO_CTL */ 241 #define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL 242 #define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL 243 /* SMIF.RX_DATA_FIFO_STATUS */ 244 #define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos 0UL 245 #define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL 246 /* SMIF.RX_DATA_FIFO_RD1 */ 247 #define SMIF_RX_DATA_FIFO_RD1_DATA0_Pos 0UL 248 #define SMIF_RX_DATA_FIFO_RD1_DATA0_Msk 0xFFUL 249 /* SMIF.RX_DATA_FIFO_RD2 */ 250 #define SMIF_RX_DATA_FIFO_RD2_DATA0_Pos 0UL 251 #define SMIF_RX_DATA_FIFO_RD2_DATA0_Msk 0xFFUL 252 #define SMIF_RX_DATA_FIFO_RD2_DATA1_Pos 8UL 253 #define SMIF_RX_DATA_FIFO_RD2_DATA1_Msk 0xFF00UL 254 /* SMIF.RX_DATA_FIFO_RD4 */ 255 #define SMIF_RX_DATA_FIFO_RD4_DATA0_Pos 0UL 256 #define SMIF_RX_DATA_FIFO_RD4_DATA0_Msk 0xFFUL 257 #define SMIF_RX_DATA_FIFO_RD4_DATA1_Pos 8UL 258 #define SMIF_RX_DATA_FIFO_RD4_DATA1_Msk 0xFF00UL 259 #define SMIF_RX_DATA_FIFO_RD4_DATA2_Pos 16UL 260 #define SMIF_RX_DATA_FIFO_RD4_DATA2_Msk 0xFF0000UL 261 #define SMIF_RX_DATA_FIFO_RD4_DATA3_Pos 24UL 262 #define SMIF_RX_DATA_FIFO_RD4_DATA3_Msk 0xFF000000UL 263 /* SMIF.RX_DATA_FIFO_RD1_SILENT */ 264 #define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Pos 0UL 265 #define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL 266 /* SMIF.SLOW_CA_CTL */ 267 #define SMIF_SLOW_CA_CTL_WAY_Pos 16UL 268 #define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL 269 #define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL 270 #define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL 271 #define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL 272 #define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL 273 #define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL 274 #define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL 275 /* SMIF.SLOW_CA_CMD */ 276 #define SMIF_SLOW_CA_CMD_INV_Pos 0UL 277 #define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL 278 /* SMIF.FAST_CA_CTL */ 279 #define SMIF_FAST_CA_CTL_WAY_Pos 16UL 280 #define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL 281 #define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL 282 #define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL 283 #define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL 284 #define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL 285 #define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL 286 #define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL 287 /* SMIF.FAST_CA_CMD */ 288 #define SMIF_FAST_CA_CMD_INV_Pos 0UL 289 #define SMIF_FAST_CA_CMD_INV_Msk 0x1UL 290 /* SMIF.CRYPTO_CMD */ 291 #define SMIF_CRYPTO_CMD_START_Pos 0UL 292 #define SMIF_CRYPTO_CMD_START_Msk 0x1UL 293 /* SMIF.CRYPTO_INPUT0 */ 294 #define SMIF_CRYPTO_INPUT0_INPUT_Pos 0UL 295 #define SMIF_CRYPTO_INPUT0_INPUT_Msk 0xFFFFFFFFUL 296 /* SMIF.CRYPTO_INPUT1 */ 297 #define SMIF_CRYPTO_INPUT1_INPUT_Pos 0UL 298 #define SMIF_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL 299 /* SMIF.CRYPTO_INPUT2 */ 300 #define SMIF_CRYPTO_INPUT2_INPUT_Pos 0UL 301 #define SMIF_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL 302 /* SMIF.CRYPTO_INPUT3 */ 303 #define SMIF_CRYPTO_INPUT3_INPUT_Pos 0UL 304 #define SMIF_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL 305 /* SMIF.CRYPTO_KEY0 */ 306 #define SMIF_CRYPTO_KEY0_KEY_Pos 0UL 307 #define SMIF_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL 308 /* SMIF.CRYPTO_KEY1 */ 309 #define SMIF_CRYPTO_KEY1_KEY_Pos 0UL 310 #define SMIF_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL 311 /* SMIF.CRYPTO_KEY2 */ 312 #define SMIF_CRYPTO_KEY2_KEY_Pos 0UL 313 #define SMIF_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL 314 /* SMIF.CRYPTO_KEY3 */ 315 #define SMIF_CRYPTO_KEY3_KEY_Pos 0UL 316 #define SMIF_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL 317 /* SMIF.CRYPTO_OUTPUT0 */ 318 #define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL 319 #define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL 320 /* SMIF.CRYPTO_OUTPUT1 */ 321 #define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL 322 #define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL 323 /* SMIF.CRYPTO_OUTPUT2 */ 324 #define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL 325 #define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL 326 /* SMIF.CRYPTO_OUTPUT3 */ 327 #define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL 328 #define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL 329 /* SMIF.INTR */ 330 #define SMIF_INTR_TR_TX_REQ_Pos 0UL 331 #define SMIF_INTR_TR_TX_REQ_Msk 0x1UL 332 #define SMIF_INTR_TR_RX_REQ_Pos 1UL 333 #define SMIF_INTR_TR_RX_REQ_Msk 0x2UL 334 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL 335 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL 336 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL 337 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 338 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL 339 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 340 #define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Pos 5UL 341 #define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL 342 /* SMIF.INTR_SET */ 343 #define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL 344 #define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL 345 #define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL 346 #define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL 347 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL 348 #define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL 349 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL 350 #define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 351 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL 352 #define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 353 #define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Pos 5UL 354 #define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL 355 /* SMIF.INTR_MASK */ 356 #define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL 357 #define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL 358 #define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL 359 #define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL 360 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL 361 #define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL 362 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL 363 #define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 364 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL 365 #define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 366 #define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Pos 5UL 367 #define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL 368 /* SMIF.INTR_MASKED */ 369 #define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL 370 #define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL 371 #define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL 372 #define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL 373 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL 374 #define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL 375 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL 376 #define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL 377 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL 378 #define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL 379 #define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Pos 5UL 380 #define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL 381 382 383 #endif /* _CYIP_SMIF_H_ */ 384 385 386 /* [] END OF FILE */ 387
