1 /***************************************************************************//** 2 * \file cyip_sflash.h 3 * 4 * \brief 5 * SFLASH IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SFLASH_H_ 28 #define _CYIP_SFLASH_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SFLASH 34 *******************************************************************************/ 35 36 #define SFLASH_SECTION_SIZE 0x00008000UL 37 38 /** 39 * \brief FLASH Supervisory Region (SFLASH) 40 */ 41 typedef struct { 42 __IM uint8_t RESERVED; 43 __IOM uint8_t SI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */ 44 __IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */ 45 __IM uint32_t RESERVED1[2]; 46 __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ 47 __IOM uint8_t SYSCALL_ERASE_PROT; /*!< 0x0000000E Controls the behavior for Erase All and Erase Sector system 48 calls */ 49 __IM uint8_t RESERVED2[5]; 50 __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ 51 __IM uint32_t RESERVED3[4]; 52 __IOM uint32_t SFLASH_SVN; /*!< 0x00000028 SFLASH Subversion */ 53 __IM uint32_t RESERVED4[20]; 54 __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ 55 __IM uint32_t RESERVED5[352]; 56 __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ 57 __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ 58 __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ 59 __IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */ 60 __IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */ 61 __IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */ 62 __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ 63 __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ 64 __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ 65 __IM uint8_t RESERVED6[61]; 66 __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ 67 __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ 68 __IM uint32_t RESERVED7[8]; 69 __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ 70 __IM uint32_t RESERVED8[52]; 71 __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ 72 __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ 73 __IM uint16_t RESERVED9[95]; 74 __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ 75 __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ 76 __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ 77 __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ 78 __IM uint32_t RESERVED10[302]; 79 __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ 80 __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ 81 __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ 82 __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */ 83 __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ 84 __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ 85 __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ 86 __IM uint32_t RESERVED11[122]; 87 __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ 88 __IM uint16_t RESERVED12; 89 __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ 90 __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ 91 __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ 92 __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ 93 __IM uint16_t RESERVED13; 94 __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ 95 __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ 96 __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ 97 __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ 98 __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ 99 __IM uint32_t RESERVED14[7]; 100 __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ 101 __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ 102 __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ 103 __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ 104 __IM uint32_t RESERVED15[491]; 105 __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ 106 __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ 107 __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ 108 __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ 109 __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ 110 __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ 111 __IM uint32_t RESERVED16[48]; 112 __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ 113 __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ 114 __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ 115 __IM uint32_t RESERVED17[768]; 116 __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 117 0x00 */ 118 __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ 119 __IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for 120 FACTORY_HASH */ 121 __IOM uint32_t TOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x0000780C Unused (Address is Hardcoded in ROM) */ 122 __IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */ 123 __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ 124 __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ 125 __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ 126 __IM uint32_t RESERVED18[119]; 127 __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ 128 __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting 129 from offset 0x00 */ 130 __IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */ 131 __IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be 132 verified for FACTORY_HASH */ 133 __IOM uint32_t RTOC1_GENERAL_TRIM_ADDR_UNUSED; /*!< 0x00007A0C Redundant Unused (Address is Hardcoded in ROM) */ 134 __IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */ 135 __IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH 136 patch also */ 137 __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ 138 __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ 139 __IM uint32_t RESERVED19[119]; 140 __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 141 bytes are 0 */ 142 __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset 143 0x00 */ 144 __IOM uint32_t TOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */ 145 __IOM uint32_t TOC2_KEY_BLOCK_ADDR; /*!< 0x00007C08 Address of Key Storage FLASH blocks */ 146 __IOM uint32_t TOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C0C Null terminated table of pointers representing the SMIF 147 configuration structure */ 148 __IOM uint32_t TOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C10 Address of First User Application Object */ 149 __IOM uint32_t TOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C14 Format of First User Application Object. 0 - Basic, 1 - Cypress 150 standard & 2 - Simplified */ 151 __IOM uint32_t TOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C18 Address of Second User Application Object */ 152 __IOM uint32_t TOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C1C Format of Second User Application Object. 0 - Basic, 1 - 153 Cypress standard & 2 - Simplified */ 154 __IOM uint32_t TOC2_SHASH_OBJECTS; /*!< 0x00007C20 Number of additional objects(in addition to objects covered by 155 FACORY_CAMC) starting from offset 0x24 to be verified for 156 SECURE_HASH(SHASH) */ 157 __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is 158 signature specific key. It is the public key in case of RSA */ 159 __IM uint32_t RESERVED20[115]; 160 __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ 161 __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ 162 __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ 163 __IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting 164 from offset 0x00 */ 165 __IOM uint32_t RTOC2_MAGIC_NUMBER; /*!< 0x00007E04 Redundant Magic number(0x01211220) */ 166 __IOM uint32_t RTOC2_KEY_BLOCK_ADDR; /*!< 0x00007E08 Redundant Address of Key Storage FLASH blocks */ 167 __IOM uint32_t RTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007E0C Redundant Null terminated table of pointers representing the 168 SMIF configuration structure */ 169 __IOM uint32_t RTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007E10 Redundant Address of First User Application Object */ 170 __IOM uint32_t RTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007E14 Redundant Format of First User Application Object. 0 - Basic, 1 171 - Cypress standard & 2 - Simplified */ 172 __IOM uint32_t RTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007E18 Redundant Address of Second User Application Object */ 173 __IOM uint32_t RTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007E1C Redundant Format of Second User Application Object. 0 - Basic, 174 1 - Cypress standard & 2 - Simplified */ 175 __IOM uint32_t RTOC2_SHASH_OBJECTS; /*!< 0x00007E20 Redundant Number of additional objects(in addition to objects 176 covered by FACORY_CAMC) starting from offset 0x24 to be verified 177 for SECURE_HASH(SHASH) */ 178 __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The 179 object is signature specific key. It is the public key in case 180 of RSA */ 181 __IM uint32_t RESERVED21[115]; 182 __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ 183 __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ 184 __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 185 bytes are 0 */ 186 } SFLASH_V1_Type; /*!< Size = 32768 (0x8000) */ 187 188 189 /* SFLASH.SI_REVISION_ID */ 190 #define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL 191 #define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL 192 /* SFLASH.SILICON_ID */ 193 #define SFLASH_SILICON_ID_ID_Pos 0UL 194 #define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL 195 /* SFLASH.FAMILY_ID */ 196 #define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL 197 #define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL 198 /* SFLASH.SYSCALL_ERASE_PROT */ 199 #define SFLASH_SYSCALL_ERASE_PROT_DATA_Pos 0UL 200 #define SFLASH_SYSCALL_ERASE_PROT_DATA_Msk 0xFFUL 201 /* SFLASH.CPUSS_WOUNDING */ 202 #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL 203 #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL 204 /* SFLASH.SFLASH_SVN */ 205 #define SFLASH_SFLASH_SVN_DATA32_Pos 0UL 206 #define SFLASH_SFLASH_SVN_DATA32_Msk 0xFFFFFFFFUL 207 /* SFLASH.FB_FLAGS */ 208 #define SFLASH_FB_FLAGS_FB_PIN_CTL_Pos 0UL 209 #define SFLASH_FB_FLAGS_FB_PIN_CTL_Msk 0x3UL 210 #define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Pos 2UL 211 #define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Msk 0xCUL 212 #define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Pos 4UL 213 #define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Msk 0x30UL 214 /* SFLASH.DIE_LOT */ 215 #define SFLASH_DIE_LOT_LOT_Pos 0UL 216 #define SFLASH_DIE_LOT_LOT_Msk 0xFFUL 217 /* SFLASH.DIE_WAFER */ 218 #define SFLASH_DIE_WAFER_WAFER_Pos 0UL 219 #define SFLASH_DIE_WAFER_WAFER_Msk 0xFFUL 220 /* SFLASH.DIE_X */ 221 #define SFLASH_DIE_X_X_Pos 0UL 222 #define SFLASH_DIE_X_X_Msk 0xFFUL 223 /* SFLASH.DIE_Y */ 224 #define SFLASH_DIE_Y_Y_Pos 0UL 225 #define SFLASH_DIE_Y_Y_Msk 0xFFUL 226 /* SFLASH.DIE_SORT */ 227 #define SFLASH_DIE_SORT_S1_PASS_Pos 0UL 228 #define SFLASH_DIE_SORT_S1_PASS_Msk 0x1UL 229 #define SFLASH_DIE_SORT_S2_PASS_Pos 1UL 230 #define SFLASH_DIE_SORT_S2_PASS_Msk 0x2UL 231 #define SFLASH_DIE_SORT_S3_PASS_Pos 2UL 232 #define SFLASH_DIE_SORT_S3_PASS_Msk 0x4UL 233 #define SFLASH_DIE_SORT_CRI_PASS_Pos 3UL 234 #define SFLASH_DIE_SORT_CRI_PASS_Msk 0x8UL 235 #define SFLASH_DIE_SORT_CHI_PASS_Pos 4UL 236 #define SFLASH_DIE_SORT_CHI_PASS_Msk 0x10UL 237 #define SFLASH_DIE_SORT_ENG_PASS_Pos 5UL 238 #define SFLASH_DIE_SORT_ENG_PASS_Msk 0x20UL 239 /* SFLASH.DIE_MINOR */ 240 #define SFLASH_DIE_MINOR_MINOR_Pos 0UL 241 #define SFLASH_DIE_MINOR_MINOR_Msk 0xFFUL 242 /* SFLASH.DIE_DAY */ 243 #define SFLASH_DIE_DAY_MINOR_Pos 0UL 244 #define SFLASH_DIE_DAY_MINOR_Msk 0xFFUL 245 /* SFLASH.DIE_MONTH */ 246 #define SFLASH_DIE_MONTH_MINOR_Pos 0UL 247 #define SFLASH_DIE_MONTH_MINOR_Msk 0xFFUL 248 /* SFLASH.DIE_YEAR */ 249 #define SFLASH_DIE_YEAR_MINOR_Pos 0UL 250 #define SFLASH_DIE_YEAR_MINOR_Msk 0xFFUL 251 /* SFLASH.SAR_TEMP_MULTIPLIER */ 252 #define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Pos 0UL 253 #define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Msk 0xFFFFUL 254 /* SFLASH.SAR_TEMP_OFFSET */ 255 #define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Pos 0UL 256 #define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Msk 0xFFFFUL 257 /* SFLASH.CSP_PANEL_ID */ 258 #define SFLASH_CSP_PANEL_ID_DATA32_Pos 0UL 259 #define SFLASH_CSP_PANEL_ID_DATA32_Msk 0xFFFFFFFFUL 260 /* SFLASH.LDO_0P9V_TRIM */ 261 #define SFLASH_LDO_0P9V_TRIM_DATA8_Pos 0UL 262 #define SFLASH_LDO_0P9V_TRIM_DATA8_Msk 0xFFUL 263 /* SFLASH.LDO_1P1V_TRIM */ 264 #define SFLASH_LDO_1P1V_TRIM_DATA8_Pos 0UL 265 #define SFLASH_LDO_1P1V_TRIM_DATA8_Msk 0xFFUL 266 /* SFLASH.BLE_DEVICE_ADDRESS */ 267 #define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos 0UL 268 #define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk 0xFFFFFFFFUL 269 /* SFLASH.USER_FREE_ROW1 */ 270 #define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL 271 #define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL 272 /* SFLASH.USER_FREE_ROW2 */ 273 #define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL 274 #define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL 275 /* SFLASH.USER_FREE_ROW3 */ 276 #define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL 277 #define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL 278 /* SFLASH.DEVICE_UID */ 279 #define SFLASH_DEVICE_UID_DATA8_Pos 0UL 280 #define SFLASH_DEVICE_UID_DATA8_Msk 0xFFUL 281 /* SFLASH.MASTER_KEY */ 282 #define SFLASH_MASTER_KEY_DATA8_Pos 0UL 283 #define SFLASH_MASTER_KEY_DATA8_Msk 0xFFUL 284 /* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR */ 285 #define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos 0UL 286 #define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk 0xFFFFFFFFUL 287 /* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR */ 288 #define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos 0UL 289 #define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk 0xFFFFFFFFUL 290 /* SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR */ 291 #define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos 0UL 292 #define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk 0xFFFFFFFFUL 293 /* SFLASH.STANDARD_MPU_STRUCT */ 294 #define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos 0UL 295 #define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL 296 /* SFLASH.STANDARD_PPU_STRUCT */ 297 #define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos 0UL 298 #define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL 299 /* SFLASH.PILO_FREQ_STEP */ 300 #define SFLASH_PILO_FREQ_STEP_STEP_Pos 0UL 301 #define SFLASH_PILO_FREQ_STEP_STEP_Msk 0xFFFFUL 302 /* SFLASH.CSDV2_CSD0_ADC_VREF0 */ 303 #define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Pos 0UL 304 #define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Msk 0xFFFFUL 305 #define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Pos 16UL 306 #define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Msk 0xFFFF0000UL 307 /* SFLASH.CSDV2_CSD0_ADC_VREF1 */ 308 #define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Pos 0UL 309 #define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Msk 0xFFFFUL 310 #define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Pos 16UL 311 #define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Msk 0xFFFF0000UL 312 /* SFLASH.CSDV2_CSD0_ADC_VREF2 */ 313 #define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Pos 0UL 314 #define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Msk 0xFFFFUL 315 /* SFLASH.PWR_TRIM_WAKE_CTL */ 316 #define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL 317 #define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL 318 /* SFLASH.RADIO_LDO_TRIMS */ 319 #define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos 0UL 320 #define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk 0xFUL 321 #define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos 4UL 322 #define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk 0x30UL 323 #define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos 6UL 324 #define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk 0xC0UL 325 #define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos 8UL 326 #define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk 0x300UL 327 /* SFLASH.CPUSS_TRIM_ROM_CTL_ULP */ 328 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Pos 0UL 329 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL 330 /* SFLASH.CPUSS_TRIM_RAM_CTL_ULP */ 331 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Pos 0UL 332 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL 333 /* SFLASH.CPUSS_TRIM_ROM_CTL_LP */ 334 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Pos 0UL 335 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL 336 /* SFLASH.CPUSS_TRIM_RAM_CTL_LP */ 337 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Pos 0UL 338 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL 339 /* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_ULP */ 340 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Pos 0UL 341 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL 342 /* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_ULP */ 343 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Pos 0UL 344 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL 345 /* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_LP */ 346 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Pos 0UL 347 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL 348 /* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_LP */ 349 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Pos 0UL 350 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL 351 /* SFLASH.FLASH_BOOT_OBJECT_SIZE */ 352 #define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL 353 #define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL 354 /* SFLASH.FLASH_BOOT_APP_ID */ 355 #define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL 356 #define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL 357 #define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL 358 #define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL 359 #define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL 360 #define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL 361 /* SFLASH.FLASH_BOOT_ATTRIBUTE */ 362 #define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos 0UL 363 #define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk 0xFFFFFFFFUL 364 /* SFLASH.FLASH_BOOT_N_CORES */ 365 #define SFLASH_FLASH_BOOT_N_CORES_DATA32_Pos 0UL 366 #define SFLASH_FLASH_BOOT_N_CORES_DATA32_Msk 0xFFFFFFFFUL 367 /* SFLASH.FLASH_BOOT_VT_OFFSET */ 368 #define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Pos 0UL 369 #define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Msk 0xFFFFFFFFUL 370 /* SFLASH.FLASH_BOOT_CORE_CPUID */ 371 #define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Pos 0UL 372 #define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Msk 0xFFFFFFFFUL 373 /* SFLASH.FLASH_BOOT_CODE */ 374 #define SFLASH_FLASH_BOOT_CODE_DATA_Pos 0UL 375 #define SFLASH_FLASH_BOOT_CODE_DATA_Msk 0xFFUL 376 /* SFLASH.PUBLIC_KEY */ 377 #define SFLASH_PUBLIC_KEY_DATA_Pos 0UL 378 #define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL 379 /* SFLASH.BOOT_PROT_SETTINGS */ 380 #define SFLASH_BOOT_PROT_SETTINGS_DATA32_Pos 0UL 381 #define SFLASH_BOOT_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL 382 /* SFLASH.TOC1_OBJECT_SIZE */ 383 #define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL 384 #define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL 385 /* SFLASH.TOC1_MAGIC_NUMBER */ 386 #define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL 387 #define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL 388 /* SFLASH.TOC1_FHASH_OBJECTS */ 389 #define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL 390 #define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL 391 /* SFLASH.TOC1_GENERAL_TRIM_ADDR_UNUSED */ 392 #define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL 393 #define SFLASH_TOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 394 /* SFLASH.TOC1_UNIQUE_ID_ADDR */ 395 #define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL 396 #define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL 397 /* SFLASH.TOC1_FB_OBJECT_ADDR */ 398 #define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL 399 #define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL 400 /* SFLASH.TOC1_SYSCALL_TABLE_ADDR_UNUSED */ 401 #define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL 402 #define SFLASH_TOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 403 /* SFLASH.TOC1_OBJECT_ADDR_UNUSED */ 404 #define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL 405 #define SFLASH_TOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 406 /* SFLASH.TOC1_CRC_ADDR */ 407 #define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL 408 #define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL 409 /* SFLASH.RTOC1_OBJECT_SIZE */ 410 #define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Pos 0UL 411 #define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL 412 /* SFLASH.RTOC1_MAGIC_NUMBER */ 413 #define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Pos 0UL 414 #define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL 415 /* SFLASH.RTOC1_FHASH_OBJECTS */ 416 #define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL 417 #define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL 418 /* SFLASH.RTOC1_GENERAL_TRIM_ADDR_UNUSED */ 419 #define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Pos 0UL 420 #define SFLASH_RTOC1_GENERAL_TRIM_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 421 /* SFLASH.RTOC1_UNIQUE_ID_ADDR */ 422 #define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL 423 #define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL 424 /* SFLASH.RTOC1_FB_OBJECT_ADDR */ 425 #define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL 426 #define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL 427 /* SFLASH.RTOC1_SYSCALL_TABLE_ADDR_UNUSED */ 428 #define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Pos 0UL 429 #define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 430 /* SFLASH.RTOC1_OBJECT_ADDR_UNUSED */ 431 #define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Pos 0UL 432 #define SFLASH_RTOC1_OBJECT_ADDR_UNUSED_DATA32_Msk 0xFFFFFFFFUL 433 /* SFLASH.RTOC1_CRC_ADDR */ 434 #define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL 435 #define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL 436 /* SFLASH.TOC2_OBJECT_SIZE */ 437 #define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL 438 #define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL 439 /* SFLASH.TOC2_MAGIC_NUMBER */ 440 #define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL 441 #define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL 442 /* SFLASH.TOC2_KEY_BLOCK_ADDR */ 443 #define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL 444 #define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL 445 /* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */ 446 #define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL 447 #define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL 448 /* SFLASH.TOC2_FIRST_USER_APP_ADDR */ 449 #define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL 450 #define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL 451 /* SFLASH.TOC2_FIRST_USER_APP_FORMAT */ 452 #define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL 453 #define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL 454 /* SFLASH.TOC2_SECOND_USER_APP_ADDR */ 455 #define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL 456 #define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL 457 /* SFLASH.TOC2_SECOND_USER_APP_FORMAT */ 458 #define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL 459 #define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL 460 /* SFLASH.TOC2_SHASH_OBJECTS */ 461 #define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL 462 #define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL 463 /* SFLASH.TOC2_SIGNATURE_VERIF_KEY */ 464 #define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL 465 #define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL 466 /* SFLASH.TOC2_REVISION */ 467 #define SFLASH_TOC2_REVISION_DATA32_Pos 0UL 468 #define SFLASH_TOC2_REVISION_DATA32_Msk 0xFFFFFFFFUL 469 /* SFLASH.TOC2_FLAGS */ 470 #define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Pos 0UL 471 #define SFLASH_TOC2_FLAGS_CLOCK_CONFIG_Msk 0x3UL 472 #define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Pos 2UL 473 #define SFLASH_TOC2_FLAGS_LISTEN_WINDOW_Msk 0x1CUL 474 #define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Pos 5UL 475 #define SFLASH_TOC2_FLAGS_SWJ_PINS_CTL_Msk 0x60UL 476 #define SFLASH_TOC2_FLAGS_APP_AUTH_CTL_Pos 7UL 477 #define SFLASH_TOC2_FLAGS_APP_AUTH_CTL_Msk 0x180UL 478 #define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_CTL_Pos 9UL 479 #define SFLASH_TOC2_FLAGS_FB_BOOTLOADER_CTL_Msk 0x600UL 480 /* SFLASH.TOC2_CRC_ADDR */ 481 #define SFLASH_TOC2_CRC_ADDR_DATA32_Pos 0UL 482 #define SFLASH_TOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL 483 /* SFLASH.RTOC2_OBJECT_SIZE */ 484 #define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Pos 0UL 485 #define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL 486 /* SFLASH.RTOC2_MAGIC_NUMBER */ 487 #define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Pos 0UL 488 #define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL 489 /* SFLASH.RTOC2_KEY_BLOCK_ADDR */ 490 #define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL 491 #define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL 492 /* SFLASH.RTOC2_SMIF_CFG_STRUCT_ADDR */ 493 #define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL 494 #define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL 495 /* SFLASH.RTOC2_FIRST_USER_APP_ADDR */ 496 #define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL 497 #define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL 498 /* SFLASH.RTOC2_FIRST_USER_APP_FORMAT */ 499 #define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL 500 #define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL 501 /* SFLASH.RTOC2_SECOND_USER_APP_ADDR */ 502 #define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL 503 #define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL 504 /* SFLASH.RTOC2_SECOND_USER_APP_FORMAT */ 505 #define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL 506 #define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL 507 /* SFLASH.RTOC2_SHASH_OBJECTS */ 508 #define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Pos 0UL 509 #define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL 510 /* SFLASH.RTOC2_SIGNATURE_VERIF_KEY */ 511 #define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL 512 #define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL 513 /* SFLASH.RTOC2_REVISION */ 514 #define SFLASH_RTOC2_REVISION_DATA32_Pos 0UL 515 #define SFLASH_RTOC2_REVISION_DATA32_Msk 0xFFFFFFFFUL 516 /* SFLASH.RTOC2_FLAGS */ 517 #define SFLASH_RTOC2_FLAGS_DATA32_Pos 0UL 518 #define SFLASH_RTOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL 519 /* SFLASH.RTOC2_CRC_ADDR */ 520 #define SFLASH_RTOC2_CRC_ADDR_DATA32_Pos 0UL 521 #define SFLASH_RTOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL 522 523 524 #endif /* _CYIP_SFLASH_H_ */ 525 526 527 /* [] END OF FILE */ 528
