1 /***************************************************************************//** 2 * \file cyip_sar_v2.h 3 * 4 * \brief 5 * SAR IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SAR_V2_H_ 28 #define _CYIP_SAR_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SAR 34 *******************************************************************************/ 35 36 #define SAR_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief SAR ADC with Sequencer (SAR) 40 */ 41 typedef struct { 42 __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */ 43 __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */ 44 __IM uint32_t RESERVED[2]; 45 __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */ 46 __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */ 47 __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */ 48 __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */ 49 __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */ 50 __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */ 51 __IM uint32_t RESERVED1[22]; 52 __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */ 53 __IM uint32_t RESERVED2[16]; 54 __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */ 55 __IM uint32_t RESERVED3[16]; 56 __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */ 57 __IM uint32_t RESERVED4[16]; 58 __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */ 59 __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */ 60 __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */ 61 __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */ 62 __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */ 63 __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */ 64 __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */ 65 __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */ 66 __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */ 67 __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */ 68 __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */ 69 __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */ 70 __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */ 71 __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */ 72 __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ 73 __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ 74 __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ 75 __IM uint32_t RESERVED5[15]; 76 __IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */ 77 __IM uint32_t RESERVED6[3]; 78 __IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */ 79 __IM uint32_t RESERVED7[3]; 80 __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ 81 __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ 82 __IM uint32_t RESERVED8[22]; 83 __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ 84 __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ 85 __IM uint32_t RESERVED9[15]; 86 __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ 87 __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ 88 } SAR_V2_Type; /*!< Size = 844 (0x34C) */ 89 90 91 /* SAR.CTRL */ 92 #define SAR_V2_CTRL_PWR_CTRL_VREF_Pos 0UL 93 #define SAR_V2_CTRL_PWR_CTRL_VREF_Msk 0x7UL 94 #define SAR_V2_CTRL_VREF_SEL_Pos 4UL 95 #define SAR_V2_CTRL_VREF_SEL_Msk 0x70UL 96 #define SAR_V2_CTRL_VREF_BYP_CAP_EN_Pos 7UL 97 #define SAR_V2_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL 98 #define SAR_V2_CTRL_NEG_SEL_Pos 9UL 99 #define SAR_V2_CTRL_NEG_SEL_Msk 0xE00UL 100 #define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL 101 #define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL 102 #define SAR_V2_CTRL_COMP_DLY_Pos 14UL 103 #define SAR_V2_CTRL_COMP_DLY_Msk 0xC000UL 104 #define SAR_V2_CTRL_SPARE_Pos 16UL 105 #define SAR_V2_CTRL_SPARE_Msk 0xF0000UL 106 #define SAR_V2_CTRL_BOOSTPUMP_EN_Pos 20UL 107 #define SAR_V2_CTRL_BOOSTPUMP_EN_Msk 0x100000UL 108 #define SAR_V2_CTRL_REFBUF_EN_Pos 21UL 109 #define SAR_V2_CTRL_REFBUF_EN_Msk 0x200000UL 110 #define SAR_V2_CTRL_COMP_PWR_Pos 24UL 111 #define SAR_V2_CTRL_COMP_PWR_Msk 0x7000000UL 112 #define SAR_V2_CTRL_DEEPSLEEP_ON_Pos 27UL 113 #define SAR_V2_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL 114 #define SAR_V2_CTRL_DSI_SYNC_CONFIG_Pos 28UL 115 #define SAR_V2_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL 116 #define SAR_V2_CTRL_DSI_MODE_Pos 29UL 117 #define SAR_V2_CTRL_DSI_MODE_Msk 0x20000000UL 118 #define SAR_V2_CTRL_SWITCH_DISABLE_Pos 30UL 119 #define SAR_V2_CTRL_SWITCH_DISABLE_Msk 0x40000000UL 120 #define SAR_V2_CTRL_ENABLED_Pos 31UL 121 #define SAR_V2_CTRL_ENABLED_Msk 0x80000000UL 122 /* SAR.SAMPLE_CTRL */ 123 #define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL 124 #define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL 125 #define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL 126 #define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL 127 #define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL 128 #define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL 129 #define SAR_V2_SAMPLE_CTRL_AVG_CNT_Pos 4UL 130 #define SAR_V2_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL 131 #define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL 132 #define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL 133 #define SAR_V2_SAMPLE_CTRL_AVG_MODE_Pos 8UL 134 #define SAR_V2_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL 135 #define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Pos 16UL 136 #define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL 137 #define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL 138 #define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL 139 #define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL 140 #define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL 141 #define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL 142 #define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL 143 #define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL 144 #define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL 145 #define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL 146 #define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL 147 #define SAR_V2_SAMPLE_CTRL_VALID_SEL_Pos 24UL 148 #define SAR_V2_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL 149 #define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL 150 #define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL 151 #define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL 152 #define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL 153 #define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL 154 #define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL 155 #define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL 156 #define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL 157 /* SAR.SAMPLE_TIME01 */ 158 #define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL 159 #define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL 160 #define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL 161 #define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL 162 /* SAR.SAMPLE_TIME23 */ 163 #define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL 164 #define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL 165 #define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL 166 #define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL 167 /* SAR.RANGE_THRES */ 168 #define SAR_V2_RANGE_THRES_RANGE_LOW_Pos 0UL 169 #define SAR_V2_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL 170 #define SAR_V2_RANGE_THRES_RANGE_HIGH_Pos 16UL 171 #define SAR_V2_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL 172 /* SAR.RANGE_COND */ 173 #define SAR_V2_RANGE_COND_RANGE_COND_Pos 30UL 174 #define SAR_V2_RANGE_COND_RANGE_COND_Msk 0xC0000000UL 175 /* SAR.CHAN_EN */ 176 #define SAR_V2_CHAN_EN_CHAN_EN_Pos 0UL 177 #define SAR_V2_CHAN_EN_CHAN_EN_Msk 0xFFFFUL 178 /* SAR.START_CTRL */ 179 #define SAR_V2_START_CTRL_FW_TRIGGER_Pos 0UL 180 #define SAR_V2_START_CTRL_FW_TRIGGER_Msk 0x1UL 181 /* SAR.CHAN_CONFIG */ 182 #define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL 183 #define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL 184 #define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL 185 #define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL 186 #define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL 187 #define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL 188 #define SAR_V2_CHAN_CONFIG_AVG_EN_Pos 10UL 189 #define SAR_V2_CHAN_CONFIG_AVG_EN_Msk 0x400UL 190 #define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL 191 #define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL 192 #define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL 193 #define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL 194 #define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL 195 #define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL 196 #define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL 197 #define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL 198 #define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL 199 #define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL 200 /* SAR.CHAN_WORK */ 201 #define SAR_V2_CHAN_WORK_WORK_Pos 0UL 202 #define SAR_V2_CHAN_WORK_WORK_Msk 0xFFFFUL 203 #define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL 204 #define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL 205 #define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL 206 #define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL 207 /* SAR.CHAN_RESULT */ 208 #define SAR_V2_CHAN_RESULT_RESULT_Pos 0UL 209 #define SAR_V2_CHAN_RESULT_RESULT_Msk 0xFFFFUL 210 #define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL 211 #define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL 212 #define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL 213 #define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL 214 #define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL 215 #define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL 216 #define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL 217 #define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL 218 /* SAR.CHAN_WORK_UPDATED */ 219 #define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL 220 #define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL 221 /* SAR.CHAN_RESULT_UPDATED */ 222 #define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL 223 #define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL 224 /* SAR.CHAN_WORK_NEWVALUE */ 225 #define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL 226 #define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL 227 /* SAR.CHAN_RESULT_NEWVALUE */ 228 #define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL 229 #define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL 230 /* SAR.INTR */ 231 #define SAR_V2_INTR_EOS_INTR_Pos 0UL 232 #define SAR_V2_INTR_EOS_INTR_Msk 0x1UL 233 #define SAR_V2_INTR_OVERFLOW_INTR_Pos 1UL 234 #define SAR_V2_INTR_OVERFLOW_INTR_Msk 0x2UL 235 #define SAR_V2_INTR_FW_COLLISION_INTR_Pos 2UL 236 #define SAR_V2_INTR_FW_COLLISION_INTR_Msk 0x4UL 237 #define SAR_V2_INTR_DSI_COLLISION_INTR_Pos 3UL 238 #define SAR_V2_INTR_DSI_COLLISION_INTR_Msk 0x8UL 239 #define SAR_V2_INTR_INJ_EOC_INTR_Pos 4UL 240 #define SAR_V2_INTR_INJ_EOC_INTR_Msk 0x10UL 241 #define SAR_V2_INTR_INJ_SATURATE_INTR_Pos 5UL 242 #define SAR_V2_INTR_INJ_SATURATE_INTR_Msk 0x20UL 243 #define SAR_V2_INTR_INJ_RANGE_INTR_Pos 6UL 244 #define SAR_V2_INTR_INJ_RANGE_INTR_Msk 0x40UL 245 #define SAR_V2_INTR_INJ_COLLISION_INTR_Pos 7UL 246 #define SAR_V2_INTR_INJ_COLLISION_INTR_Msk 0x80UL 247 /* SAR.INTR_SET */ 248 #define SAR_V2_INTR_SET_EOS_SET_Pos 0UL 249 #define SAR_V2_INTR_SET_EOS_SET_Msk 0x1UL 250 #define SAR_V2_INTR_SET_OVERFLOW_SET_Pos 1UL 251 #define SAR_V2_INTR_SET_OVERFLOW_SET_Msk 0x2UL 252 #define SAR_V2_INTR_SET_FW_COLLISION_SET_Pos 2UL 253 #define SAR_V2_INTR_SET_FW_COLLISION_SET_Msk 0x4UL 254 #define SAR_V2_INTR_SET_DSI_COLLISION_SET_Pos 3UL 255 #define SAR_V2_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL 256 #define SAR_V2_INTR_SET_INJ_EOC_SET_Pos 4UL 257 #define SAR_V2_INTR_SET_INJ_EOC_SET_Msk 0x10UL 258 #define SAR_V2_INTR_SET_INJ_SATURATE_SET_Pos 5UL 259 #define SAR_V2_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL 260 #define SAR_V2_INTR_SET_INJ_RANGE_SET_Pos 6UL 261 #define SAR_V2_INTR_SET_INJ_RANGE_SET_Msk 0x40UL 262 #define SAR_V2_INTR_SET_INJ_COLLISION_SET_Pos 7UL 263 #define SAR_V2_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL 264 /* SAR.INTR_MASK */ 265 #define SAR_V2_INTR_MASK_EOS_MASK_Pos 0UL 266 #define SAR_V2_INTR_MASK_EOS_MASK_Msk 0x1UL 267 #define SAR_V2_INTR_MASK_OVERFLOW_MASK_Pos 1UL 268 #define SAR_V2_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL 269 #define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Pos 2UL 270 #define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL 271 #define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL 272 #define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL 273 #define SAR_V2_INTR_MASK_INJ_EOC_MASK_Pos 4UL 274 #define SAR_V2_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL 275 #define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL 276 #define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL 277 #define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Pos 6UL 278 #define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL 279 #define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL 280 #define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL 281 /* SAR.INTR_MASKED */ 282 #define SAR_V2_INTR_MASKED_EOS_MASKED_Pos 0UL 283 #define SAR_V2_INTR_MASKED_EOS_MASKED_Msk 0x1UL 284 #define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL 285 #define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL 286 #define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL 287 #define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL 288 #define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL 289 #define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL 290 #define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL 291 #define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL 292 #define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL 293 #define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL 294 #define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL 295 #define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL 296 #define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL 297 #define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL 298 /* SAR.SATURATE_INTR */ 299 #define SAR_V2_SATURATE_INTR_SATURATE_INTR_Pos 0UL 300 #define SAR_V2_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL 301 /* SAR.SATURATE_INTR_SET */ 302 #define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL 303 #define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL 304 /* SAR.SATURATE_INTR_MASK */ 305 #define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL 306 #define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL 307 /* SAR.SATURATE_INTR_MASKED */ 308 #define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL 309 #define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL 310 /* SAR.RANGE_INTR */ 311 #define SAR_V2_RANGE_INTR_RANGE_INTR_Pos 0UL 312 #define SAR_V2_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL 313 /* SAR.RANGE_INTR_SET */ 314 #define SAR_V2_RANGE_INTR_SET_RANGE_SET_Pos 0UL 315 #define SAR_V2_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL 316 /* SAR.RANGE_INTR_MASK */ 317 #define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL 318 #define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL 319 /* SAR.RANGE_INTR_MASKED */ 320 #define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL 321 #define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL 322 /* SAR.INTR_CAUSE */ 323 #define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL 324 #define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL 325 #define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL 326 #define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL 327 #define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL 328 #define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL 329 #define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL 330 #define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL 331 #define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL 332 #define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL 333 #define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL 334 #define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL 335 #define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL 336 #define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL 337 #define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL 338 #define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL 339 #define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL 340 #define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL 341 #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL 342 #define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL 343 /* SAR.INJ_CHAN_CONFIG */ 344 #define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL 345 #define SAR_V2_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL 346 #define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL 347 #define SAR_V2_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL 348 #define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL 349 #define SAR_V2_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL 350 #define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL 351 #define SAR_V2_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL 352 #define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL 353 #define SAR_V2_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL 354 #define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL 355 #define SAR_V2_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL 356 #define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL 357 #define SAR_V2_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL 358 /* SAR.INJ_RESULT */ 359 #define SAR_V2_INJ_RESULT_INJ_RESULT_Pos 0UL 360 #define SAR_V2_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL 361 #define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Pos 27UL 362 #define SAR_V2_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL 363 #define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL 364 #define SAR_V2_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL 365 #define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL 366 #define SAR_V2_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL 367 #define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL 368 #define SAR_V2_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL 369 #define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL 370 #define SAR_V2_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL 371 /* SAR.STATUS */ 372 #define SAR_V2_STATUS_CUR_CHAN_Pos 0UL 373 #define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL 374 #define SAR_V2_STATUS_SW_VREF_NEG_Pos 30UL 375 #define SAR_V2_STATUS_SW_VREF_NEG_Msk 0x40000000UL 376 #define SAR_V2_STATUS_BUSY_Pos 31UL 377 #define SAR_V2_STATUS_BUSY_Msk 0x80000000UL 378 /* SAR.AVG_STAT */ 379 #define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Pos 0UL 380 #define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL 381 #define SAR_V2_AVG_STAT_INTRLV_BUSY_Pos 23UL 382 #define SAR_V2_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL 383 #define SAR_V2_AVG_STAT_CUR_AVG_CNT_Pos 24UL 384 #define SAR_V2_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL 385 /* SAR.MUX_SWITCH0 */ 386 #define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL 387 #define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL 388 #define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL 389 #define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL 390 #define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL 391 #define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL 392 #define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL 393 #define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL 394 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL 395 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL 396 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL 397 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL 398 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL 399 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL 400 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL 401 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL 402 #define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL 403 #define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL 404 #define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL 405 #define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL 406 #define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL 407 #define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL 408 #define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL 409 #define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL 410 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL 411 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL 412 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL 413 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL 414 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL 415 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL 416 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL 417 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL 418 #define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL 419 #define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL 420 #define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL 421 #define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL 422 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL 423 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL 424 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL 425 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL 426 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL 427 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL 428 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL 429 #define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL 430 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL 431 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL 432 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL 433 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL 434 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL 435 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL 436 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL 437 #define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL 438 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL 439 #define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL 440 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL 441 #define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL 442 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL 443 #define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL 444 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL 445 #define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL 446 /* SAR.MUX_SWITCH_CLEAR0 */ 447 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL 448 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL 449 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL 450 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL 451 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL 452 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL 453 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL 454 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL 455 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL 456 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL 457 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL 458 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL 459 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL 460 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL 461 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL 462 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL 463 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL 464 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL 465 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL 466 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL 467 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL 468 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL 469 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL 470 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL 471 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL 472 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL 473 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL 474 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL 475 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL 476 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL 477 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL 478 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL 479 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL 480 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL 481 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL 482 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL 483 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL 484 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL 485 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL 486 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL 487 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL 488 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL 489 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL 490 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL 491 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL 492 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL 493 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL 494 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL 495 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL 496 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL 497 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL 498 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL 499 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL 500 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL 501 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL 502 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL 503 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL 504 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL 505 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL 506 #define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL 507 /* SAR.MUX_SWITCH_SQ_CTRL */ 508 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL 509 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL 510 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL 511 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL 512 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL 513 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL 514 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL 515 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL 516 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL 517 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL 518 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL 519 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL 520 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL 521 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL 522 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL 523 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL 524 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL 525 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL 526 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL 527 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL 528 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL 529 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL 530 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL 531 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL 532 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL 533 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL 534 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL 535 #define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL 536 /* SAR.MUX_SWITCH_STATUS */ 537 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL 538 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL 539 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL 540 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL 541 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL 542 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL 543 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL 544 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL 545 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL 546 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL 547 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL 548 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL 549 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL 550 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL 551 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL 552 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL 553 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL 554 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL 555 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL 556 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL 557 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL 558 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL 559 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL 560 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL 561 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL 562 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL 563 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL 564 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL 565 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL 566 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL 567 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL 568 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL 569 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL 570 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL 571 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL 572 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL 573 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL 574 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL 575 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL 576 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL 577 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL 578 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL 579 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL 580 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL 581 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL 582 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL 583 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL 584 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL 585 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL 586 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL 587 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL 588 #define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL 589 590 591 #endif /* _CYIP_SAR_V2_H_ */ 592 593 594 /* [] END OF FILE */ 595
