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Searched refs:RAMC_PWR_DELAY_CTL_SEQ1_DELAY_Msk (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_ramc_v2.h255 #define RAMC_PWR_DELAY_CTL_SEQ1_DELAY_Msk 0xFF000000UL macro
Dcyip_ramc.h294 #define RAMC_PWR_DELAY_CTL_SEQ1_DELAY_Msk 0xFF000000UL macro