1 /***************************************************************************//** 2 * \file cyip_ramc.h 3 * 4 * \brief 5 * RAMC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_RAMC_H_ 28 #define _CYIP_RAMC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * RAMC 34 *******************************************************************************/ 35 36 #define RAMC_MPC_SECTION_SIZE 0x00001000UL 37 #define RAMC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief MPC Memory Protection Controller registers (RAMC_MPC) 41 */ 42 typedef struct { 43 __IOM uint32_t CFG; /*!< 0x00000000 Config register with error response, RegionID PPC_MPC_MAIN is 44 the security owner PC. The error response configuration is 45 located in CFG.RESPONSE, only one such configuration exists 46 applying to all protection contexts in the system. */ 47 __IM uint32_t RESERVED[3]; 48 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 49 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 50 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 51 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 52 __IM uint32_t INTR_INFO1; /*!< 0x00000020 Infor about violation */ 53 __IM uint32_t INTR_INFO2; /*!< 0x00000024 Infor about violation */ 54 __IM uint32_t RESERVED1[54]; 55 __IOM uint32_t CTRL; /*!< 0x00000100 Control register with lock bit and auto-increment only 56 (Separate CTRL for each PC depends on access_pc) */ 57 __IM uint32_t BLK_MAX; /*!< 0x00000104 Max value of block-based index register */ 58 __IM uint32_t BLK_CFG; /*!< 0x00000108 Block size & initialization in progress */ 59 __IOM uint32_t BLK_IDX; /*!< 0x0000010C Index of 32-block group accessed through BLK_LUT (Separate IDX 60 for each PC depending on access_pc) */ 61 __IOM uint32_t BLK_LUT; /*!< 0x00000110 NS status for 32 blocks at BLK_IDX with PC=<access_pc> */ 62 __IM uint32_t RESERVED2[59]; 63 __IOM uint32_t ROT_CTRL; /*!< 0x00000200 Control register with lock bit and auto-increment only */ 64 __IOM uint32_t ROT_CFG; /*!< 0x00000204 Sets block-size to match memory size (external memory only) */ 65 __IM uint32_t ROT_BLK_MAX; /*!< 0x00000208 Max value of block-based index register for ROT */ 66 __IM uint32_t ROT_BLK_CFG; /*!< 0x0000020C Same as BLK_CFG */ 67 __IOM uint32_t ROT_BLK_IDX; /*!< 0x00000210 Index of 8-block group accessed through ROT_BLK_LUT_* */ 68 __IOM uint32_t ROT_BLK_PC; /*!< 0x00000214 Protection context of 8-block group accesses through 69 ROT_BLK_LUT */ 70 __IOM uint32_t ROT_BLK_LUT; /*!< 0x00000218 (R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC */ 71 __IM uint32_t RESERVED3[889]; 72 } RAMC_MPC_Type; /*!< Size = 4096 (0x1000) */ 73 74 /** 75 * \brief RAMC0/1/2 (RAMC) 76 */ 77 typedef struct { 78 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 79 __IM uint32_t RESERVED; 80 __IM uint32_t STATUS; /*!< 0x00000008 Status */ 81 __IM uint32_t RESERVED1[5]; 82 __IOM uint32_t ECC_CTL; /*!< 0x00000020 ECC control */ 83 __IOM uint32_t ECC_MATCH; /*!< 0x00000024 ECC match */ 84 __IM uint32_t ECC_STATUS0; /*!< 0x00000028 ECC status 0 */ 85 __IM uint32_t ECC_STATUS1; /*!< 0x0000002C ECC status 1 */ 86 __IM uint32_t RESERVED2[116]; 87 __IOM uint32_t PWR_MACRO_CTL; /*!< 0x00000200 SRAM power partition power control */ 88 __IM uint32_t RESERVED3[15]; 89 __IOM uint32_t PWR_MACRO_CTL_LOCK; /*!< 0x00000240 SRAM power partition power control Lock */ 90 __IM uint32_t RESERVED4[15]; 91 __IOM uint32_t PWR_DELAY_CTL; /*!< 0x00000280 SRAM power switch power up & sequence delay */ 92 __IM uint32_t RESERVED5[3935]; 93 RAMC_MPC_Type MPC[1]; /*!< 0x00004000 MPC Memory Protection Controller registers */ 94 } RAMC_Type; /*!< Size = 20480 (0x5000) */ 95 96 97 /* RAMC_MPC.CFG */ 98 #define RAMC_MPC_CFG_RESPONSE_Pos 4UL 99 #define RAMC_MPC_CFG_RESPONSE_Msk 0x10UL 100 /* RAMC_MPC.INTR */ 101 #define RAMC_MPC_INTR_VIOLATION_Pos 0UL 102 #define RAMC_MPC_INTR_VIOLATION_Msk 0x1UL 103 /* RAMC_MPC.INTR_SET */ 104 #define RAMC_MPC_INTR_SET_VIOLATION_Pos 0UL 105 #define RAMC_MPC_INTR_SET_VIOLATION_Msk 0x1UL 106 /* RAMC_MPC.INTR_MASK */ 107 #define RAMC_MPC_INTR_MASK_VIOLATION_Pos 0UL 108 #define RAMC_MPC_INTR_MASK_VIOLATION_Msk 0x1UL 109 /* RAMC_MPC.INTR_MASKED */ 110 #define RAMC_MPC_INTR_MASKED_VIOLATION_Pos 0UL 111 #define RAMC_MPC_INTR_MASKED_VIOLATION_Msk 0x1UL 112 /* RAMC_MPC.INTR_INFO1 */ 113 #define RAMC_MPC_INTR_INFO1_VALUE_Pos 0UL 114 #define RAMC_MPC_INTR_INFO1_VALUE_Msk 0xFFFFFFFFUL 115 /* RAMC_MPC.INTR_INFO2 */ 116 #define RAMC_MPC_INTR_INFO2_HMASTER_Pos 0UL 117 #define RAMC_MPC_INTR_INFO2_HMASTER_Msk 0xFFFFUL 118 #define RAMC_MPC_INTR_INFO2_HNONSEC_Pos 16UL 119 #define RAMC_MPC_INTR_INFO2_HNONSEC_Msk 0x10000UL 120 #define RAMC_MPC_INTR_INFO2_CFG_NS_Pos 17UL 121 #define RAMC_MPC_INTR_INFO2_CFG_NS_Msk 0x20000UL 122 #define RAMC_MPC_INTR_INFO2_HWRITE_Pos 18UL 123 #define RAMC_MPC_INTR_INFO2_HWRITE_Msk 0x40000UL 124 #define RAMC_MPC_INTR_INFO2_HAUSER_Pos 24UL 125 #define RAMC_MPC_INTR_INFO2_HAUSER_Msk 0xF000000UL 126 #define RAMC_MPC_INTR_INFO2_SECURITY_VIOLATION_Pos 30UL 127 #define RAMC_MPC_INTR_INFO2_SECURITY_VIOLATION_Msk 0x40000000UL 128 #define RAMC_MPC_INTR_INFO2_ACCESS_VIOLATION_Pos 31UL 129 #define RAMC_MPC_INTR_INFO2_ACCESS_VIOLATION_Msk 0x80000000UL 130 /* RAMC_MPC.CTRL */ 131 #define RAMC_MPC_CTRL_AUTO_INC_Pos 8UL 132 #define RAMC_MPC_CTRL_AUTO_INC_Msk 0x100UL 133 #define RAMC_MPC_CTRL_LOCK_Pos 31UL 134 #define RAMC_MPC_CTRL_LOCK_Msk 0x80000000UL 135 /* RAMC_MPC.BLK_MAX */ 136 #define RAMC_MPC_BLK_MAX_VALUE_Pos 0UL 137 #define RAMC_MPC_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 138 /* RAMC_MPC.BLK_CFG */ 139 #define RAMC_MPC_BLK_CFG_BLOCK_SIZE_Pos 0UL 140 #define RAMC_MPC_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 141 #define RAMC_MPC_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 142 #define RAMC_MPC_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 143 /* RAMC_MPC.BLK_IDX */ 144 #define RAMC_MPC_BLK_IDX_VALUE_Pos 0UL 145 #define RAMC_MPC_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 146 /* RAMC_MPC.BLK_LUT */ 147 #define RAMC_MPC_BLK_LUT_ATTR_NS0_Pos 0UL 148 #define RAMC_MPC_BLK_LUT_ATTR_NS0_Msk 0x1UL 149 #define RAMC_MPC_BLK_LUT_ATTR_NS1_Pos 1UL 150 #define RAMC_MPC_BLK_LUT_ATTR_NS1_Msk 0x2UL 151 #define RAMC_MPC_BLK_LUT_ATTR_NS2_Pos 2UL 152 #define RAMC_MPC_BLK_LUT_ATTR_NS2_Msk 0x4UL 153 #define RAMC_MPC_BLK_LUT_ATTR_NS3_Pos 3UL 154 #define RAMC_MPC_BLK_LUT_ATTR_NS3_Msk 0x8UL 155 #define RAMC_MPC_BLK_LUT_ATTR_NS4_Pos 4UL 156 #define RAMC_MPC_BLK_LUT_ATTR_NS4_Msk 0x10UL 157 #define RAMC_MPC_BLK_LUT_ATTR_NS5_Pos 5UL 158 #define RAMC_MPC_BLK_LUT_ATTR_NS5_Msk 0x20UL 159 #define RAMC_MPC_BLK_LUT_ATTR_NS6_Pos 6UL 160 #define RAMC_MPC_BLK_LUT_ATTR_NS6_Msk 0x40UL 161 #define RAMC_MPC_BLK_LUT_ATTR_NS7_Pos 7UL 162 #define RAMC_MPC_BLK_LUT_ATTR_NS7_Msk 0x80UL 163 #define RAMC_MPC_BLK_LUT_ATTR_NS8_Pos 8UL 164 #define RAMC_MPC_BLK_LUT_ATTR_NS8_Msk 0x100UL 165 #define RAMC_MPC_BLK_LUT_ATTR_NS9_Pos 9UL 166 #define RAMC_MPC_BLK_LUT_ATTR_NS9_Msk 0x200UL 167 #define RAMC_MPC_BLK_LUT_ATTR_NS10_Pos 10UL 168 #define RAMC_MPC_BLK_LUT_ATTR_NS10_Msk 0x400UL 169 #define RAMC_MPC_BLK_LUT_ATTR_NS11_Pos 11UL 170 #define RAMC_MPC_BLK_LUT_ATTR_NS11_Msk 0x800UL 171 #define RAMC_MPC_BLK_LUT_ATTR_NS12_Pos 12UL 172 #define RAMC_MPC_BLK_LUT_ATTR_NS12_Msk 0x1000UL 173 #define RAMC_MPC_BLK_LUT_ATTR_NS13_Pos 13UL 174 #define RAMC_MPC_BLK_LUT_ATTR_NS13_Msk 0x2000UL 175 #define RAMC_MPC_BLK_LUT_ATTR_NS14_Pos 14UL 176 #define RAMC_MPC_BLK_LUT_ATTR_NS14_Msk 0x4000UL 177 #define RAMC_MPC_BLK_LUT_ATTR_NS15_Pos 15UL 178 #define RAMC_MPC_BLK_LUT_ATTR_NS15_Msk 0x8000UL 179 #define RAMC_MPC_BLK_LUT_ATTR_NS16_Pos 16UL 180 #define RAMC_MPC_BLK_LUT_ATTR_NS16_Msk 0x10000UL 181 #define RAMC_MPC_BLK_LUT_ATTR_NS17_Pos 17UL 182 #define RAMC_MPC_BLK_LUT_ATTR_NS17_Msk 0x20000UL 183 #define RAMC_MPC_BLK_LUT_ATTR_NS18_Pos 18UL 184 #define RAMC_MPC_BLK_LUT_ATTR_NS18_Msk 0x40000UL 185 #define RAMC_MPC_BLK_LUT_ATTR_NS19_Pos 19UL 186 #define RAMC_MPC_BLK_LUT_ATTR_NS19_Msk 0x80000UL 187 #define RAMC_MPC_BLK_LUT_ATTR_NS20_Pos 20UL 188 #define RAMC_MPC_BLK_LUT_ATTR_NS20_Msk 0x100000UL 189 #define RAMC_MPC_BLK_LUT_ATTR_NS21_Pos 21UL 190 #define RAMC_MPC_BLK_LUT_ATTR_NS21_Msk 0x200000UL 191 #define RAMC_MPC_BLK_LUT_ATTR_NS22_Pos 22UL 192 #define RAMC_MPC_BLK_LUT_ATTR_NS22_Msk 0x400000UL 193 #define RAMC_MPC_BLK_LUT_ATTR_NS23_Pos 23UL 194 #define RAMC_MPC_BLK_LUT_ATTR_NS23_Msk 0x800000UL 195 #define RAMC_MPC_BLK_LUT_ATTR_NS24_Pos 24UL 196 #define RAMC_MPC_BLK_LUT_ATTR_NS24_Msk 0x1000000UL 197 #define RAMC_MPC_BLK_LUT_ATTR_NS25_Pos 25UL 198 #define RAMC_MPC_BLK_LUT_ATTR_NS25_Msk 0x2000000UL 199 #define RAMC_MPC_BLK_LUT_ATTR_NS26_Pos 26UL 200 #define RAMC_MPC_BLK_LUT_ATTR_NS26_Msk 0x4000000UL 201 #define RAMC_MPC_BLK_LUT_ATTR_NS27_Pos 27UL 202 #define RAMC_MPC_BLK_LUT_ATTR_NS27_Msk 0x8000000UL 203 #define RAMC_MPC_BLK_LUT_ATTR_NS28_Pos 28UL 204 #define RAMC_MPC_BLK_LUT_ATTR_NS28_Msk 0x10000000UL 205 #define RAMC_MPC_BLK_LUT_ATTR_NS29_Pos 29UL 206 #define RAMC_MPC_BLK_LUT_ATTR_NS29_Msk 0x20000000UL 207 #define RAMC_MPC_BLK_LUT_ATTR_NS30_Pos 30UL 208 #define RAMC_MPC_BLK_LUT_ATTR_NS30_Msk 0x40000000UL 209 #define RAMC_MPC_BLK_LUT_ATTR_NS31_Pos 31UL 210 #define RAMC_MPC_BLK_LUT_ATTR_NS31_Msk 0x80000000UL 211 /* RAMC_MPC.ROT_CTRL */ 212 #define RAMC_MPC_ROT_CTRL_AUTO_INC_Pos 8UL 213 #define RAMC_MPC_ROT_CTRL_AUTO_INC_Msk 0x100UL 214 #define RAMC_MPC_ROT_CTRL_LOCK_Pos 31UL 215 #define RAMC_MPC_ROT_CTRL_LOCK_Msk 0x80000000UL 216 /* RAMC_MPC.ROT_CFG */ 217 #define RAMC_MPC_ROT_CFG_BLOCK_SIZE_Pos 0UL 218 #define RAMC_MPC_ROT_CFG_BLOCK_SIZE_Msk 0xFUL 219 /* RAMC_MPC.ROT_BLK_MAX */ 220 #define RAMC_MPC_ROT_BLK_MAX_VALUE_Pos 0UL 221 #define RAMC_MPC_ROT_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 222 /* RAMC_MPC.ROT_BLK_CFG */ 223 #define RAMC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Pos 0UL 224 #define RAMC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 225 #define RAMC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 226 #define RAMC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 227 /* RAMC_MPC.ROT_BLK_IDX */ 228 #define RAMC_MPC_ROT_BLK_IDX_VALUE_Pos 0UL 229 #define RAMC_MPC_ROT_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 230 /* RAMC_MPC.ROT_BLK_PC */ 231 #define RAMC_MPC_ROT_BLK_PC_PC_Pos 0UL 232 #define RAMC_MPC_ROT_BLK_PC_PC_Msk 0xFUL 233 /* RAMC_MPC.ROT_BLK_LUT */ 234 #define RAMC_MPC_ROT_BLK_LUT_ATTR0_Pos 0UL 235 #define RAMC_MPC_ROT_BLK_LUT_ATTR0_Msk 0x7UL 236 #define RAMC_MPC_ROT_BLK_LUT_ATTR1_Pos 4UL 237 #define RAMC_MPC_ROT_BLK_LUT_ATTR1_Msk 0x70UL 238 #define RAMC_MPC_ROT_BLK_LUT_ATTR2_Pos 8UL 239 #define RAMC_MPC_ROT_BLK_LUT_ATTR2_Msk 0x700UL 240 #define RAMC_MPC_ROT_BLK_LUT_ATTR3_Pos 12UL 241 #define RAMC_MPC_ROT_BLK_LUT_ATTR3_Msk 0x7000UL 242 #define RAMC_MPC_ROT_BLK_LUT_ATTR4_Pos 16UL 243 #define RAMC_MPC_ROT_BLK_LUT_ATTR4_Msk 0x70000UL 244 #define RAMC_MPC_ROT_BLK_LUT_ATTR5_Pos 20UL 245 #define RAMC_MPC_ROT_BLK_LUT_ATTR5_Msk 0x700000UL 246 #define RAMC_MPC_ROT_BLK_LUT_ATTR6_Pos 24UL 247 #define RAMC_MPC_ROT_BLK_LUT_ATTR6_Msk 0x7000000UL 248 #define RAMC_MPC_ROT_BLK_LUT_ATTR7_Pos 28UL 249 #define RAMC_MPC_ROT_BLK_LUT_ATTR7_Msk 0x70000000UL 250 251 252 /* RAMC.CTL */ 253 #define RAMC_CTL_SRAM_WS_Pos 0UL 254 #define RAMC_CTL_SRAM_WS_Msk 0x3UL 255 #define RAMC_CTL_CLOCK_FORCE_Pos 16UL 256 #define RAMC_CTL_CLOCK_FORCE_Msk 0x10000UL 257 /* RAMC.STATUS */ 258 #define RAMC_STATUS_WB_EMPTY_Pos 0UL 259 #define RAMC_STATUS_WB_EMPTY_Msk 0x1UL 260 #define RAMC_STATUS_PWR_DONE_Pos 4UL 261 #define RAMC_STATUS_PWR_DONE_Msk 0x10UL 262 /* RAMC.ECC_CTL */ 263 #define RAMC_ECC_CTL_EN_Pos 0UL 264 #define RAMC_ECC_CTL_EN_Msk 0x1UL 265 #define RAMC_ECC_CTL_AUTO_CORRECT_Pos 1UL 266 #define RAMC_ECC_CTL_AUTO_CORRECT_Msk 0x2UL 267 #define RAMC_ECC_CTL_INJ_EN_Pos 2UL 268 #define RAMC_ECC_CTL_INJ_EN_Msk 0x4UL 269 #define RAMC_ECC_CTL_CHECK_EN_Pos 3UL 270 #define RAMC_ECC_CTL_CHECK_EN_Msk 0x8UL 271 #define RAMC_ECC_CTL_PARITY_Pos 16UL 272 #define RAMC_ECC_CTL_PARITY_Msk 0x7F0000UL 273 /* RAMC.ECC_MATCH */ 274 #define RAMC_ECC_MATCH_WORD_ADDR_Pos 0UL 275 #define RAMC_ECC_MATCH_WORD_ADDR_Msk 0x1FFFFFFUL 276 /* RAMC.ECC_STATUS0 */ 277 #define RAMC_ECC_STATUS0_ADDR_Pos 0UL 278 #define RAMC_ECC_STATUS0_ADDR_Msk 0xFFFFFFFFUL 279 /* RAMC.ECC_STATUS1 */ 280 #define RAMC_ECC_STATUS1_SYNDROME_Pos 0UL 281 #define RAMC_ECC_STATUS1_SYNDROME_Msk 0x7FUL 282 /* RAMC.PWR_MACRO_CTL */ 283 #define RAMC_PWR_MACRO_CTL_OFF_Pos 0UL 284 #define RAMC_PWR_MACRO_CTL_OFF_Msk 0xFFFFFFFFUL 285 /* RAMC.PWR_MACRO_CTL_LOCK */ 286 #define RAMC_PWR_MACRO_CTL_LOCK_PWR_MACRO_CTL_LOCK_Pos 0UL 287 #define RAMC_PWR_MACRO_CTL_LOCK_PWR_MACRO_CTL_LOCK_Msk 0x3UL 288 /* RAMC.PWR_DELAY_CTL */ 289 #define RAMC_PWR_DELAY_CTL_UP_Pos 0UL 290 #define RAMC_PWR_DELAY_CTL_UP_Msk 0x3FFUL 291 #define RAMC_PWR_DELAY_CTL_SEQ0_DELAY_Pos 16UL 292 #define RAMC_PWR_DELAY_CTL_SEQ0_DELAY_Msk 0xFF0000UL 293 #define RAMC_PWR_DELAY_CTL_SEQ1_DELAY_Pos 24UL 294 #define RAMC_PWR_DELAY_CTL_SEQ1_DELAY_Msk 0xFF000000UL 295 296 297 #endif /* _CYIP_RAMC_H_ */ 298 299 300 /* [] END OF FILE */ 301
