1 /***************************************************************************//** 2 * \file cyip_pass.h 3 * 4 * \brief 5 * PASS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PASS_H_ 28 #define _CYIP_PASS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PASS 34 *******************************************************************************/ 35 36 #define PASS_AREF_SECTION_SIZE 0x00000100UL 37 #define PASS_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief AREF configuration (PASS_AREF) 41 */ 42 typedef struct { 43 __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ 44 __IM uint32_t RESERVED[63]; 45 } PASS_AREF_V1_Type; /*!< Size = 256 (0x100) */ 46 47 /** 48 * \brief PASS top-level MMIO (DSABv2, INTR) (PASS) 49 */ 50 typedef struct { 51 __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ 52 __IM uint32_t RESERVED[895]; 53 PASS_AREF_V1_Type AREF; /*!< 0x00000E00 AREF configuration */ 54 __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ 55 __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ 56 __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ 57 __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ 58 __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 IZTAT Trim bits */ 59 __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ 60 __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ 61 __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ 62 } PASS_V1_Type; /*!< Size = 3872 (0xF20) */ 63 64 65 /* PASS_AREF.AREF_CTRL */ 66 #define PASS_AREF_AREF_CTRL_AREF_MODE_Pos 0UL 67 #define PASS_AREF_AREF_CTRL_AREF_MODE_Msk 0x1UL 68 #define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL 69 #define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL 70 #define PASS_AREF_AREF_CTRL_AREF_RMB_Pos 4UL 71 #define PASS_AREF_AREF_CTRL_AREF_RMB_Msk 0x70UL 72 #define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL 73 #define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL 74 #define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL 75 #define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL 76 #define PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos 16UL 77 #define PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL 78 #define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL 79 #define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL 80 #define PASS_AREF_AREF_CTRL_VREF_SEL_Pos 20UL 81 #define PASS_AREF_AREF_CTRL_VREF_SEL_Msk 0x300000UL 82 #define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL 83 #define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL 84 #define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL 85 #define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL 86 #define PASS_AREF_AREF_CTRL_ENABLED_Pos 31UL 87 #define PASS_AREF_AREF_CTRL_ENABLED_Msk 0x80000000UL 88 89 90 /* PASS.INTR_CAUSE */ 91 #define PASS_INTR_CAUSE_CTB0_INT_Pos 0UL 92 #define PASS_INTR_CAUSE_CTB0_INT_Msk 0x1UL 93 #define PASS_INTR_CAUSE_CTB1_INT_Pos 1UL 94 #define PASS_INTR_CAUSE_CTB1_INT_Msk 0x2UL 95 #define PASS_INTR_CAUSE_CTB2_INT_Pos 2UL 96 #define PASS_INTR_CAUSE_CTB2_INT_Msk 0x4UL 97 #define PASS_INTR_CAUSE_CTB3_INT_Pos 3UL 98 #define PASS_INTR_CAUSE_CTB3_INT_Msk 0x8UL 99 #define PASS_INTR_CAUSE_CTDAC0_INT_Pos 4UL 100 #define PASS_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL 101 #define PASS_INTR_CAUSE_CTDAC1_INT_Pos 5UL 102 #define PASS_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL 103 #define PASS_INTR_CAUSE_CTDAC2_INT_Pos 6UL 104 #define PASS_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL 105 #define PASS_INTR_CAUSE_CTDAC3_INT_Pos 7UL 106 #define PASS_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL 107 /* PASS.VREF_TRIM0 */ 108 #define PASS_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL 109 #define PASS_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL 110 /* PASS.VREF_TRIM1 */ 111 #define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL 112 #define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL 113 /* PASS.VREF_TRIM2 */ 114 #define PASS_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL 115 #define PASS_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL 116 /* PASS.VREF_TRIM3 */ 117 #define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL 118 #define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL 119 /* PASS.IZTAT_TRIM0 */ 120 #define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL 121 #define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL 122 /* PASS.IZTAT_TRIM1 */ 123 #define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL 124 #define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL 125 /* PASS.IPTAT_TRIM0 */ 126 #define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL 127 #define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL 128 #define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL 129 #define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL 130 /* PASS.ICTAT_TRIM0 */ 131 #define PASS_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL 132 #define PASS_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL 133 134 135 #endif /* _CYIP_PASS_H_ */ 136 137 138 /* [] END OF FILE */ 139
