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Searched refs:P0_3 (Results 1 – 25 of 56) sorted by relevance

123

/hal_infineon-3.5.0/mtb-hal-cat1/COMPONENT_CAT1B/source/pin_packages/
Dcyhal_cyw20829_56_qfn.c123 {0u, 12u, P0_3, P0_3_KEYSCAN_KS_COL12},
197 {0u, 5u, P0_3, P0_3_PERI_TR_IO_INPUT5},
226 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
242 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
280 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
293 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
331 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
400 {0u, 0u, P0_3, P0_3_TCPWM0_LINE0},
401 {1u, 1u, P0_3, P0_3_TCPWM0_LINE257},
473 {0u, 0u, P0_3, P0_3_TDM_TDM_RX_SD0},
Dcyhal_cyw20829a0_56_qfn.c121 {0u, 12u, P0_3, P0_3_KEYSCAN_KS_COL12},
193 {0u, 5u, P0_3, P0_3_PERI_TR_IO_INPUT5},
221 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
236 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
274 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
287 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
325 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3},
394 {0u, 0u, P0_3, P0_3_TCPWM0_LINE0},
395 {1u, 1u, P0_3, P0_3_TCPWM0_LINE257},
467 {0u, 0u, P0_3, P0_3_TDM_TDM_RX_SD0},
/hal_infineon-3.5.0/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/
Dcyhal_psoc6_04_64_tqfp.c218 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
242 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
313 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
405 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
516 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
517 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
574 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_04_68_qfn.c216 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
240 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
309 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
399 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
509 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
510 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
566 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_04_80_m_csp.c218 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
242 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
315 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
409 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
520 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
521 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
578 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_04_80_tqfp.c218 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
242 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
315 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
409 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
520 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
521 {1u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL257},
578 {0u, 3u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN3},
Dcyhal_psoc6_03_68_qfn.c184 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
210 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
284 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
381 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
530 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
531 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_68_qfn_ble.c337 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
364 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
439 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
534 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
657 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
658 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_03_100_tqfp.c195 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
224 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
306 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
413 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
575 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
576 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_68_qfn.c224 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
254 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
338 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
451 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
642 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
643 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_80_wlcsp.c351 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
383 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
478 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
599 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
745 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
746 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_104_m_csp_ble.c361 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
395 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
499 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
632 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
787 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
788 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_104_m_csp_ble_usb.c361 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
395 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
498 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
629 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
784 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
785 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_116_bga_ble.c363 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
398 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
508 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
647 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
812 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
813 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_124_bga_sip.c365 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
401 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
516 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
661 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
830 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
831 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_116_bga_usb.c363 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
398 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
505 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
640 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
803 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
804 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_100_wlcsp.c253 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
293 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
405 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
558 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
793 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
794 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_01_124_bga.c374 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
415 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
545 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
710 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
898 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
899 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_124_bga.c264 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
309 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
439 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
616 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
874 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
875 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
Dcyhal_psoc6_02_128_tqfp.c264 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
310 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
442 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO},
622 {0u, 0u, P0_3, P0_3_SCB0_UART_TX},
882 {0u, 1u, P0_3, P0_3_TCPWM0_LINE_COMPL1},
883 {1u, 1u, P0_3, P0_3_TCPWM1_LINE_COMPL1},
/hal_infineon-3.5.0/mtb-hal-cat1/COMPONENT_CAT1C/source/pin_packages/
Dcyhal_xmc7100_100_teqfp.c86 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1},
403 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
451 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
468 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
548 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
565 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
612 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS},
772 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13},
856 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14},
945 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39},
[all …]
Dcyhal_xmc7200_176_teqfp.c92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1},
595 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
667 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
690 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
813 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
836 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
909 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS},
1098 {4u, 13u, P0_3, P0_3_TCPWM1_LINE13},
1283 {4u, 14u, P0_3, P0_3_TCPWM1_LINE_COMPL14},
1472 {4u, 39u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN39},
[all …]
Dcyhal_xmc7100_144_teqfp.c92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1},
482 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
547 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
569 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
675 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
697 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
759 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS},
938 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13},
1069 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14},
1204 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39},
[all …]
Dcyhal_xmc7100_176_teqfp.c92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1},
539 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA},
611 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
634 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
757 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI},
780 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0},
853 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS},
1041 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13},
1208 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14},
1379 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39},
[all …]
/hal_infineon-3.5.0/XMCLib/drivers/inc/
Dxmc1_gpio_map.h72 #define P0_3 XMC_GPIO_PORT0, 3 macro
165 #define P0_3 XMC_GPIO_PORT0, 3 macro
294 #define P0_3 XMC_GPIO_PORT0, 3 macro
357 #define P0_3 XMC_GPIO_PORT0, 3 macro
481 #define P0_3 XMC_GPIO_PORT0, 3 macro
695 #define P0_3 XMC_GPIO_PORT0, 3 macro
897 #define P0_3 XMC_GPIO_PORT0, 3 macro
1052 #define P0_3 XMC_GPIO_PORT0, 3 macro
1247 #define P0_3 XMC_GPIO_PORT0, 3 macro
1356 #define P0_3 XMC_GPIO_PORT0, 3 macro
[all …]

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