1 /***************************************************************************//** 2 * \file cyip_mxcm33.h 3 * 4 * \brief 5 * MXCM33 IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MXCM33_H_ 28 #define _CYIP_MXCM33_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MXCM33 34 *******************************************************************************/ 35 36 #define MXCM33_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief MXCM33-0/1 (MXCM33) 40 */ 41 typedef struct { 42 __IOM uint32_t CM33_CTL; /*!< 0x00000000 Control */ 43 __IOM uint32_t CM33_CMD; /*!< 0x00000004 Command */ 44 __IM uint32_t CM33_STATUS; /*!< 0x00000008 Status */ 45 __IM uint32_t RESERVED[13]; 46 __IM uint32_t CM33_INT_STATUS[16]; /*!< 0x00000040 CM33 interrupt status */ 47 __IOM uint32_t CM33_NMI_CTL[4]; /*!< 0x00000080 CM33 NMI control */ 48 __IM uint32_t RESERVED1[988]; 49 __IOM uint32_t CM33_S_VECTOR_TABLE_BASE; /*!< 0x00001000 CM33 secure vector table base */ 50 __IOM uint32_t CM33_NS_VECTOR_TABLE_BASE; /*!< 0x00001004 CM33 non-secure vector table base */ 51 __IM uint32_t RESERVED2[1022]; 52 __IOM uint32_t CM33_PC_CTL; /*!< 0x00002000 CM33 protection context control */ 53 __IM uint32_t RESERVED3[15]; 54 __IOM uint32_t CM33_PC0_HANDLER; /*!< 0x00002040 CM33 protection context 0 handler */ 55 __IOM uint32_t CM33_PC1_HANDLER; /*!< 0x00002044 CM33 protection context 1 handler */ 56 __IOM uint32_t CM33_PC2_HANDLER; /*!< 0x00002048 CM33 protection context 2 handler */ 57 __IOM uint32_t CM33_PC3_HANDLER; /*!< 0x0000204C CM33 protection context 3 handler */ 58 __IM uint32_t RESERVED4[6124]; 59 __IOM uint32_t CM33_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM33 system interrupt control */ 60 } MXCM33_Type; /*!< Size = 36860 (0x8FFC) */ 61 62 63 /* MXCM33.CM33_CTL */ 64 #define MXCM33_CM33_CTL_CPU_WAIT_Pos 4UL 65 #define MXCM33_CM33_CTL_CPU_WAIT_Msk 0x10UL 66 #define MXCM33_CM33_CTL_LOCKNSVTOR_Pos 8UL 67 #define MXCM33_CM33_CTL_LOCKNSVTOR_Msk 0x100UL 68 #define MXCM33_CM33_CTL_LOCKSVTAIRCR_Pos 9UL 69 #define MXCM33_CM33_CTL_LOCKSVTAIRCR_Msk 0x200UL 70 #define MXCM33_CM33_CTL_LOCKSMPU_Pos 10UL 71 #define MXCM33_CM33_CTL_LOCKSMPU_Msk 0x400UL 72 #define MXCM33_CM33_CTL_LOCKNSMPU_Pos 11UL 73 #define MXCM33_CM33_CTL_LOCKNSMPU_Msk 0x800UL 74 #define MXCM33_CM33_CTL_LOCKSAU_Pos 12UL 75 #define MXCM33_CM33_CTL_LOCKSAU_Msk 0x1000UL 76 #define MXCM33_CM33_CTL_IOC_MASK_Pos 24UL 77 #define MXCM33_CM33_CTL_IOC_MASK_Msk 0x1000000UL 78 #define MXCM33_CM33_CTL_DZC_MASK_Pos 25UL 79 #define MXCM33_CM33_CTL_DZC_MASK_Msk 0x2000000UL 80 #define MXCM33_CM33_CTL_OFC_MASK_Pos 26UL 81 #define MXCM33_CM33_CTL_OFC_MASK_Msk 0x4000000UL 82 #define MXCM33_CM33_CTL_UFC_MASK_Pos 27UL 83 #define MXCM33_CM33_CTL_UFC_MASK_Msk 0x8000000UL 84 #define MXCM33_CM33_CTL_IXC_MASK_Pos 28UL 85 #define MXCM33_CM33_CTL_IXC_MASK_Msk 0x10000000UL 86 #define MXCM33_CM33_CTL_IDC_MASK_Pos 31UL 87 #define MXCM33_CM33_CTL_IDC_MASK_Msk 0x80000000UL 88 /* MXCM33.CM33_CMD */ 89 #define MXCM33_CM33_CMD_ENABLED_Pos 1UL 90 #define MXCM33_CM33_CMD_ENABLED_Msk 0x2UL 91 #define MXCM33_CM33_CMD_VECTKEYSTAT_Pos 16UL 92 #define MXCM33_CM33_CMD_VECTKEYSTAT_Msk 0xFFFF0000UL 93 /* MXCM33.CM33_STATUS */ 94 #define MXCM33_CM33_STATUS_SLEEPING_Pos 0UL 95 #define MXCM33_CM33_STATUS_SLEEPING_Msk 0x1UL 96 #define MXCM33_CM33_STATUS_SLEEPDEEP_Pos 1UL 97 #define MXCM33_CM33_STATUS_SLEEPDEEP_Msk 0x2UL 98 /* MXCM33.CM33_INT_STATUS */ 99 #define MXCM33_CM33_INT_STATUS_SYSTEM_INT_IDX_Pos 0UL 100 #define MXCM33_CM33_INT_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 101 #define MXCM33_CM33_INT_STATUS_SYSTEM_INT_VALID_Pos 31UL 102 #define MXCM33_CM33_INT_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 103 /* MXCM33.CM33_NMI_CTL */ 104 #define MXCM33_CM33_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 105 #define MXCM33_CM33_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 106 /* MXCM33.CM33_S_VECTOR_TABLE_BASE */ 107 #define MXCM33_CM33_S_VECTOR_TABLE_BASE_ADDR25_Pos 7UL 108 #define MXCM33_CM33_S_VECTOR_TABLE_BASE_ADDR25_Msk 0xFFFFFF80UL 109 /* MXCM33.CM33_NS_VECTOR_TABLE_BASE */ 110 #define MXCM33_CM33_NS_VECTOR_TABLE_BASE_ADDR25_Pos 7UL 111 #define MXCM33_CM33_NS_VECTOR_TABLE_BASE_ADDR25_Msk 0xFFFFFF80UL 112 /* MXCM33.CM33_PC_CTL */ 113 #define MXCM33_CM33_PC_CTL_VALID_Pos 0UL 114 #define MXCM33_CM33_PC_CTL_VALID_Msk 0xFUL 115 /* MXCM33.CM33_PC0_HANDLER */ 116 #define MXCM33_CM33_PC0_HANDLER_ADDR_Pos 0UL 117 #define MXCM33_CM33_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL 118 /* MXCM33.CM33_PC1_HANDLER */ 119 #define MXCM33_CM33_PC1_HANDLER_ADDR_Pos 0UL 120 #define MXCM33_CM33_PC1_HANDLER_ADDR_Msk 0xFFFFFFFFUL 121 /* MXCM33.CM33_PC2_HANDLER */ 122 #define MXCM33_CM33_PC2_HANDLER_ADDR_Pos 0UL 123 #define MXCM33_CM33_PC2_HANDLER_ADDR_Msk 0xFFFFFFFFUL 124 /* MXCM33.CM33_PC3_HANDLER */ 125 #define MXCM33_CM33_PC3_HANDLER_ADDR_Pos 0UL 126 #define MXCM33_CM33_PC3_HANDLER_ADDR_Msk 0xFFFFFFFFUL 127 /* MXCM33.CM33_SYSTEM_INT_CTL */ 128 #define MXCM33_CM33_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL 129 #define MXCM33_CM33_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0xFUL 130 #define MXCM33_CM33_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 131 #define MXCM33_CM33_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 132 133 134 #endif /* _CYIP_MXCM33_H_ */ 135 136 137 /* [] END OF FILE */ 138
