1 /***************************************************************************//** 2 * \file cyip_srss_v3.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_V3_H_ 28 #define _CYIP_SRSS_V3_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define CSV_HF_CSV_SECTION_SIZE 0x00000010UL 37 #define CSV_HF_SECTION_SIZE 0x00000100UL 38 #define CSV_REF_CSV_SECTION_SIZE 0x00000010UL 39 #define CSV_REF_SECTION_SIZE 0x00000010UL 40 #define CSV_LF_CSV_SECTION_SIZE 0x00000010UL 41 #define CSV_LF_SECTION_SIZE 0x00000010UL 42 #define CSV_ILO_CSV_SECTION_SIZE 0x00000010UL 43 #define CSV_ILO_SECTION_SIZE 0x00000010UL 44 #define CLK_PLL400M_SECTION_SIZE 0x00000010UL 45 #define MCWDT_CTR_SECTION_SIZE 0x00000020UL 46 #define MCWDT_SECTION_SIZE 0x00000100UL 47 #define WDT_SECTION_SIZE 0x00000080UL 48 #define SRSS_SECTION_SIZE 0x00010000UL 49 50 /** 51 * \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV) 52 */ 53 typedef struct { 54 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 55 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 56 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 57 __IM uint32_t RESERVED; 58 } CSV_HF_CSV_Type; /*!< Size = 16 (0x10) */ 59 60 /** 61 * \brief Clock Supervisor (CSV) registers for Root clocks (CSV_HF) 62 */ 63 typedef struct { 64 CSV_HF_CSV_Type CSV[16]; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers */ 65 } CSV_HF_Type; /*!< Size = 256 (0x100) */ 66 67 /** 68 * \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV) 69 */ 70 typedef struct { 71 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 72 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 73 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 74 __IM uint32_t RESERVED; 75 } CSV_REF_CSV_Type; /*!< Size = 16 (0x10) */ 76 77 /** 78 * \brief CSV registers for the CSV Reference clock (CSV_REF) 79 */ 80 typedef struct { 81 CSV_REF_CSV_Type CSV; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers for CSV 82 Reference clock */ 83 } CSV_REF_Type; /*!< Size = 16 (0x10) */ 84 85 /** 86 * \brief LF clock Clock Supervisor registers (CSV_LF_CSV) 87 */ 88 typedef struct { 89 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 90 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 91 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 92 __IM uint32_t RESERVED; 93 } CSV_LF_CSV_Type; /*!< Size = 16 (0x10) */ 94 95 /** 96 * \brief CSV registers for LF clock (CSV_LF) 97 */ 98 typedef struct { 99 CSV_LF_CSV_Type CSV; /*!< 0x00000000 LF clock Clock Supervisor registers */ 100 } CSV_LF_Type; /*!< Size = 16 (0x10) */ 101 102 /** 103 * \brief ILO0 clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV) 104 */ 105 typedef struct { 106 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 107 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 108 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 109 __IM uint32_t RESERVED; 110 } CSV_ILO_CSV_Type; /*!< Size = 16 (0x10) */ 111 112 /** 113 * \brief CSV registers for HVILO clock (CSV_ILO) 114 */ 115 typedef struct { 116 CSV_ILO_CSV_Type CSV; /*!< 0x00000000 ILO0 clock DeepSleep domain Clock Supervisor registers */ 117 } CSV_ILO_Type; /*!< Size = 16 (0x10) */ 118 119 /** 120 * \brief 400MHz PLL Configuration Register (CLK_PLL400M) 121 */ 122 typedef struct { 123 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ 124 __IOM uint32_t CONFIG2; /*!< 0x00000004 400MHz PLL Configuration Register 2 */ 125 __IOM uint32_t CONFIG3; /*!< 0x00000008 400MHz PLL Configuration Register 3 */ 126 __IOM uint32_t STATUS; /*!< 0x0000000C 400MHz PLL Status Register */ 127 } CLK_PLL400M_Type; /*!< Size = 16 (0x10) */ 128 129 /** 130 * \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR) 131 */ 132 typedef struct { 133 __IOM uint32_t CTL; /*!< 0x00000000 MCWDT Subcounter Control Register */ 134 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 MCWDT Subcounter Lower Limit Register */ 135 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 MCWDT Subcounter Upper Limit Register */ 136 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C MCWDT Subcounter Warn Limit Register */ 137 __IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Register */ 138 __IOM uint32_t CNT; /*!< 0x00000014 MCWDT Subcounter Count Register */ 139 __IM uint32_t RESERVED[2]; 140 } MCWDT_CTR_Type; /*!< Size = 32 (0x20) */ 141 142 /** 143 * \brief Multi-Counter Watchdog Timer (MCWDT) 144 */ 145 typedef struct { 146 MCWDT_CTR_Type CTR[2]; /*!< 0x00000000 MCWDT Configuration for Subcounter 0 and 1 */ 147 __IOM uint32_t CPU_SELECT; /*!< 0x00000040 MCWDT CPU selection register */ 148 __IM uint32_t RESERVED[15]; 149 __IOM uint32_t CTR2_CTL; /*!< 0x00000080 MCWDT Subcounter 2 Control register */ 150 __IOM uint32_t CTR2_CONFIG; /*!< 0x00000084 MCWDT Subcounter 2 Configuration register */ 151 __IOM uint32_t CTR2_CNT; /*!< 0x00000088 MCWDT Subcounter 2 Count Register */ 152 __IM uint32_t RESERVED1; 153 __IOM uint32_t LOCK; /*!< 0x00000090 MCWDT Lock Register */ 154 __IOM uint32_t SERVICE; /*!< 0x00000094 MCWDT Service Register */ 155 __IM uint32_t RESERVED2[2]; 156 __IOM uint32_t INTR; /*!< 0x000000A0 MCWDT Interrupt Register */ 157 __IOM uint32_t INTR_SET; /*!< 0x000000A4 MCWDT Interrupt Set Register */ 158 __IOM uint32_t INTR_MASK; /*!< 0x000000A8 MCWDT Interrupt Mask Register */ 159 __IM uint32_t INTR_MASKED; /*!< 0x000000AC MCWDT Interrupt Masked Register */ 160 __IM uint32_t RESERVED3[20]; 161 } MCWDT_Type; /*!< Size = 256 (0x100) */ 162 163 /** 164 * \brief Watchdog Timer (WDT) 165 */ 166 typedef struct { 167 __IOM uint32_t CTL; /*!< 0x00000000 WDT Control Register */ 168 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 WDT Lower Limit Register */ 169 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 WDT Upper Limit Register */ 170 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C WDT Warn Limit Register */ 171 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ 172 __IOM uint32_t CNT; /*!< 0x00000014 WDT Count Register */ 173 __IM uint32_t RESERVED[10]; 174 __IOM uint32_t LOCK; /*!< 0x00000040 WDT Lock register */ 175 __IOM uint32_t SERVICE; /*!< 0x00000044 WDT Service register */ 176 __IM uint32_t RESERVED1[2]; 177 __IOM uint32_t INTR; /*!< 0x00000050 WDT Interrupt Register */ 178 __IOM uint32_t INTR_SET; /*!< 0x00000054 WDT Interrupt Set Register */ 179 __IOM uint32_t INTR_MASK; /*!< 0x00000058 WDT Interrupt Mask Register */ 180 __IM uint32_t INTR_MASKED; /*!< 0x0000005C WDT Interrupt Masked Register */ 181 __IM uint32_t RESERVED2[8]; 182 } WDT_Type; /*!< Size = 128 (0x80) */ 183 184 /** 185 * \brief SRSS Core Registers (ver3) (SRSS) 186 */ 187 typedef struct { 188 __IM uint32_t RESERVED[16]; 189 __IM uint32_t PWR_LVD_STATUS; /*!< 0x00000040 High Voltage / Low Voltage Detector (HVLVD) Status Register */ 190 __IM uint32_t PWR_LVD_STATUS2; /*!< 0x00000044 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 */ 191 __IM uint32_t RESERVED1[46]; 192 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000100 Clock DSI Select Register */ 193 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000140 Fast Clock Output Select Register */ 194 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000144 Slow Clock Output Select Register */ 195 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x00000148 Clock Calibration Counter 1 */ 196 __IM uint32_t CLK_CAL_CNT2; /*!< 0x0000014C Clock Calibration Counter 2 */ 197 __IM uint32_t RESERVED2[44]; 198 __IOM uint32_t SRSS_INTR; /*!< 0x00000200 SRSS Interrupt Register */ 199 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000204 SRSS Interrupt Set Register */ 200 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000208 SRSS Interrupt Mask Register */ 201 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000020C SRSS Interrupt Masked Register */ 202 __IM uint32_t RESERVED3[892]; 203 __IM uint32_t PWR_CTL; /*!< 0x00001000 Power Mode Control */ 204 __IOM uint32_t PWR_CTL2; /*!< 0x00001004 Power Mode Control 2 */ 205 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00001008 HIBERNATE Mode Register */ 206 __IM uint32_t RESERVED4; 207 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00001010 Buck Control Register */ 208 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00001014 Buck Control Register 2 */ 209 __IOM uint32_t PWR_SSV_CTL; /*!< 0x00001018 Supply Supervision Control Register */ 210 __IM uint32_t PWR_SSV_STATUS; /*!< 0x0000101C Supply Supervision Status Register */ 211 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration 212 Register */ 213 __IOM uint32_t PWR_LVD_CTL2; /*!< 0x00001024 High Voltage / Low Voltage Detector (HVLVD) Configuration 214 Register #2 */ 215 __IOM uint32_t PWR_REGHC_CTL; /*!< 0x00001028 REGHC Control Register */ 216 __IM uint32_t PWR_REGHC_STATUS; /*!< 0x0000102C REGHC Status Register */ 217 __IOM uint32_t PWR_REGHC_CTL2; /*!< 0x00001030 REGHC Control Register 2 */ 218 __IM uint32_t RESERVED5; 219 __IOM uint32_t PWR_REGHC_CTL4; /*!< 0x00001038 REGHC Control Register 4 */ 220 __IM uint32_t RESERVED6; 221 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00001040 HIBERNATE Data Register */ 222 __IM uint32_t RESERVED7[16]; 223 __IOM uint32_t PWR_PMIC_CTL; /*!< 0x000010C0 PMIC Control Register */ 224 __IM uint32_t PWR_PMIC_STATUS; /*!< 0x000010C4 PMIC Status Register */ 225 __IOM uint32_t PWR_PMIC_CTL2; /*!< 0x000010C8 PMIC Control Register 2 */ 226 __IM uint32_t RESERVED8; 227 __IOM uint32_t PWR_PMIC_CTL4; /*!< 0x000010D0 PMIC Control Register 4 */ 228 __IM uint32_t RESERVED9[75]; 229 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00001200 Clock Path Select Register */ 230 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00001240 Clock Root Select Register */ 231 __IM uint32_t RESERVED10[96]; 232 CSV_HF_Type CSV_HF; /*!< 0x00001400 Clock Supervisor (CSV) registers for Root clocks */ 233 __IOM uint32_t CLK_SELECT; /*!< 0x00001500 Clock selection register */ 234 __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00001504 Timer Clock Control Register */ 235 __IOM uint32_t CLK_ILO0_CONFIG; /*!< 0x00001508 ILO0 Configuration */ 236 __IOM uint32_t CLK_ILO1_CONFIG; /*!< 0x0000150C ILO1 Configuration */ 237 __IM uint32_t RESERVED11[2]; 238 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00001518 IMO Configuration */ 239 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000151C ECO Configuration Register */ 240 __IOM uint32_t CLK_ECO_PRESCALE; /*!< 0x00001520 ECO Prescaler Configuration Register */ 241 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00001524 ECO Status Register */ 242 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x00001528 Precision ILO Configuration Register */ 243 __IM uint32_t RESERVED12; 244 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00001530 FLL Configuration Register */ 245 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00001534 FLL Configuration Register 2 */ 246 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00001538 FLL Configuration Register 3 */ 247 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000153C FLL Configuration Register 4 */ 248 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00001540 FLL Status Register */ 249 __IOM uint32_t CLK_ECO_CONFIG2; /*!< 0x00001544 ECO Configuration Register 2 */ 250 __IM uint32_t RESERVED13[46]; 251 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00001600 PLL Configuration Register */ 252 __IM uint32_t RESERVED14; 253 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00001640 PLL Status Register */ 254 __IM uint32_t RESERVED15[33]; 255 __IOM uint32_t CSV_REF_SEL; /*!< 0x00001700 Select CSV Reference clock for Active domain */ 256 __IM uint32_t RESERVED16[3]; 257 CSV_REF_Type CSV_REF; /*!< 0x00001710 CSV registers for the CSV Reference clock */ 258 CSV_LF_Type CSV_LF; /*!< 0x00001720 CSV registers for LF clock */ 259 CSV_ILO_Type CSV_ILO; /*!< 0x00001730 CSV registers for HVILO clock */ 260 __IM uint32_t RESERVED17[48]; 261 __IOM uint32_t RES_CAUSE; /*!< 0x00001800 Reset Cause Observation Register */ 262 __IOM uint32_t RES_CAUSE2; /*!< 0x00001804 Reset Cause Observation Register 2 */ 263 __IM uint32_t RESERVED18[62]; 264 CLK_PLL400M_Type CLK_PLL400M[15]; /*!< 0x00001900 400MHz PLL Configuration Register */ 265 __IM uint32_t RESERVED19[1417]; 266 __IOM uint32_t CLK_TRIM_ILO0_CTL; /*!< 0x00003014 ILO0 Trim Register */ 267 __IM uint32_t RESERVED20[60]; 268 __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x00003108 Power System Trim Register */ 269 __IM uint32_t RESERVED21[2]; 270 __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x00003114 PILO Trim Register */ 271 __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x00003118 PILO Trim Register 2 */ 272 __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000311C PILO Trim Register 3 */ 273 __IM uint32_t RESERVED22[64]; 274 __IOM uint32_t CLK_TRIM_ILO1_CTL; /*!< 0x00003220 ILO1 Trim Register */ 275 __IM uint32_t RESERVED23[4983]; 276 MCWDT_Type MCWDT[4]; /*!< 0x00008000 Multi-Counter Watchdog Timer */ 277 __IM uint32_t RESERVED24[3840]; 278 WDT_Type WDT_STRUCT; /*!< 0x0000C000 Watchdog Timer */ 279 } SRSS_Type; /*!< Size = 49280 (0xC080) */ 280 281 282 /* CSV_HF_CSV.REF_CTL */ 283 #define CSV_HF_CSV_REF_CTL_STARTUP_Pos 0UL 284 #define CSV_HF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 285 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 286 #define CSV_HF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 287 #define CSV_HF_CSV_REF_CTL_CSV_EN_Pos 31UL 288 #define CSV_HF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 289 /* CSV_HF_CSV.REF_LIMIT */ 290 #define CSV_HF_CSV_REF_LIMIT_LOWER_Pos 0UL 291 #define CSV_HF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 292 #define CSV_HF_CSV_REF_LIMIT_UPPER_Pos 16UL 293 #define CSV_HF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 294 /* CSV_HF_CSV.MON_CTL */ 295 #define CSV_HF_CSV_MON_CTL_PERIOD_Pos 0UL 296 #define CSV_HF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 297 298 299 /* CSV_REF_CSV.REF_CTL */ 300 #define CSV_REF_CSV_REF_CTL_STARTUP_Pos 0UL 301 #define CSV_REF_CSV_REF_CTL_STARTUP_Msk 0xFFFFUL 302 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Pos 30UL 303 #define CSV_REF_CSV_REF_CTL_CSV_ACTION_Msk 0x40000000UL 304 #define CSV_REF_CSV_REF_CTL_CSV_EN_Pos 31UL 305 #define CSV_REF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 306 /* CSV_REF_CSV.REF_LIMIT */ 307 #define CSV_REF_CSV_REF_LIMIT_LOWER_Pos 0UL 308 #define CSV_REF_CSV_REF_LIMIT_LOWER_Msk 0xFFFFUL 309 #define CSV_REF_CSV_REF_LIMIT_UPPER_Pos 16UL 310 #define CSV_REF_CSV_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 311 /* CSV_REF_CSV.MON_CTL */ 312 #define CSV_REF_CSV_MON_CTL_PERIOD_Pos 0UL 313 #define CSV_REF_CSV_MON_CTL_PERIOD_Msk 0xFFFFUL 314 315 316 /* CSV_LF_CSV.REF_CTL */ 317 #define CSV_LF_CSV_REF_CTL_STARTUP_Pos 0UL 318 #define CSV_LF_CSV_REF_CTL_STARTUP_Msk 0xFFUL 319 #define CSV_LF_CSV_REF_CTL_CSV_EN_Pos 31UL 320 #define CSV_LF_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 321 /* CSV_LF_CSV.REF_LIMIT */ 322 #define CSV_LF_CSV_REF_LIMIT_LOWER_Pos 0UL 323 #define CSV_LF_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 324 #define CSV_LF_CSV_REF_LIMIT_UPPER_Pos 16UL 325 #define CSV_LF_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 326 /* CSV_LF_CSV.MON_CTL */ 327 #define CSV_LF_CSV_MON_CTL_PERIOD_Pos 0UL 328 #define CSV_LF_CSV_MON_CTL_PERIOD_Msk 0xFFUL 329 330 331 /* CSV_ILO_CSV.REF_CTL */ 332 #define CSV_ILO_CSV_REF_CTL_STARTUP_Pos 0UL 333 #define CSV_ILO_CSV_REF_CTL_STARTUP_Msk 0xFFUL 334 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Pos 31UL 335 #define CSV_ILO_CSV_REF_CTL_CSV_EN_Msk 0x80000000UL 336 /* CSV_ILO_CSV.REF_LIMIT */ 337 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Pos 0UL 338 #define CSV_ILO_CSV_REF_LIMIT_LOWER_Msk 0xFFUL 339 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Pos 16UL 340 #define CSV_ILO_CSV_REF_LIMIT_UPPER_Msk 0xFF0000UL 341 /* CSV_ILO_CSV.MON_CTL */ 342 #define CSV_ILO_CSV_MON_CTL_PERIOD_Pos 0UL 343 #define CSV_ILO_CSV_MON_CTL_PERIOD_Msk 0xFFUL 344 345 346 /* CLK_PLL400M.CONFIG */ 347 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Pos 0UL 348 #define CLK_PLL400M_CONFIG_FEEDBACK_DIV_Msk 0xFFUL 349 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Pos 8UL 350 #define CLK_PLL400M_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 351 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Pos 16UL 352 #define CLK_PLL400M_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 353 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Pos 25UL 354 #define CLK_PLL400M_CONFIG_LOCK_DELAY_Msk 0x6000000UL 355 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Pos 28UL 356 #define CLK_PLL400M_CONFIG_BYPASS_SEL_Msk 0x30000000UL 357 #define CLK_PLL400M_CONFIG_ENABLE_Pos 31UL 358 #define CLK_PLL400M_CONFIG_ENABLE_Msk 0x80000000UL 359 /* CLK_PLL400M.CONFIG2 */ 360 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Pos 0UL 361 #define CLK_PLL400M_CONFIG2_FRAC_DIV_Msk 0xFFFFFFUL 362 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Pos 28UL 363 #define CLK_PLL400M_CONFIG2_FRAC_DITHER_EN_Msk 0x70000000UL 364 #define CLK_PLL400M_CONFIG2_FRAC_EN_Pos 31UL 365 #define CLK_PLL400M_CONFIG2_FRAC_EN_Msk 0x80000000UL 366 /* CLK_PLL400M.CONFIG3 */ 367 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Pos 0UL 368 #define CLK_PLL400M_CONFIG3_SSCG_DEPTH_Msk 0x3FFUL 369 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Pos 16UL 370 #define CLK_PLL400M_CONFIG3_SSCG_RATE_Msk 0x70000UL 371 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Pos 24UL 372 #define CLK_PLL400M_CONFIG3_SSCG_DITHER_EN_Msk 0x1000000UL 373 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Pos 28UL 374 #define CLK_PLL400M_CONFIG3_SSCG_MODE_Msk 0x10000000UL 375 #define CLK_PLL400M_CONFIG3_SSCG_EN_Pos 31UL 376 #define CLK_PLL400M_CONFIG3_SSCG_EN_Msk 0x80000000UL 377 /* CLK_PLL400M.STATUS */ 378 #define CLK_PLL400M_STATUS_LOCKED_Pos 0UL 379 #define CLK_PLL400M_STATUS_LOCKED_Msk 0x1UL 380 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Pos 1UL 381 #define CLK_PLL400M_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 382 383 384 /* MCWDT_CTR.CTL */ 385 #define MCWDT_CTR_CTL_ENABLED_Pos 0UL 386 #define MCWDT_CTR_CTL_ENABLED_Msk 0x1UL 387 #define MCWDT_CTR_CTL_ENABLE_Pos 31UL 388 #define MCWDT_CTR_CTL_ENABLE_Msk 0x80000000UL 389 /* MCWDT_CTR.LOWER_LIMIT */ 390 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 391 #define MCWDT_CTR_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFUL 392 /* MCWDT_CTR.UPPER_LIMIT */ 393 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 394 #define MCWDT_CTR_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFUL 395 /* MCWDT_CTR.WARN_LIMIT */ 396 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Pos 0UL 397 #define MCWDT_CTR_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFUL 398 /* MCWDT_CTR.CONFIG */ 399 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Pos 0UL 400 #define MCWDT_CTR_CONFIG_LOWER_ACTION_Msk 0x3UL 401 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Pos 4UL 402 #define MCWDT_CTR_CONFIG_UPPER_ACTION_Msk 0x30UL 403 #define MCWDT_CTR_CONFIG_WARN_ACTION_Pos 8UL 404 #define MCWDT_CTR_CONFIG_WARN_ACTION_Msk 0x100UL 405 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Pos 12UL 406 #define MCWDT_CTR_CONFIG_AUTO_SERVICE_Msk 0x1000UL 407 #define MCWDT_CTR_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 408 #define MCWDT_CTR_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 409 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 410 #define MCWDT_CTR_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 411 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Pos 31UL 412 #define MCWDT_CTR_CONFIG_DEBUG_RUN_Msk 0x80000000UL 413 /* MCWDT_CTR.CNT */ 414 #define MCWDT_CTR_CNT_CNT_Pos 0UL 415 #define MCWDT_CTR_CNT_CNT_Msk 0xFFFFUL 416 417 418 /* MCWDT.CPU_SELECT */ 419 #define MCWDT_CPU_SELECT_CPU_SEL_Pos 0UL 420 #define MCWDT_CPU_SELECT_CPU_SEL_Msk 0x3UL 421 /* MCWDT.CTR2_CTL */ 422 #define MCWDT_CTR2_CTL_ENABLED_Pos 0UL 423 #define MCWDT_CTR2_CTL_ENABLED_Msk 0x1UL 424 #define MCWDT_CTR2_CTL_ENABLE_Pos 31UL 425 #define MCWDT_CTR2_CTL_ENABLE_Msk 0x80000000UL 426 /* MCWDT.CTR2_CONFIG */ 427 #define MCWDT_CTR2_CONFIG_ACTION_Pos 0UL 428 #define MCWDT_CTR2_CONFIG_ACTION_Msk 0x1UL 429 #define MCWDT_CTR2_CONFIG_BITS_Pos 16UL 430 #define MCWDT_CTR2_CONFIG_BITS_Msk 0x1F0000UL 431 #define MCWDT_CTR2_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 432 #define MCWDT_CTR2_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 433 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 434 #define MCWDT_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 435 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Pos 31UL 436 #define MCWDT_CTR2_CONFIG_DEBUG_RUN_Msk 0x80000000UL 437 /* MCWDT.CTR2_CNT */ 438 #define MCWDT_CTR2_CNT_CNT2_Pos 0UL 439 #define MCWDT_CTR2_CNT_CNT2_Msk 0xFFFFFFFFUL 440 /* MCWDT.LOCK */ 441 #define MCWDT_LOCK_MCWDT_LOCK_Pos 0UL 442 #define MCWDT_LOCK_MCWDT_LOCK_Msk 0x3UL 443 /* MCWDT.SERVICE */ 444 #define MCWDT_SERVICE_CTR0_SERVICE_Pos 0UL 445 #define MCWDT_SERVICE_CTR0_SERVICE_Msk 0x1UL 446 #define MCWDT_SERVICE_CTR1_SERVICE_Pos 1UL 447 #define MCWDT_SERVICE_CTR1_SERVICE_Msk 0x2UL 448 /* MCWDT.INTR */ 449 #define MCWDT_INTR_CTR0_INT_Pos 0UL 450 #define MCWDT_INTR_CTR0_INT_Msk 0x1UL 451 #define MCWDT_INTR_CTR1_INT_Pos 1UL 452 #define MCWDT_INTR_CTR1_INT_Msk 0x2UL 453 #define MCWDT_INTR_CTR2_INT_Pos 2UL 454 #define MCWDT_INTR_CTR2_INT_Msk 0x4UL 455 /* MCWDT.INTR_SET */ 456 #define MCWDT_INTR_SET_CTR0_INT_Pos 0UL 457 #define MCWDT_INTR_SET_CTR0_INT_Msk 0x1UL 458 #define MCWDT_INTR_SET_CTR1_INT_Pos 1UL 459 #define MCWDT_INTR_SET_CTR1_INT_Msk 0x2UL 460 #define MCWDT_INTR_SET_CTR2_INT_Pos 2UL 461 #define MCWDT_INTR_SET_CTR2_INT_Msk 0x4UL 462 /* MCWDT.INTR_MASK */ 463 #define MCWDT_INTR_MASK_CTR0_INT_Pos 0UL 464 #define MCWDT_INTR_MASK_CTR0_INT_Msk 0x1UL 465 #define MCWDT_INTR_MASK_CTR1_INT_Pos 1UL 466 #define MCWDT_INTR_MASK_CTR1_INT_Msk 0x2UL 467 #define MCWDT_INTR_MASK_CTR2_INT_Pos 2UL 468 #define MCWDT_INTR_MASK_CTR2_INT_Msk 0x4UL 469 /* MCWDT.INTR_MASKED */ 470 #define MCWDT_INTR_MASKED_CTR0_INT_Pos 0UL 471 #define MCWDT_INTR_MASKED_CTR0_INT_Msk 0x1UL 472 #define MCWDT_INTR_MASKED_CTR1_INT_Pos 1UL 473 #define MCWDT_INTR_MASKED_CTR1_INT_Msk 0x2UL 474 #define MCWDT_INTR_MASKED_CTR2_INT_Pos 2UL 475 #define MCWDT_INTR_MASKED_CTR2_INT_Msk 0x4UL 476 477 478 /* WDT.CTL */ 479 #define WDT_CTL_ENABLED_Pos 0UL 480 #define WDT_CTL_ENABLED_Msk 0x1UL 481 #define WDT_CTL_ENABLE_Pos 31UL 482 #define WDT_CTL_ENABLE_Msk 0x80000000UL 483 /* WDT.LOWER_LIMIT */ 484 #define WDT_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 485 #define WDT_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFFFFFUL 486 /* WDT.UPPER_LIMIT */ 487 #define WDT_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 488 #define WDT_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFFFFFUL 489 /* WDT.WARN_LIMIT */ 490 #define WDT_WARN_LIMIT_WARN_LIMIT_Pos 0UL 491 #define WDT_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFFFFFUL 492 /* WDT.CONFIG */ 493 #define WDT_CONFIG_LOWER_ACTION_Pos 0UL 494 #define WDT_CONFIG_LOWER_ACTION_Msk 0x1UL 495 #define WDT_CONFIG_UPPER_ACTION_Pos 4UL 496 #define WDT_CONFIG_UPPER_ACTION_Msk 0x10UL 497 #define WDT_CONFIG_WARN_ACTION_Pos 8UL 498 #define WDT_CONFIG_WARN_ACTION_Msk 0x100UL 499 #define WDT_CONFIG_AUTO_SERVICE_Pos 12UL 500 #define WDT_CONFIG_AUTO_SERVICE_Msk 0x1000UL 501 #define WDT_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 502 #define WDT_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 503 #define WDT_CONFIG_DPSLP_PAUSE_Pos 29UL 504 #define WDT_CONFIG_DPSLP_PAUSE_Msk 0x20000000UL 505 #define WDT_CONFIG_HIB_PAUSE_Pos 30UL 506 #define WDT_CONFIG_HIB_PAUSE_Msk 0x40000000UL 507 #define WDT_CONFIG_DEBUG_RUN_Pos 31UL 508 #define WDT_CONFIG_DEBUG_RUN_Msk 0x80000000UL 509 /* WDT.CNT */ 510 #define WDT_CNT_CNT_Pos 0UL 511 #define WDT_CNT_CNT_Msk 0xFFFFFFFFUL 512 /* WDT.LOCK */ 513 #define WDT_LOCK_WDT_LOCK_Pos 0UL 514 #define WDT_LOCK_WDT_LOCK_Msk 0x3UL 515 /* WDT.SERVICE */ 516 #define WDT_SERVICE_SERVICE_Pos 0UL 517 #define WDT_SERVICE_SERVICE_Msk 0x1UL 518 /* WDT.INTR */ 519 #define WDT_INTR_WDT_Pos 0UL 520 #define WDT_INTR_WDT_Msk 0x1UL 521 /* WDT.INTR_SET */ 522 #define WDT_INTR_SET_WDT_Pos 0UL 523 #define WDT_INTR_SET_WDT_Msk 0x1UL 524 /* WDT.INTR_MASK */ 525 #define WDT_INTR_MASK_WDT_Pos 0UL 526 #define WDT_INTR_MASK_WDT_Msk 0x1UL 527 /* WDT.INTR_MASKED */ 528 #define WDT_INTR_MASKED_WDT_Pos 0UL 529 #define WDT_INTR_MASKED_WDT_Msk 0x1UL 530 531 532 /* SRSS.PWR_LVD_STATUS */ 533 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Pos 0UL 534 #define SRSS_PWR_LVD_STATUS_HVLVD1_OUT_Msk 0x1UL 535 /* SRSS.PWR_LVD_STATUS2 */ 536 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 0UL 537 #define SRSS_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 0x1UL 538 /* SRSS.CLK_DSI_SELECT */ 539 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 540 #define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 541 /* SRSS.CLK_OUTPUT_FAST */ 542 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 543 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 544 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 545 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 546 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 547 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 548 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 549 #define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 550 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 551 #define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 552 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 553 #define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 554 /* SRSS.CLK_OUTPUT_SLOW */ 555 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 556 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 557 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 558 #define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 559 /* SRSS.CLK_CAL_CNT1 */ 560 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 561 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 562 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 563 #define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 564 /* SRSS.CLK_CAL_CNT2 */ 565 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 566 #define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 567 /* SRSS.SRSS_INTR */ 568 #define SRSS_SRSS_INTR_HVLVD1_Pos 1UL 569 #define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL 570 #define SRSS_SRSS_INTR_HVLVD2_Pos 2UL 571 #define SRSS_SRSS_INTR_HVLVD2_Msk 0x4UL 572 #define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL 573 #define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL 574 /* SRSS.SRSS_INTR_SET */ 575 #define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL 576 #define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL 577 #define SRSS_SRSS_INTR_SET_HVLVD2_Pos 2UL 578 #define SRSS_SRSS_INTR_SET_HVLVD2_Msk 0x4UL 579 #define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL 580 #define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 581 /* SRSS.SRSS_INTR_MASK */ 582 #define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL 583 #define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL 584 #define SRSS_SRSS_INTR_MASK_HVLVD2_Pos 2UL 585 #define SRSS_SRSS_INTR_MASK_HVLVD2_Msk 0x4UL 586 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 587 #define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 588 /* SRSS.SRSS_INTR_MASKED */ 589 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL 590 #define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL 591 #define SRSS_SRSS_INTR_MASKED_HVLVD2_Pos 2UL 592 #define SRSS_SRSS_INTR_MASKED_HVLVD2_Msk 0x4UL 593 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 594 #define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 595 /* SRSS.PWR_CTL */ 596 #define SRSS_PWR_CTL_POWER_MODE_Pos 0UL 597 #define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL 598 #define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL 599 #define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 600 #define SRSS_PWR_CTL_LPM_READY_Pos 5UL 601 #define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL 602 /* SRSS.PWR_CTL2 */ 603 #define SRSS_PWR_CTL2_LINREG_DIS_Pos 0UL 604 #define SRSS_PWR_CTL2_LINREG_DIS_Msk 0x1UL 605 #define SRSS_PWR_CTL2_LINREG_OK_Pos 1UL 606 #define SRSS_PWR_CTL2_LINREG_OK_Msk 0x2UL 607 #define SRSS_PWR_CTL2_LINREG_LPMODE_Pos 2UL 608 #define SRSS_PWR_CTL2_LINREG_LPMODE_Msk 0x4UL 609 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Pos 4UL 610 #define SRSS_PWR_CTL2_DPSLP_REG_DIS_Msk 0x10UL 611 #define SRSS_PWR_CTL2_RET_REG_DIS_Pos 8UL 612 #define SRSS_PWR_CTL2_RET_REG_DIS_Msk 0x100UL 613 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Pos 12UL 614 #define SRSS_PWR_CTL2_NWELL_REG_DIS_Msk 0x1000UL 615 #define SRSS_PWR_CTL2_REFV_DIS_Pos 16UL 616 #define SRSS_PWR_CTL2_REFV_DIS_Msk 0x10000UL 617 #define SRSS_PWR_CTL2_REFV_OK_Pos 17UL 618 #define SRSS_PWR_CTL2_REFV_OK_Msk 0x20000UL 619 #define SRSS_PWR_CTL2_REFVBUF_DIS_Pos 20UL 620 #define SRSS_PWR_CTL2_REFVBUF_DIS_Msk 0x100000UL 621 #define SRSS_PWR_CTL2_REFVBUF_OK_Pos 21UL 622 #define SRSS_PWR_CTL2_REFVBUF_OK_Msk 0x200000UL 623 #define SRSS_PWR_CTL2_REFVBUF_LPMODE_Pos 22UL 624 #define SRSS_PWR_CTL2_REFVBUF_LPMODE_Msk 0x400000UL 625 #define SRSS_PWR_CTL2_REFI_DIS_Pos 24UL 626 #define SRSS_PWR_CTL2_REFI_DIS_Msk 0x1000000UL 627 #define SRSS_PWR_CTL2_REFI_OK_Pos 25UL 628 #define SRSS_PWR_CTL2_REFI_OK_Msk 0x2000000UL 629 #define SRSS_PWR_CTL2_REFI_LPMODE_Pos 26UL 630 #define SRSS_PWR_CTL2_REFI_LPMODE_Msk 0x4000000UL 631 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Pos 27UL 632 #define SRSS_PWR_CTL2_PORBOD_LPMODE_Msk 0x8000000UL 633 #define SRSS_PWR_CTL2_BGREF_LPMODE_Pos 28UL 634 #define SRSS_PWR_CTL2_BGREF_LPMODE_Msk 0x10000000UL 635 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Pos 31UL 636 #define SRSS_PWR_CTL2_PLL_LS_BYPASS_Msk 0x80000000UL 637 /* SRSS.PWR_HIBERNATE */ 638 #define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL 639 #define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 640 #define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL 641 #define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 642 #define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL 643 #define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 644 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 645 #define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 646 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 647 #define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 648 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 649 #define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 650 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 651 #define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 652 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 653 #define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 654 #define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL 655 #define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 656 /* SRSS.PWR_BUCK_CTL */ 657 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 658 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 659 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 660 #define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 661 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 662 #define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 663 /* SRSS.PWR_BUCK_CTL2 */ 664 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 665 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 666 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 667 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 668 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 669 #define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 670 /* SRSS.PWR_SSV_CTL */ 671 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Pos 0UL 672 #define SRSS_PWR_SSV_CTL_BODVDDD_VSEL_Msk 0x1UL 673 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 3UL 674 #define SRSS_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 0x8UL 675 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Pos 4UL 676 #define SRSS_PWR_SSV_CTL_BODVDDA_VSEL_Msk 0x10UL 677 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Pos 6UL 678 #define SRSS_PWR_SSV_CTL_BODVDDA_ACTION_Msk 0xC0UL 679 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 8UL 680 #define SRSS_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 0x100UL 681 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 11UL 682 #define SRSS_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 0x800UL 683 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 16UL 684 #define SRSS_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 0x10000UL 685 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 19UL 686 #define SRSS_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 0x80000UL 687 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 20UL 688 #define SRSS_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 0x100000UL 689 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 22UL 690 #define SRSS_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 0xC00000UL 691 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 24UL 692 #define SRSS_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 0x1000000UL 693 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 27UL 694 #define SRSS_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 0x8000000UL 695 /* SRSS.PWR_SSV_STATUS */ 696 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Pos 0UL 697 #define SRSS_PWR_SSV_STATUS_BODVDDD_OK_Msk 0x1UL 698 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Pos 1UL 699 #define SRSS_PWR_SSV_STATUS_BODVDDA_OK_Msk 0x2UL 700 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Pos 2UL 701 #define SRSS_PWR_SSV_STATUS_BODVCCD_OK_Msk 0x4UL 702 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Pos 8UL 703 #define SRSS_PWR_SSV_STATUS_OVDVDDD_OK_Msk 0x100UL 704 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Pos 9UL 705 #define SRSS_PWR_SSV_STATUS_OVDVDDA_OK_Msk 0x200UL 706 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Pos 10UL 707 #define SRSS_PWR_SSV_STATUS_OVDVCCD_OK_Msk 0x400UL 708 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Pos 16UL 709 #define SRSS_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Msk 0x10000UL 710 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Pos 17UL 711 #define SRSS_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Msk 0x20000UL 712 /* SRSS.PWR_LVD_CTL */ 713 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 714 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 715 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 716 #define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 717 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 718 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 719 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 8UL 720 #define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 0x1F00UL 721 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 14UL 722 #define SRSS_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 0x4000UL 723 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 15UL 724 #define SRSS_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 0x8000UL 725 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 16UL 726 #define SRSS_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 0x30000UL 727 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Pos 18UL 728 #define SRSS_PWR_LVD_CTL_HVLVD1_ACTION_Msk 0x40000UL 729 /* SRSS.PWR_LVD_CTL2 */ 730 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 8UL 731 #define SRSS_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 0x1F00UL 732 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 14UL 733 #define SRSS_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 0x4000UL 734 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 15UL 735 #define SRSS_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 0x8000UL 736 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 16UL 737 #define SRSS_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 0x30000UL 738 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 18UL 739 #define SRSS_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 0x40000UL 740 /* SRSS.PWR_REGHC_CTL */ 741 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Pos 0UL 742 #define SRSS_PWR_REGHC_CTL_REGHC_MODE_Msk 0x1UL 743 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Pos 2UL 744 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_DRV_VOUT_Msk 0xCUL 745 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Pos 4UL 746 #define SRSS_PWR_REGHC_CTL_REGHC_VADJ_Msk 0x1F0UL 747 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Pos 10UL 748 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_LINREG_Msk 0x400UL 749 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Pos 11UL 750 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_USE_RADJ_Msk 0x800UL 751 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Pos 12UL 752 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_RADJ_Msk 0x7000UL 753 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Pos 16UL 754 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_OUTEN_Msk 0x10000UL 755 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Pos 17UL 756 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_CTL_POLARITY_Msk 0x20000UL 757 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Pos 18UL 758 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_INEN_Msk 0x40000UL 759 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Pos 19UL 760 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_POLARITY_Msk 0x80000UL 761 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Pos 20UL 762 #define SRSS_PWR_REGHC_CTL_REGHC_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 763 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Pos 30UL 764 #define SRSS_PWR_REGHC_CTL_REGHC_TRANS_USE_OCD_Msk 0x40000000UL 765 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Pos 31UL 766 #define SRSS_PWR_REGHC_CTL_REGHC_CONFIGURED_Msk 0x80000000UL 767 /* SRSS.PWR_REGHC_STATUS */ 768 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Pos 0UL 769 #define SRSS_PWR_REGHC_STATUS_REGHC_ENABLED_Msk 0x1UL 770 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Pos 1UL 771 #define SRSS_PWR_REGHC_STATUS_REGHC_OCD_OK_Msk 0x2UL 772 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Pos 2UL 773 #define SRSS_PWR_REGHC_STATUS_REGHC_CKT_OK_Msk 0x4UL 774 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Pos 8UL 775 #define SRSS_PWR_REGHC_STATUS_REGHC_UV_OUT_Msk 0x100UL 776 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Pos 9UL 777 #define SRSS_PWR_REGHC_STATUS_REGHC_OV_OUT_Msk 0x200UL 778 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Pos 12UL 779 #define SRSS_PWR_REGHC_STATUS_REGHC_PMIC_STATUS_OK_Msk 0x1000UL 780 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Pos 31UL 781 #define SRSS_PWR_REGHC_STATUS_REGHC_SEQ_BUSY_Msk 0x80000000UL 782 /* SRSS.PWR_REGHC_CTL2 */ 783 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Pos 0UL 784 #define SRSS_PWR_REGHC_CTL2_REGHC_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 785 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Pos 31UL 786 #define SRSS_PWR_REGHC_CTL2_REGHC_EN_Msk 0x80000000UL 787 /* SRSS.PWR_REGHC_CTL4 */ 788 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Pos 30UL 789 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_VADJ_DIS_Msk 0x40000000UL 790 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Pos 31UL 791 #define SRSS_PWR_REGHC_CTL4_REGHC_PMIC_DPSLP_Msk 0x80000000UL 792 /* SRSS.PWR_HIB_DATA */ 793 #define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL 794 #define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 795 /* SRSS.PWR_PMIC_CTL */ 796 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Pos 2UL 797 #define SRSS_PWR_PMIC_CTL_PMIC_VREF_Msk 0xCUL 798 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Pos 4UL 799 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_Msk 0x1F0UL 800 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Pos 10UL 801 #define SRSS_PWR_PMIC_CTL_PMIC_USE_LINREG_Msk 0x400UL 802 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Pos 15UL 803 #define SRSS_PWR_PMIC_CTL_PMIC_VADJ_BUF_EN_Msk 0x8000UL 804 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Pos 16UL 805 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_OUTEN_Msk 0x10000UL 806 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Pos 17UL 807 #define SRSS_PWR_PMIC_CTL_PMIC_CTL_POLARITY_Msk 0x20000UL 808 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Pos 18UL 809 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_INEN_Msk 0x40000UL 810 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Pos 19UL 811 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_POLARITY_Msk 0x80000UL 812 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Pos 20UL 813 #define SRSS_PWR_PMIC_CTL_PMIC_STATUS_WAIT_Msk 0x3FF00000UL 814 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Pos 31UL 815 #define SRSS_PWR_PMIC_CTL_PMIC_CONFIGURED_Msk 0x80000000UL 816 /* SRSS.PWR_PMIC_STATUS */ 817 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Pos 0UL 818 #define SRSS_PWR_PMIC_STATUS_PMIC_ENABLED_Msk 0x1UL 819 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Pos 12UL 820 #define SRSS_PWR_PMIC_STATUS_PMIC_STATUS_OK_Msk 0x1000UL 821 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Pos 31UL 822 #define SRSS_PWR_PMIC_STATUS_PMIC_SEQ_BUSY_Msk 0x80000000UL 823 /* SRSS.PWR_PMIC_CTL2 */ 824 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Pos 0UL 825 #define SRSS_PWR_PMIC_CTL2_PMIC_STATUS_TIMEOUT_Msk 0xFFUL 826 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Pos 31UL 827 #define SRSS_PWR_PMIC_CTL2_PMIC_EN_Msk 0x80000000UL 828 /* SRSS.PWR_PMIC_CTL4 */ 829 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Pos 30UL 830 #define SRSS_PWR_PMIC_CTL4_PMIC_VADJ_DIS_Msk 0x40000000UL 831 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Pos 31UL 832 #define SRSS_PWR_PMIC_CTL4_PMIC_DPSLP_Msk 0x80000000UL 833 /* SRSS.CLK_PATH_SELECT */ 834 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 835 #define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 836 /* SRSS.CLK_ROOT_SELECT */ 837 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 838 #define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 839 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 840 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 841 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Pos 8UL 842 #define SRSS_CLK_ROOT_SELECT_DIRECT_MUX_Msk 0x100UL 843 #define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL 844 #define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 845 /* SRSS.CLK_SELECT */ 846 #define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL 847 #define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x7UL 848 #define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL 849 #define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 850 #define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL 851 #define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 852 #define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL 853 #define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 854 /* SRSS.CLK_TIMER_CTL */ 855 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL 856 #define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL 857 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL 858 #define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL 859 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL 860 #define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL 861 #define SRSS_CLK_TIMER_CTL_ENABLE_Pos 31UL 862 #define SRSS_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL 863 /* SRSS.CLK_ILO0_CONFIG */ 864 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 0UL 865 #define SRSS_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 0x1UL 866 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Pos 30UL 867 #define SRSS_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Msk 0x40000000UL 868 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Pos 31UL 869 #define SRSS_CLK_ILO0_CONFIG_ENABLE_Msk 0x80000000UL 870 /* SRSS.CLK_ILO1_CONFIG */ 871 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Pos 30UL 872 #define SRSS_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Msk 0x40000000UL 873 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Pos 31UL 874 #define SRSS_CLK_ILO1_CONFIG_ENABLE_Msk 0x80000000UL 875 /* SRSS.CLK_IMO_CONFIG */ 876 #define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL 877 #define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 878 /* SRSS.CLK_ECO_CONFIG */ 879 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 880 #define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 881 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 27UL 882 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 0x8000000UL 883 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 28UL 884 #define SRSS_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 0x10000000UL 885 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 886 #define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 887 /* SRSS.CLK_ECO_PRESCALE */ 888 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 0UL 889 #define SRSS_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 0x1UL 890 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 8UL 891 #define SRSS_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 0xFF00UL 892 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 16UL 893 #define SRSS_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 0x3FF0000UL 894 /* SRSS.CLK_ECO_STATUS */ 895 #define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL 896 #define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 897 #define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL 898 #define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 899 /* SRSS.CLK_PILO_CONFIG */ 900 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL 901 #define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL 902 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL 903 #define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL 904 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL 905 #define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL 906 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 907 #define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 908 /* SRSS.CLK_FLL_CONFIG */ 909 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 910 #define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 911 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 912 #define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 913 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 914 #define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 915 /* SRSS.CLK_FLL_CONFIG2 */ 916 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 917 #define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 918 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 919 #define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0xFF0000UL 920 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Pos 24UL 921 #define SRSS_CLK_FLL_CONFIG2_UPDATE_TOL_Msk 0xFF000000UL 922 /* SRSS.CLK_FLL_CONFIG3 */ 923 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 924 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 925 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 926 #define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 927 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 928 #define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 929 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 930 #define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 931 /* SRSS.CLK_FLL_CONFIG4 */ 932 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 933 #define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 934 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 935 #define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 936 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 937 #define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 938 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 939 #define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 940 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 941 #define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 942 /* SRSS.CLK_FLL_STATUS */ 943 #define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL 944 #define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 945 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 946 #define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 947 #define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL 948 #define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 949 /* SRSS.CLK_ECO_CONFIG2 */ 950 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Pos 0UL 951 #define SRSS_CLK_ECO_CONFIG2_WDTRIM_Msk 0x7UL 952 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Pos 4UL 953 #define SRSS_CLK_ECO_CONFIG2_ATRIM_Msk 0xF0UL 954 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Pos 8UL 955 #define SRSS_CLK_ECO_CONFIG2_FTRIM_Msk 0x300UL 956 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Pos 10UL 957 #define SRSS_CLK_ECO_CONFIG2_RTRIM_Msk 0xC00UL 958 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Pos 12UL 959 #define SRSS_CLK_ECO_CONFIG2_GTRIM_Msk 0x7000UL 960 /* SRSS.CLK_PLL_CONFIG */ 961 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 962 #define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 963 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 964 #define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 965 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 966 #define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 967 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Pos 25UL 968 #define SRSS_CLK_PLL_CONFIG_LOCK_DELAY_Msk 0x6000000UL 969 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 970 #define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 971 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 972 #define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 973 #define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL 974 #define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 975 /* SRSS.CLK_PLL_STATUS */ 976 #define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL 977 #define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 978 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 979 #define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 980 /* SRSS.CSV_REF_SEL */ 981 #define SRSS_CSV_REF_SEL_REF_MUX_Pos 0UL 982 #define SRSS_CSV_REF_SEL_REF_MUX_Msk 0x7UL 983 /* SRSS.RES_CAUSE */ 984 #define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL 985 #define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL 986 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 987 #define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 988 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 989 #define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 990 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Pos 3UL 991 #define SRSS_RES_CAUSE_RESET_TC_DBGRESET_Msk 0x8UL 992 #define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL 993 #define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL 994 #define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL 995 #define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 996 #define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL 997 #define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 998 #define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL 999 #define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 1000 #define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL 1001 #define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 1002 #define SRSS_RES_CAUSE_RESET_XRES_Pos 16UL 1003 #define SRSS_RES_CAUSE_RESET_XRES_Msk 0x10000UL 1004 #define SRSS_RES_CAUSE_RESET_BODVDDD_Pos 17UL 1005 #define SRSS_RES_CAUSE_RESET_BODVDDD_Msk 0x20000UL 1006 #define SRSS_RES_CAUSE_RESET_BODVDDA_Pos 18UL 1007 #define SRSS_RES_CAUSE_RESET_BODVDDA_Msk 0x40000UL 1008 #define SRSS_RES_CAUSE_RESET_BODVCCD_Pos 19UL 1009 #define SRSS_RES_CAUSE_RESET_BODVCCD_Msk 0x80000UL 1010 #define SRSS_RES_CAUSE_RESET_OVDVDDD_Pos 20UL 1011 #define SRSS_RES_CAUSE_RESET_OVDVDDD_Msk 0x100000UL 1012 #define SRSS_RES_CAUSE_RESET_OVDVDDA_Pos 21UL 1013 #define SRSS_RES_CAUSE_RESET_OVDVDDA_Msk 0x200000UL 1014 #define SRSS_RES_CAUSE_RESET_OVDVCCD_Pos 22UL 1015 #define SRSS_RES_CAUSE_RESET_OVDVCCD_Msk 0x400000UL 1016 #define SRSS_RES_CAUSE_RESET_OCD_ACT_LINREG_Pos 23UL 1017 #define SRSS_RES_CAUSE_RESET_OCD_ACT_LINREG_Msk 0x800000UL 1018 #define SRSS_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Pos 24UL 1019 #define SRSS_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Msk 0x1000000UL 1020 #define SRSS_RES_CAUSE_RESET_OCD_REGHC_Pos 25UL 1021 #define SRSS_RES_CAUSE_RESET_OCD_REGHC_Msk 0x2000000UL 1022 #define SRSS_RES_CAUSE_RESET_PMIC_Pos 26UL 1023 #define SRSS_RES_CAUSE_RESET_PMIC_Msk 0x4000000UL 1024 #define SRSS_RES_CAUSE_RESET_PXRES_Pos 28UL 1025 #define SRSS_RES_CAUSE_RESET_PXRES_Msk 0x10000000UL 1026 #define SRSS_RES_CAUSE_RESET_STRUCT_XRES_Pos 29UL 1027 #define SRSS_RES_CAUSE_RESET_STRUCT_XRES_Msk 0x20000000UL 1028 #define SRSS_RES_CAUSE_RESET_PORVDDD_Pos 30UL 1029 #define SRSS_RES_CAUSE_RESET_PORVDDD_Msk 0x40000000UL 1030 /* SRSS.RES_CAUSE2 */ 1031 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Pos 0UL 1032 #define SRSS_RES_CAUSE2_RESET_CSV_HF_Msk 0xFFFFUL 1033 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Pos 16UL 1034 #define SRSS_RES_CAUSE2_RESET_CSV_REF_Msk 0x10000UL 1035 /* SRSS.CLK_TRIM_ILO0_CTL */ 1036 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Pos 0UL 1037 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Msk 0x3FUL 1038 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Pos 8UL 1039 #define SRSS_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Msk 0xF00UL 1040 /* SRSS.PWR_TRIM_PWRSYS_CTL */ 1041 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL 1042 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL 1043 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL 1044 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL 1045 /* SRSS.CLK_TRIM_PILO_CTL */ 1046 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL 1047 #define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL 1048 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL 1049 #define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL 1050 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL 1051 #define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL 1052 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL 1053 #define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL 1054 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL 1055 #define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL 1056 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL 1057 #define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL 1058 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL 1059 #define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL 1060 /* SRSS.CLK_TRIM_PILO_CTL2 */ 1061 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL 1062 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL 1063 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL 1064 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL 1065 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL 1066 #define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL 1067 /* SRSS.CLK_TRIM_PILO_CTL3 */ 1068 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL 1069 #define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL 1070 /* SRSS.CLK_TRIM_ILO1_CTL */ 1071 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Pos 0UL 1072 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Msk 0x3FUL 1073 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Pos 8UL 1074 #define SRSS_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Msk 0xF00UL 1075 1076 1077 #endif /* _CYIP_SRSS_V3_H_ */ 1078 1079 1080 /* [] END OF FILE */ 1081
