1 /***************************************************************************//**
2 * \file cyip_icache.h
3 *
4 * \brief
5 * ICACHE IP definitions
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYIP_ICACHE_H_
28 #define _CYIP_ICACHE_H_
29 
30 #include "cyip_headers.h"
31 
32 /*******************************************************************************
33 *                                    ICACHE
34 *******************************************************************************/
35 
36 #define ICACHE_SECTION_SIZE                     0x00001000UL
37 
38 /**
39   * \brief CM33_0/1 CA APB interface (ICACHE)
40   */
41 typedef struct {
42   __IOM uint32_t CTL;                           /*!< 0x00000000 Cache control */
43    __IM uint32_t RESERVED;
44   __IOM uint32_t CMD;                           /*!< 0x00000008 Cache command */
45    __IM uint32_t RESERVED1[29];
46    __IM uint32_t STATUS0;                       /*!< 0x00000080 Cache status 0 */
47    __IM uint32_t STATUS1;                       /*!< 0x00000084 Cache status 1 */
48    __IM uint32_t STATUS2;                       /*!< 0x00000088 Cache status 2 */
49    __IM uint32_t RESERVED2[29];
50   __IOM uint32_t ECC_CTL;                       /*!< 0x00000100 ECC control */
51 } ICACHE_Type;                                  /*!< Size = 260 (0x104) */
52 
53 
54 /* ICACHE.CTL */
55 #define ICACHE_CTL_ECC_EN_Pos                   0UL
56 #define ICACHE_CTL_ECC_EN_Msk                   0x1UL
57 #define ICACHE_CTL_ECC_INJ_EN_Pos               1UL
58 #define ICACHE_CTL_ECC_INJ_EN_Msk               0x2UL
59 #define ICACHE_CTL_WAY_Pos                      16UL
60 #define ICACHE_CTL_WAY_Msk                      0x30000UL
61 #define ICACHE_CTL_SET_ADDR_Pos                 24UL
62 #define ICACHE_CTL_SET_ADDR_Msk                 0x1F000000UL
63 #define ICACHE_CTL_PREF_EN_Pos                  30UL
64 #define ICACHE_CTL_PREF_EN_Msk                  0x40000000UL
65 #define ICACHE_CTL_CA_EN_Pos                    31UL
66 #define ICACHE_CTL_CA_EN_Msk                    0x80000000UL
67 /* ICACHE.CMD */
68 #define ICACHE_CMD_INV_Pos                      0UL
69 #define ICACHE_CMD_INV_Msk                      0x1UL
70 #define ICACHE_CMD_BUFF_INV_Pos                 1UL
71 #define ICACHE_CMD_BUFF_INV_Msk                 0x2UL
72 /* ICACHE.STATUS0 */
73 #define ICACHE_STATUS0_VALID32_Pos              0UL
74 #define ICACHE_STATUS0_VALID32_Msk              0xFFFFFFFFUL
75 /* ICACHE.STATUS1 */
76 #define ICACHE_STATUS1_TAG_Pos                  0UL
77 #define ICACHE_STATUS1_TAG_Msk                  0xFFFFFFFFUL
78 /* ICACHE.STATUS2 */
79 #define ICACHE_STATUS2_LRU_Pos                  0UL
80 #define ICACHE_STATUS2_LRU_Msk                  0x3FUL
81 /* ICACHE.ECC_CTL */
82 #define ICACHE_ECC_CTL_WORD_ADDR_Pos            0UL
83 #define ICACHE_ECC_CTL_WORD_ADDR_Msk            0xFFFFFFUL
84 #define ICACHE_ECC_CTL_PARITY_Pos               24UL
85 #define ICACHE_ECC_CTL_PARITY_Msk               0x7F000000UL
86 
87 
88 #endif /* _CYIP_ICACHE_H_ */
89 
90 
91 /* [] END OF FILE */
92