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Searched refs:CY_SYSLIB_DIV_ROUND (Results 1 – 13 of 13) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_pra.c297 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT), 4U)].writeMask = (CY_GPIO_OUT_… in Cy_PRA_InitGpioPort()
298 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_CLR), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
299 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_SET), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
300 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, OUT_INV), 4U)].writeMask = (CY_GPIO_… in Cy_PRA_InitGpioPort()
301 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, IN), 4U)].writeMask = (CY_GPIO_IN_MA… in Cy_PRA_InitGpioPort()
302 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, INTR), 4U)].writeMask = (CY_GPIO_INT… in Cy_PRA_InitGpioPort()
303 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, INTR_MASK), 4U)].writeMask = (CY_GPI… in Cy_PRA_InitGpioPort()
304 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, INTR_MASKED), 4U)].writeMask = (CY_G… in Cy_PRA_InitGpioPort()
305 …regPolicy[index + CY_SYSLIB_DIV_ROUND(offsetof(GPIO_PRT_Type, INTR_SET), 4U)].writeMask = (CY_GPIO… in Cy_PRA_InitGpioPort()
308 …regPolicy[index + CY_SYSLIB_DIV_ROUND((uint16_t)(cy_device->gpioPrtIntrCfgOffset), 4U)].writeMask … in Cy_PRA_InitGpioPort()
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Dcy_sysclk.c294 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkSlowGetFrequency()
555 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkPeriGetFrequency()
593 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkFastGetFrequency()
817 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkMfGetFrequency()
1200 uint32_t freqKhz = CY_SYSLIB_DIV_ROUND(freq, 1000UL); in Cy_SysClk_EcoConfigure()
1202 uint32_t maxAmpl = CY_SYSLIB_DIV_ROUND((159155UL * /* 5 * 100000 / PI */ in Cy_SysClk_EcoConfigure()
1203 cy_sqrt(CY_SYSLIB_DIV_ROUND(2000000UL * driveLevel, esr))), /* Scaled by 2 */ in Cy_SysClk_EcoConfigure()
1207 uint32_t ampSect = (CY_SYSLIB_DIV_ROUND(cSum * cSum * in Cy_SysClk_EcoConfigure()
1208 … CY_SYSLIB_DIV_ROUND(freqKhz * freqKhz, 126651UL), 100UL) * esr)/ 900000UL; in Cy_SysClk_EcoConfigure()
1521 …uint32_t ki_p = (uint32_t)CY_SYSLIB_DIV_ROUND(850ULL * CY_SYSCLK_FLL_INT_COEF * inputFreq, (uint64… in Cy_SysClk_FllConfigure()
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Dcy_seglcd.c395 …uint32_t locSubfr = CY_SYSLIB_DIV_ROUND((CY_SYSLIB_DIV_ROUND(config->clkFreq, config->frRate * 4UL… in Cy_SegLCD_Init()
396 …uint32_t locDead = CY_SYSLIB_DIV_ROUND(CY_SYSLIB_DIV_ROUND(config->clkFreq * ((uint32_t)(100UL - (… in Cy_SegLCD_Init()
Dcy_sysclk_v2.c433 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkSlowGetFrequency()
462 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkMemGetFrequency()
586 return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); in Cy_SysClk_ClkPeriGetFrequency()
792 return (uint32_t) CY_SYSLIB_DIV_ROUND(locFreq, (uint64_t)locDiv); in Cy_SysClk_ClkFastSrcGetFrequency()
930 return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); in Cy_SysClk_ClkHfGetFrequency()
933 return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); in Cy_SysClk_ClkHfGetFrequency()
1103 return (CY_SYSLIB_DIV_ROUND(mfFreq, mfDiv)); in Cy_SysClk_ClkMfGetFrequency()
1997 uint32_t maxAmpl = CY_SYSLIB_DIV_ROUND((159155UL * /* 5 * 100000 / PI */ in Cy_SysClk_EcoConfigure()
1998 cy_sqrt(CY_SYSLIB_DIV_ROUND(2000000UL * driveLevel, esr))), /* Scaled by 2 */ in Cy_SysClk_EcoConfigure()
1999 … (CY_SYSLIB_DIV_ROUND(freq, 1000UL)/* KHz */ * cSum)); /* The result is scaled by 10^3 */ in Cy_SysClk_EcoConfigure()
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Dcy_sar.c247 …defaultGain = (int32_t)(uint16_t)CY_SYSLIB_DIV_ROUND((uint32_t)CY_SAR_WRK_MAX_12BIT * (uint32_t)CY… in Cy_SAR_Init()
Dcy_pra_cfg.c800 …retFreq = CY_SYSLIB_DIV_ROUND(Cy_SysClk_ClkPathGetFrequency((uint32_t) devConfig->hf0Source),(1UL … in Cy_PRA_GetHF0FreqHz()
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/
Dcy_adcmic.h405 #define CY_ADCMIC_DC_OFFSET (-((int16_t)CY_SYSLIB_DIV_ROUND(CY_ADCMIC_DC_FS, CY_ADCMIC_DC_LO)))
407 #define CY_ADCMIC_DC_HI_CNT ((int16_t)CY_SYSLIB_DIV_ROUND(CY_ADCMIC_DC_FS * CY_ADCMIC_DC_HI, 10…
411 #define CY_ADCMIC_DC_3_6_GAIN ((int16_t)CY_SYSLIB_DIV_ROUND(CY_ADCMIC_DC_FS_CNT, 36U))
413 #define CY_ADCMIC_DC_1_8_GAIN ((int16_t)CY_SYSLIB_DIV_ROUND(CY_ADCMIC_DC_FS_CNT, 18U))
Dcy_sysclk.h7359 #define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b)))
/hal_infineon-3.5.0/core-lib/include/
Dcy_utils.h395 #define CY_SYSLIB_DIV_ROUND(a, b) (((a) + ((b) / 2U)) / (b)) macro
/hal_infineon-3.5.0/core-lib/
DREADME.md37 …* `CY_SYSLIB_DIV_ROUND`: Calculates a / b with rounding to the nearest integer, a and b must have …
DRELEASE.md33 …* CY_SYSLIB_DIV_ROUND: Calculates a / b with rounding to the nearest integer, a and b must have th…
/hal_infineon-3.5.0/mtb-hal-cat1/source/
Dcyhal_clock.c1478 …uint32_t fll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_enabled_fll()
1527 …uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_frequency_fll()
1647 …uint32_t pll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv… in _cyhal_clock_set_enabled_pll()
1726 …uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv… in _cyhal_clock_set_frequency_pll()
Dcyhal_usb_dev.c275 freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)pll_config.feedbackDiv), in _cyhal_usb_dev_get_pll_freq()