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Searched refs:CY_SYSCLK_CLKHF_IN_CLKPATH1 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c704 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ in Cy_PRA_GetInputSourceFreq()
945 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ in Cy_PRA_GetInputSourceClock()
1608 case (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1: /* CLK_PATH1 */ in Cy_PRA_ValidateClkPath()
2704 sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH1); in Cy_PRA_SystemConfig()
Dcy_pra.c2161 if (structCpy.hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH1) in Cy_PRA_ProcessCmd()
2359 …if ((structCpy.hf0Source == CY_SYSCLK_CLKHF_IN_CLKPATH1) || (structCpy.hf0Source == CY_SYSCLK_CLKH… in Cy_PRA_ProcessCmd()
3181 …sysClkStatus = Cy_SysClk_ClkPathSetSource((uint32_t) CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPAT… in Cy_PRA_ClocksReset()
3192 … sysClkStatus = Cy_SysClk_ClkHfSetSource(CY_PRA_CLKHF_0, CY_SYSCLK_CLKHF_IN_CLKPATH1); in Cy_PRA_ClocksReset()
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h5193 CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U, /**< clkHf input is Clock Path 1 */ enumerator