1 /***************************************************************************//** 2 * \file cy_flash_srom.h 3 * \version 3.70 4 * 5 * \brief 6 * Provides declaration of API controlling the SROM APIs. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2021, Cypress Semiconductor Corporation. All rights reserved. 11 * You may use this file only in accordance with the license, terms, conditions, 12 * disclaimers, and limitations in the end user license agreement accompanying 13 * the software package with which this file was provided. 14 *******************************************************************************/ 15 16 /* This driver is created by referring SROM BROS (002-03298) rev 0W. */ 17 /* Please note SROM API is subject to update in the future. */ 18 19 #if !defined(CY_FLAH_SROM_H) 20 #define CY_FLAH_SROM_H 21 #include "cy_device.h" 22 #if defined (CY_IP_M7CPUSS) 23 #include "cy_syslib.h" 24 #include "cy_ipc_drv.h" 25 #include "cy_sysint.h" 26 27 /** \cond INTERNAL */ 28 typedef void (*cy_srom_handler)(void); 29 30 #define CY_SROM_DR_IPC_NOTIFY_STRUCT (0x1UL) 31 #define CY_SROM_DR_IPC_INTR_STRUCT (0x2UL) 32 #define CY_SROM_DR_IPC_INTR_NO (cpuss_interrupts_ipc_2_IRQn) 33 34 typedef enum 35 { 36 CY_SROM_OP_SILICON_ID = (0x00UL), 37 CY_SROM_OP_READ_FUSE_BYTE = (0x03UL), 38 CY_SROM_OP_READ_UNIQUE_ID = (0x1FUL), 39 CY_SROM_OP_SWITCH_REGULATOR = (0x11UL), 40 CY_SROM_OP_CONFIGURE_REGULATOR = (0x15UL), 41 CY_SROM_OP_FLASH_PROGRAM_ROW = (0x06UL), 42 CY_SROM_OP_FLASH_CHECKSUM = (0x0BUL), 43 CY_SROM_OP_FLASH_HASH = (0x0DUL), 44 CY_SROM_OP_FLASH_ERASE_ALL = (0x0AUL), 45 CY_SROM_OP_FLASH_ERASE_SECTOR = (0x14UL), 46 CY_SROM_OP_FLASH_FM_STATUS = (0x07UL), 47 CY_SROM_OP_FLASH_FM_INTR = (0x08UL), 48 CY_SROM_OP_FLASH_ERASE_SUSPEND = (0x22UL), 49 CY_SROM_OP_FLASH_ERASE_RESUME = (0x23UL), 50 CY_SROM_OP_FLASH_BLANK_CHECK = (0x2AUL), 51 CY_SROM_OP_FLASH_PROGRAM_WFLASH = (0x30UL), 52 } cy_en_srom_api_opcode_t; 53 54 typedef enum 55 { 56 CY_SROM_STATUS_SUCCESS = (0x00000000UL), // SROM PASS. Note this is driver specific value. 57 CY_SROM_STATUS_INVALID = (0x0FFFFFFFUL), // Status Value invalid. Note this is driver specific value. 58 CY_SROM_STATUS_INVALID_PROTECTION = (int32_t)(0xF0000001UL), // Invalid Protection state. This API is not available in current protection state. 59 CY_SROM_STATUS_INVALID_FUSE_ADDR = (int32_t)(0xF0000002UL), // Invalid efuse address.This status is returned when BlowFuseBit is called on out-of-bound eFuse. 60 CY_SROM_STATUS_INVALID_FM_PL = (int32_t)(0xF0000003UL), // Invalid FLASH page latch address 61 CY_SROM_STATUS_INVALID_FLASH_ADDR = (int32_t)(0xF0000004UL), // Wrong or out of bound FLASH address 62 CY_SROM_STATUS_NVM_PROTECTED = (int32_t)(0xF0000005UL), // Non-Volatile Memory(FLASH or eFuse) bytes are read/write protected via protection units.Previously called as STATUS_ROW_PROTECTED. 63 CY_SROM_STATUS_INVALID_IPC_STRUCT = (int32_t)(0xF0000006UL), // Client did not use its reserved IPC structure for invoking system call. 64 CY_SROM_STATUS_ADDR_PROTECTED = (int32_t)(0xF0000008UL), // Returned by all APIs when client doesn't have access to region it is using for passing arguments. 65 CY_SROM_STAUTS_CHECKSUM_NON_ZERO = (int32_t)(0xF000000AUL), // Checksum of FLASH resulted in non-zero 66 CY_SROM_STATUS_INVALID_OPCODE = (int32_t)(0xF000000BUL), // The opcode is not a valid API opcode. 67 CY_SROM_STATUS_INVALID_ADDR_RANGE = (int32_t)(0xF000000EUL), // Returned when ConfigureRegionBulk is called with start address greater than end address or EraseAll called in dual bank mode for SONOS. 68 CY_SROM_STATUS_INVALID_ARGUMENTS = (int32_t)(0xF000000FUL), // Returned when invalid arguments are passed to the API. For e.g calling Silicon ID API with ID type of 0x5. 69 CY_SROM_STATUS_BOOT_FLASH_AUTH_FAIL = (int32_t)(0xF0000010UL), // HASH stored in efuse does not match to computed HASH 70 CY_SROM_STATUS_TEST_KEY_DFT_EN = (int32_t)(0xF0000011UL), // Indicates that TEST_KEY_DFT_EN was set during boot up 71 CY_SROM_STATUS_TEST_KEY_SAFE_MODE = (int32_t)(0xF0000012UL), // Indicates that TST_KEY_SAFE_MODE was set during boot up 72 CY_SROM_STATUS_INVALID_ARGUMENT_LOCATION = (int32_t)(0xF0000013UL), // User has provided arguments in region other than available user SRAM or not 32-bit 73 CY_SROM_STATUS_NON_NMI_ENTRY = (int32_t)(0xF0000014UL), // NMI Handler function was executed under non-NMI mode. 74 CY_SROM_STATUS_INVALID_TRIM_LEN = (int32_t)(0xF0000015UL), // General trims length was found to be less than 2 75 CY_SROM_STATUS_INVALID_HASH_ZEROS = (int32_t)(0xF0000017UL), // Number of zeros in the HASH computed by ROM boot & number of zeros stored in eFuse don't match. 76 CY_SROM_STATUS_INVALID_TOC1 = (int32_t)(0xF0000018UL), // Table of contents 1fs CRC check failed or /and magic number is not present 77 CY_SROM_STATUS_CM4_NOT_IN_DEEPSLEEP = (int32_t)(0xF0000019UL), // CM4 only reset requested by SoftReset when CM4 is not in deepsleep. 78 CY_SROM_STATUS_ALT_FLASH_BOOT_AUTH_FAIL = (int32_t)(0xF000001AUL), // Returned during secure boot if SFLASH bank 1 authentication check fails. 79 CY_SROM_STATUS_INVALID_TOC2 = (int32_t)(0xF0000020UL), // Table of contents2fs CRC check failed or /and magic number is not present 80 CY_SROM_STATUS_SR_ILLEGAL_OP = (int32_t)(0xF0000021UL), // Bulk operation requested on SFLASH region. 81 CY_SROM_STATUS_OPERATION_NOT_ALLOWED = (int32_t)(0xF0000022UL), // Returned when flash embedded operations are invoked during margin mode operation. 82 CY_SROM_STATUS_MM_ERROR = (int32_t)(0xF0000030UL), // Returned by FlashMarginScreenArray SROM API when there is a margin mode failure 83 CY_SROM_STATUS_INVALID_CY_ASSET_HASH = (int32_t)(0xF0000053UL), // Calculated CY_ASSET_HASH doesn't match to the one stored in efuse unused 0xF0000054 84 CY_SROM_STATUS_ENABLE_FB_CHECK_BIT_NOT_BLOWN = (int32_t)(0xF0000055UL), // Returned by TransitionToSecure if he ENABLE_FB_CHECK_IN_NORMAL_is not blown 85 CY_SROM_STATUS_CY_ASSET_HASH_MAX_OBJECTS = (int32_t)(0xF0000056UL), // If the number of the CY_ASSET_HASH exceeds maximum value 86 CY_SROM_STATUS_INVALID_FB_CHECK_EFUSE = (int32_t)(0xF00000ACUL), // The ENABLE_FB_CHECK_IN_NORMAL fuse is corrupted 87 CY_SROM_STATUS_CALIBRATE_FAILED = (int32_t)(0xF0000080UL), // FLASH trim hunt failed for SONOS. For eCT magic number was not found in TOC1 88 CY_SROM_STATUS_TURBON_FAILED = (int32_t)(0xF0000081UL), // turbo is low during FmCalibrate 89 CY_SROM_STATUS_ISOLATED_FAILED = (int32_t)(0xF0000082UL), // Isolate is high during FmCalibrate 90 CY_SROM_STATUS_ERROR_CORRECTION_FAILED = (int32_t)(0xF0000086UL), // FLASH APIfs were not able to retrieve majority data when fetching HV parameters 91 CY_SROM_STATUS_SECTOR_SUSPEND = (int32_t)(0xF0000091UL), // Returned when Program operation is called on sector which is suspended from erase. 92 CY_SROM_STATUS_NO_ERASE_SUSPEND = (int32_t)(0xF0000092UL), // Returned when EraseResume is called when no sector is suspended from erase. 93 CY_SROM_STATUS_API_NOT_APPROVED = (int32_t)(0xF0000095UL), // Returned by API when the requested system call is not approved by TEE 94 CY_SROM_STATUS_POR_NATIVE = (int32_t)(0xF00000A0UL), // Returned when FUR download fails with POR_NATIVE=1. 95 CY_SROM_STATUS_FUR_ECC_ERROR = (int32_t)(0xF00000A1UL), // Returned when FUR download fails due to ECC error. 96 CY_SROM_STATUS_IRAM_ECC_ERROR = (int32_t)(0xF00000A2UL), // Returned when IRAM download fails due to ECC error. 97 CY_SROM_STATUS_FM_ECC_ERROR = (int32_t)(0xF00000A3UL), // Returned when FM fails due to ECC error. 98 CY_SROM_STATUS_FLASH_NOT_ERASED = (int32_t)(0xF00000A4UL), // Returned when ProgramRow is invoked on unerased cells or blank check fails. 99 CY_SROM_STATUS_NO_ERASE_ONGOING = (int32_t)(0xF00000A5UL), // Returned by EraseSuspend when called with no ongoing erase operation 100 CY_SROM_STATUS_ACTIVE_ERASE = (int32_t)(0xF00000A6UL), // Returned by ProgramRow when active erase operation is going on. 101 CY_SROM_STATUS_EMB_FAIL = (int32_t)(0xF00000A7UL), // Returned by FLASH SROM APIs when the embedded operation fails. 102 CY_SROM_STAUTS_INVALID_DATA_WIDTH = (int32_t)(0xF00000A8UL), // Returned by ProgramRow API if invalid program width option is provided 103 CY_SROM_STATUS_EMB_ACTIVE = (int32_t)(0xF00000A9UL), // Returned by WriteRow when invoked during an active embedded operation. 104 CY_SROM_STATUS_FLASH_SAFTEY_ENABLED = (int32_t)(0xF00000AAUL), // Returned by FLASH program/erase APIs when writes are disabled in safety register. 105 CY_SROM_STATUS_INVALID_BANK_MODE = (int32_t)(0xF00000ABUL), // Returned by WriteRow when invoked in dual bank mode. 106 CY_SROM_STATUS_INVALID_NUM_ENTRIES = (int32_t)(0xF00000B0UL), // Returned by WriteTOC2 when invalid number of entries are passed 107 CY_SROM_STATUS_INVALID_ACCESS_RESTRICTION = (int32_t)(0xF00000B1UL), // Returned when WriteNormalAccessRestrict is called to restrict less 108 CY_SROM_STATUS_INVALID_SFLASH_ADDR = (int32_t)(0xF00000B2UL), // Returned when WriteRow is called on invalid SFLASH rows in NORMAL state or TOC/patch entries are not in SFLASH 109 CY_SROM_STATUS_INVALID_UID = (int32_t)(0xF00000B3UL), // Returned by when invalid Unique ID is passed during RMA 110 CY_SROM_STATUS_INVALID_SIGN = (int32_t)(0xF00000B4UL), // Returned when invalid signature is found during RMA 111 CY_SROM_STATUS_INVALID_FACTORY_HASH = (int32_t)(0xF00000B5UL), // Returned when FACTORY_HASH1(in NORMAL1) or FACTORY_HASH2(in NORMAL2) does not match 112 CY_SROM_STATUS_INVALID_TOC1_HASH_OBJECT = (int32_t)(0xF00000B8UL), // Returned when more than 30(for PSOC6, 10 for Traveo II) HASH objects are indicated in TOC1 113 CY_SROM_STATUS_INVALID_TOC2_HASH_OBJECT = (int32_t)(0xF00000B9UL), // Returned when more than 30(for PSOC6, 10 for Traveo II) HASH objects are indicated in TOC2 114 CY_SROM_STATUS_INVALID_PUBLIC_KEY = (int32_t)(0xF00000BAUL), // Returned by TransitionRMA & OpenRMA when public key structure is invalid 115 CY_SROM_STATUS_SFLASH_BACKUP_ERASED = (int32_t)(0xF00000BBUL), // Returned by Sflash programming APIs when backup sector is in erased state. 116 CY_SROM_STATUS_INVALID_PU1_FLASH_WRITE_NR = (int32_t)(0xF00000BCUL), // Returned during boot when SWPU in SFLASH is more than expected 117 CY_SROM_STATUS_INVALID_PU1_FUSE_WRITE_NR = (int32_t)(0xF00000BDUL), // Returned during boot when SWPU in SFLASH is more than expected 118 CY_SROM_STATUS_INVALID_PU1_FUSE_READ_NR = (int32_t)(0xF00000BEUL), // Returned during boot when SWPU in SFLASH is more than expected 119 CY_SROM_STATUS_INVALID_PU2_FLASH_WRITE_NR = (int32_t)(0xF00000BFUL), // Returned during boot when SWPU in SFLASH is more than expected 120 CY_SROM_STATUS_INVALID_PU2_FUSE_WRITE_NR = (int32_t)(0xF00000C0UL), // Returned during boot when SWPU in SFLASH is more than expected 121 CY_SROM_STATUS_INVALID_PU2_FUSE_READ_NR = (int32_t)(0xF00000C1UL), // Returned during boot when SWPU in SFLASH is more than expected 122 CY_SROM_STATUS_INVALID_PU_ID = (int32_t)(0xF00000C2UL), // Returned by Read or WriteSWPU API when invalid ID is passed. 123 CY_SROM_STATUS_PU_PROTECTED = (int32_t)(0xF00000C3UL), // Returned by WriteSWPU API when client doesn't have access to update SWPU 124 CY_SROM_STATUS_PU_MISMATCH = (int32_t)(0xF00000C4UL), // Returned by WriteSWPU API when client doesn't providing matching SL_ADDR & SL_SIZE. 125 CY_SROM_STATUS_PU_READ_ECC_ERROR = (int32_t)(0xF00000C5UL), // Returned by ReadSWPU API if ECC error occurred during SRAM read operation. 126 CY_SROM_STATUS_PU_REJECTED = (int32_t)(0xF00000C6UL), // Returned by Read & WriteSWPU API if the IDfd PU was rejected during boot due to overlap or out-of-order region. 127 CY_SROM_STATUS_PENDING_ECC_ERROR = (int32_t)(0xF00000C7UL), // Returned by Read & Write SWPU APIs if there was a pending ECC error before performing SWPU operations 128 CY_SROM_STATUS_INVALID_LIFECYCLE_FUSE = (int32_t)(0xF00000C8UL), // Returned during boot if valid lifecycle fuse combinations are not read from eFuse. 129 CY_SROM_STATUS_FUSE_PGM_FAILED = (int32_t)(0xF00000CBUL), // Returned by BlowFuseBit API when read value from programmed fuse is 0 130 CY_SROM_STATUS_ARG_PROTECTED = (int32_t)(0xF00000CFUL), // User has provided arguments in protected region. 131 CY_SROM_STATUS_EFUSE_BOOTROW_NON_ZERO = (int32_t)(0xF00000D1UL), // Returned by TransitionToSort() in case if the bootrow is not zero in VIRGIN 132 CY_SROM_STATUS_SRAM_REPAIR_FAILED = (int32_t)(0xF00000D2UL), // Returned by Boot if SRAM BIHR repair operation fails 133 CY_SROM_STATUS_SRAM_REPAIR_FUSE_FAILED = (int32_t)(0xF00000D3UL), // Returned by Boot if SRAM repair fuse redundancy check fails 134 CY_SROM_STATUS_SFLASH_CORRUPTED = (int32_t)(0xF00000D5UL), // Returned when SFLASH markers are corrupted during boot. 135 CY_SROM_STATUS_MARKER_OVERFLOW = (int32_t)(0xF00000D6UL), // Returned by WriteRow when marker overflows by 2^32 times. 136 CY_SROM_STATUS_CM7_X_NOT_IN_DEEPSLEEP = (int32_t)(0xF00000D7UL), // Returned by SoftReset API when CM7 reset is requested with CM7 not being in deepsleep mode. 137 CY_SROM_STATUS_INVALID_LIFECYCLE = (int32_t)(0xF00000D8UL), // Operation is not supported in this LifeCycle (TVII products only) 138 CY_SROM_STATUS_INVALID_HASH_OBJECT_ADDRESS = (int32_t)(0xF00000DAUL), // Returned when TOC object StartAddr and EndAddr(TOC Object StartAddr+ TOC Object Size) are out of bound of SFLASH/OTP. 139 CY_SROM_STATUS_REGULATOR_MODE_MANUAL = (int32_t)(0xF00000E0UL), // Regulator is configured for gManualh mode 140 CY_SROM_STATUS_REGULATOR_SEQ_BUSY = (int32_t)(0xF00000E1UL), // Regulator is currently in transition. 141 CY_SROM_STATUS_REGULATOR_ALREADY_ENABLED = (int32_t)(0xF00000E2UL), // Regulator is already enabled 142 CY_SROM_STATUS_REGULATOR_NOT_CONFIGURED = (int32_t)(0xF00000E3UL), // Regulator is not configured with ConfigureRegulator() 143 CY_SROM_STATUS_REGULATOR_WRONG_CONFIGURATION = (int32_t)(0xF00000E4UL), // Returned by SwitchOverRegulators() in case when the syscall is called with different OpMode parameter then ConfigureRegulator(). 144 CY_SROM_STATUS_WRITE_DEVICE_KEYS_TRIVIAL_KEY = (int32_t)(0xF00000E5UL), // -TBD 145 CY_SROM_STATUS_WRITE_DEVICE_KEYS_NON_ZERO_KEYS = (int32_t)(0xF00000E6UL), // - TBD 146 CY_SROM_STATUS_WRITE_DEVICE_KEYS_WRONG_LIFE_CYCLE = (int32_t)(0xF00000E7UL), // - TBD 147 CY_SROM_STATUS_WRITE_DEVICE_KEYS_MISMATCHED_KEYS = (int32_t)(0xF00000E8UL), // - TBD 148 CY_SROM_STATUS_WRITE_DEVICE_KEYS_WRONG_EFUSE_ZEROS = (int32_t)(0xF00000E9UL), // - TBD 149 CY_SROM_STATUS_WRITE_DEVICE_KEYS_CORRUPTED_P_BITS = (int32_t)(0xF00000EAUL), // - TBD 150 CY_SROM_STATUS_ERROR_SYSCALL0 = (int32_t)(0xF00000EBUL), // - TBD 151 CY_SROM_STATUS_ERROR_SYSCALL1 = (int32_t)(0xF00000ECUL), // - TBD 152 CY_SROM_STATUS_ERROR_SYSCALL2 = (int32_t)(0xF00000EDUL), // - TBD 153 CY_SROM_STATUS_ERROR_SYSCALL3 = (int32_t)(0xF00000EEUL), // - TBD 154 CY_SROM_STATUS_ERROR_SYSCALL4 = (int32_t)(0xF00000EFUL), // - TBD 155 CY_SROM_STATUS_HARDFAULT_BOOT = (int32_t)(0xF00000F0UL), // Returned during boot if hard fault occurs during bootup 156 CY_SROM_STATUS_HARDFAULT_SYSCALL = (int32_t)(0xF00000F1UL), // Returned by system call if hard fault occurs in context of system calls 157 CY_SROM_STATUS_INVALID_PROG_PPU_ACCESS = (int32_t)(0xF4000000UL), // Returned when system call(PC1) doesn't have access to the programmable PPU it uses. The programmable PPU ID is returned in LSB. 158 CY_SROM_STATUS_INVALID_FIXED_PPU_ACCESS = (int32_t)(0xF5000000UL), // Returned when system call(PC1) doesn't have access to the fixed PPU it uses. The fixed PPU ID is returned in LSB. 159 CY_SROM_STATUS_BOOTROW_MMIO_MISMATCH = (int32_t)(0xF6000019UL), // Returned when bootrow fuse and MMIO doesn't match 160 CY_SROM_STATUS_BOOTROW_KEY_MISMATCH = (int32_t)(0xF6000029UL), // Returned when key in the bootrow is not 0x29 161 CY_SROM_STATUS_BOOTROW_TRIM_MISMATCH = (int32_t)(0xF6000039UL), // Returned when trim and trim inverse in bootrow are not equal 162 CY_SROM_STATUS_BOOTROW_FUSE_MISMATCH = (int32_t)(0xF6000049UL), // Returned when lifecycle fuses fail its redundancy check. 163 CY_SROM_STATUS_BOOTROW_INVALID_COMB = (int32_t)(0xF6000059UL), // Returned when invalid lifecycle fuse combinations are blown 164 CY_SROM_STATUS_HASH_FAILED = (int32_t)(0xF1000000UL), // Hash on SFLASH trims failed. The computed hash is ORfd with this status. 165 CY_SROM_STATUS_FUSE_ZERO_FAILED = (int32_t)(0xF2000000UL), // Number of zeroes stored in efuse does not match to computed number 166 CY_SROM_STATUS_BOOT_FAULT_MASK = (int32_t)(0xF3000000UL), // Returned during boot in IPC_STRUCT0.DATA1 if fault structure 0 valid bit is set. The LSBs will hold the fault ID information. 167 CY_SROM_CY_FB_ERROR_INVALID_APP_SIGN = (int32_t)(0xF1000100UL), // App signature validation failed. 168 CY_SROM_CY_FB_ERROR_INVALID_TOC = (int32_t)(0xF1000101UL), // Empty or Invalid TOC 169 CY_SROM_CY_FB_ERROR_INVALID_KEY = (int32_t)(0xF1000102UL), // Invalid Public Key 170 CY_SROM_CY_FB_ERROR_UNREACHABLE = (int32_t)(0xF1000103UL), // Unreachable Code 171 CY_SROM_CY_FB_ERROR_TOC_DATA_CLOCK = (int32_t)(0xF1000104UL), // TOC contains invalid CM0+ clock attribute. 172 CY_SROM_CY_FB_ERROR_TOC_DATA_DELAY = (int32_t)(0xF1000105UL), // TOC contains invalid listen window delay 173 CY_SROM_CY_FB_ERROR_FLL_CONFIG = (int32_t)(0xF1000106UL), // FLL configuration failed 174 CY_SROM_CY_FB_ERROR_INVALID_APP_DATA = (int32_t)(0xF1000107UL), // Invalid application structure 175 } cy_en_srom_api_status_t; 176 177 typedef enum 178 { 179 CY_SROM_DR_SUCCEEDED = 0, 180 CY_SROM_DR_IPC_BUSY = 1, 181 CY_SROM_DR_TIMEOUT = 2, 182 CY_SROM_DR_API_ERROR = 3, 183 CY_SROM_DR_API_UNKNOWN = 4, 184 CY_SROM_DR_INVALID_INPUT = 5, 185 } cy_en_srom_driver_status_t; 186 187 typedef enum 188 { 189 CY_SROM_RESPONSE_SUCCESS = 0, 190 CY_SROM_RESPONSE_FAIL = 1, 191 CY_SROM_NOT_RESPONSE = 2, 192 } cy_en_srom_response_type_t; 193 194 195 /**********************************/ 196 /*** Silicon ID Data Structures ***/ 197 /**********************************/ 198 199 /* Request Message */ 200 typedef struct 201 { 202 uint32_t : 8; 203 uint32_t IdType : 8; 204 uint32_t : 8; 205 uint32_t Opcode : 8; 206 } cy_stc_silicon_id_arg0_t; 207 208 typedef struct 209 { 210 cy_stc_silicon_id_arg0_t arg0; 211 uint32_t resv[3]; 212 } cy_stc_silicon_id_args_t; 213 214 /* Response Message */ 215 typedef struct 216 { 217 uint32_t FamilyIdLow : 8; 218 uint32_t FamilyIdHigh : 8; 219 uint32_t MinorRevisionID : 4; 220 uint32_t MajorRevisionId : 4; 221 uint32_t : 4; 222 uint32_t StatusCode : 4; 223 } cy_stc_silicon_id_resp_type0_t; 224 225 typedef struct 226 { 227 uint32_t SiliconIdLow : 8; 228 uint32_t SiliconIdHigh : 8; 229 uint32_t ProtectionState : 4; 230 uint32_t LifeCycleState : 4; 231 uint32_t : 4; 232 uint32_t StatusCode : 4; 233 } cy_stc_silicon_id_resp_type1_t; 234 235 typedef enum 236 { 237 CY_LIFE_CYCLE_STATE_VIRGIN = 0, 238 CY_LIFE_CYCLE_STATE_NORMAL = 1, 239 CY_LIFE_CYCLE_STATE_SEC_W_DBG = 2, 240 CY_LIFE_CYCLE_STATE_SECURE = 3, 241 CY_LIFE_CYCLE_STATE_RMA = 4, 242 CY_LIFE_CYCLE_STATE_SORT = 5, 243 CY_LIFE_CYCLE_STATE_PROVISIONED = 6, 244 CY_LIFE_CYCLE_STATE_NORMAL_PROVISIONED = 7, 245 CY_LIFE_CYCLE_STATE_NORMAL_RMA = 8, 246 CY_LIFE_CYCLE_STATE_CORRUPTED = 9, 247 } cy_en_life_cycle_state_t; 248 249 typedef enum 250 { 251 CY_PROTECTION_STATE_UNKNOWN = 0, 252 CY_PROTECTION_STATE_VIRGIN = 1, 253 CY_PROTECTION_STATE_NORMAL = 2, 254 CY_PROTECTION_STATE_SECURE = 3, 255 CY_PROTECTION_STATE_DEAD = 4, 256 } cy_en_protection_state_t; 257 258 typedef struct 259 { 260 uint32_t SROM_FW_MinorVersion : 8; 261 uint32_t SROM_FW_MajorVersion : 8; 262 uint32_t FlashBootMinorVersion : 8; 263 uint32_t FlashBootMajorVersion : 4; 264 uint32_t StatusCode : 4; 265 } cy_stc_silicon_id_resp_type2_t; 266 267 typedef union 268 { 269 uint32_t u32; 270 cy_stc_silicon_id_resp_type0_t IdType0; 271 cy_stc_silicon_id_resp_type1_t IdType1; 272 cy_stc_silicon_id_resp_type2_t IdType2; 273 } cy_un_slicon_id_resp0_t; 274 275 typedef struct 276 { 277 cy_un_slicon_id_resp0_t resp0; 278 uint32_t resv[3]; 279 } cy_stc_slicon_id_resps_t; 280 281 /**************************************/ 282 /*** Read Unique ID Data Structures ***/ 283 /**************************************/ 284 /* Request Message */ 285 typedef struct 286 { 287 uint32_t : 24; 288 uint32_t Opcode : 8; 289 } cy_stc_rd_unique_id_arg0_t; 290 291 typedef struct 292 { 293 cy_stc_rd_unique_id_arg0_t arg0; 294 uint32_t resv[3]; 295 } cy_stc_rd_unique_id_args_t; 296 297 /* Response Message */ 298 typedef struct 299 { 300 uint32_t ErrorCode : 24; 301 uint32_t : 4; 302 uint32_t StatusCode : 4; 303 } cy_stc_rd_unique_id_resp0_t; 304 305 typedef struct 306 { 307 uint32_t DIE_ID0 : 32; 308 } cy_stc_rd_unique_id_resp1_t; 309 310 typedef struct 311 { 312 uint32_t DIE_ID1 : 32; 313 } cy_stc_rd_unique_id_resp2_t; 314 315 typedef struct 316 { 317 cy_stc_rd_unique_id_resp0_t resp0; 318 cy_stc_rd_unique_id_resp1_t resp1; 319 cy_stc_rd_unique_id_resp2_t resp2; 320 uint32_t resp3; 321 } cy_stc_rd_unique_id_resps_t; 322 323 /*********************************/ 324 /*** Read Fuse Byte Structures ***/ 325 /*********************************/ 326 #define CY_SROM_EFUSE_RESERVED_NUM (104) 327 #define CY_SROM_EFUSE_CUSTOMER_DATA_NUM (24) 328 typedef struct 329 { 330 uint8_t Reserved[CY_SROM_EFUSE_RESERVED_NUM]; 331 uint8_t CustomerData[CY_SROM_EFUSE_CUSTOMER_DATA_NUM]; 332 } cy_stc_efuse_byte_map_t; 333 334 /* Request Message */ 335 typedef struct 336 { 337 uint32_t : 8; 338 uint32_t eFuseAddr : 16; 339 uint32_t Opcode : 8; 340 } cy_stc_rd_efuse_byte_arg0_t; 341 342 typedef struct 343 { 344 cy_stc_rd_efuse_byte_arg0_t arg0; 345 uint32_t resv[3]; 346 } cy_stc_rd_efuse_byte_args_t; 347 348 /* Response Message */ 349 typedef struct 350 { 351 uint32_t ReadByte : 8; 352 uint32_t : 20; 353 uint32_t StatusCode : 4; 354 } cy_stc_rd_efuse_byte_resp0_t; 355 356 typedef struct 357 { 358 cy_stc_rd_efuse_byte_resp0_t resp0; 359 uint32_t resv[3]; 360 } cy_stc_rd_efuse_byte_resps_t; 361 362 363 364 /*********************************************************/ 365 /*** Configure & Switch Over Regulator Data Structures ***/ 366 /*********************************************************/ 367 368 /** Operation mode of REGHC IP (ignored in case of PMIC IP) */ 369 typedef enum 370 { 371 CY_SROM_REGULATOR_MODE_TRANSISTOR = 0, 372 CY_SROM_REGULATOR_MODE_PMIC = 1, 373 } cy_en_srom_regulator_mode_t; 374 375 /** Target of switching regulators */ 376 typedef enum 377 { 378 CY_SROM_REGULATOR_SWITCH_TARGET_EXT = 0, 379 CY_SROM_REGULATOR_SWITCH_TARGET_INT = 1, 380 } cy_en_srom_regulator_switch_target_t; 381 382 /** Polarity of the PMICs "power good" / "abnormal" status output */ 383 typedef enum 384 { 385 CY_SROM_REGULATOR_STATUS_ABNORMAL_LOW = 0, 386 CY_SROM_REGULATOR_STATUS_ABNORMAL_HIGH = 1, 387 } cy_en_srom_regulator_status_polarity_t; 388 389 /** Polarity of the signal to enable the PMIC */ 390 typedef enum 391 { 392 CY_SROM_REGULATOR_ENABLE_LOW = 0, 393 CY_SROM_REGULATOR_ENABLE_HIGH = 1, 394 } cy_en_srom_regulator_enable_polarity_t; 395 396 397 /* Request Message */ 398 typedef struct 399 { 400 uint32_t : 1; 401 uint32_t Mode : 1; 402 uint32_t : 6; 403 uint32_t SwitchTarget : 8; 404 uint32_t Blocking : 8; 405 uint32_t Opcode : 8; 406 } cy_stc_switch_regulator_args_t; 407 408 409 /* Request Message 0 for configure regulator */ 410 typedef struct 411 { 412 uint32_t : 1; 413 uint32_t Mode : 1; 414 uint32_t EnablePolarity : 1; 415 uint32_t StatusAbnormalPolarity : 1; 416 uint32_t DeepSleep : 1; 417 uint32_t KeepIntRegEnabled : 1; 418 uint32_t : 2; 419 uint32_t VoltageAdjust : 4; 420 uint32_t : 12; 421 uint32_t Opcode : 8; 422 } cy_stc_configure_regulator_args_t; 423 424 typedef struct 425 { 426 uint32_t : 1; 427 uint32_t Mode : 1; 428 uint32_t EnablePolarity : 1; 429 uint32_t StatusAbnormalPolarity : 1; 430 uint32_t DeepSleep : 1; 431 uint32_t UseLinReg : 1; 432 uint32_t UseRadj : 1; 433 uint32_t VadjOption : 1; 434 uint32_t VoltageAdjust : 5; 435 uint32_t RAdjust : 3; 436 uint32_t : 8; 437 uint32_t Opcode : 8; 438 } cy_stc_configure_regulator2_args_t; 439 440 /* Request Message 1 for configure regulator 2 (new api) */ 441 typedef struct 442 { 443 uint32_t WaitCountIn1us : 10; // Wait count in 1us steps after PMIC status ok. 444 uint32_t : 22; 445 } cy_stc_configure_regulator2_args_2_t; 446 447 448 /************************************/ 449 /*** Flash Program Row Structures ***/ 450 /************************************/ 451 452 typedef enum 453 { 454 CY_SROM_PROGRAMROW_DATA_SIZE_8BIT = (0x00UL), 455 CY_SROM_PROGRAMROW_DATA_SIZE_16BIT = (0x01UL), 456 CY_SROM_PROGRAMROW_DATA_SIZE_32BIT = (0x02UL), 457 CY_SROM_PROGRAMROW_DATA_SIZE_64BIT = (0x03UL), 458 CY_SROM_PROGRAMROW_DATA_SIZE_128BIT = (0x04UL), 459 CY_SROM_PROGRAMROW_DATA_SIZE_256BIT = (0x05UL), 460 CY_SROM_PROGRAMROW_DATA_SIZE_512BIT = (0x06UL), 461 CY_SROM_PROGRAMROW_DATA_SIZE_1024BIT = (0x07UL), 462 CY_SROM_PROGRAMROW_DATA_SIZE_2048BIT = (0x08UL), 463 CY_SROM_PROGRAMROW_DATA_SIZE_4096BIT = (0x09UL) 464 } cy_en_programrow_datasize_t; 465 466 typedef enum 467 { 468 CY_SROM_PROGRAMROW_NON_BLOCKING = (0x00UL), // Non-blocking 469 CY_SROM_PROGRAMROW_BLOCKING = (0x01UL) // API blocks CM0+ 470 } cy_en_programrow_blocking_t; 471 472 typedef enum 473 { 474 CY_SROM_PROGRAMROW_BLANK_CHECK = (0x00UL), // Perform blank check 475 CY_SROM_PROGRAMROW_SKIP_BLANK_CHECK = (0x01UL) // Skips the blank check step 476 } cy_en_programrow_skipblankcheck_t; 477 478 typedef enum 479 { 480 CY_SROM_PROGRAMROW_DATA_LOCATION_SRAM = (0x01UL) // SRAM 481 } cy_en_programrow_location_t; 482 483 typedef enum 484 { 485 CY_SROM_PROGRAMROW_NOT_SET_INTR_MASK = (0x00UL), // Set FM interrupt mask 486 CY_SROM_PROGRAMROW_SET_INTR_MASK = (0x01UL) // Don't set FM interrupt mask 487 } cy_en_programrow_intrmask_t; 488 489 /* Request Message */ 490 typedef struct 491 { 492 uint32_t rev0 : 8; // reserved 493 uint32_t blocking : 8; // Blocking. see \ref cy_en_programrow_blocking_t 494 uint32_t skipBlankCheck : 8; // Skip blank check. see \ref cy_en_programrow_skipblankcheck_t 495 uint32_t opcode : 8; // Opcode = 0x06 496 } cy_stc_program_row_arg0_t; 497 498 typedef struct 499 { 500 uint32_t dataSize : 8; // Data size. see \ref cy_en_programrow_datasize_t 501 uint32_t dataLoc : 8; // Data location. see \ref cy_en_programrow_location_t 502 uint32_t rev0 : 8; // reserved 503 uint32_t interruptMask : 8; // Interrupt mask (Applicable only for eCT non-blocking). see \ref cy_en_programrow_intrmask_t 504 } cy_stc_program_row_arg1_t; 505 506 typedef struct 507 { 508 uint32_t dstAddr : 32; // Flash address to be programmed 509 } cy_stc_program_row_arg2_t; 510 511 typedef struct 512 { 513 uint32_t srcAddr : 32; // 32-bit aligned address of SRAM where data to be programmed will be stored 514 } cy_stc_program_row_arg3_t; 515 516 typedef struct 517 { 518 cy_stc_program_row_arg0_t arg0; 519 cy_stc_program_row_arg1_t arg1; 520 cy_stc_program_row_arg2_t arg2; 521 cy_stc_program_row_arg3_t arg3; 522 } cy_stc_program_row_args_t; 523 524 /* Response Message */ 525 typedef struct 526 { 527 uint32_t Indication : 28; // indication 528 uint32_t statusCode : 4; // status code 529 } cy_stc_program_row_resp0_t; 530 531 typedef struct 532 { 533 cy_stc_program_row_resp0_t resp0; 534 uint32_t resv[3]; 535 } cy_stc_program_row_resps_t; 536 537 /*************************************/ 538 /*** Flash Erase Sector Structures ***/ 539 /*************************************/ 540 typedef enum 541 { 542 CY_SROM_ERASE_NON_BLOCKING = (0x00UL), // Non-blocking 543 CY_SROM_ERASE_BLOCKING = (0x01UL) // API blocks CM0+ 544 } cy_en_erase_blocking_t; 545 546 typedef enum 547 { 548 CY_SROM_ERASE_NOT_SET_INTR_MASK = (0x00UL), // Set FM interrupt mask 549 CY_SROM_ERASE_SET_INTR_MASK = (0x01UL) // Don't set FM interrupt mask 550 } cy_en_erase_intrmask_t; 551 552 /* Request Message */ 553 typedef struct 554 { 555 uint32_t rev0 : 8; 556 uint32_t blocking : 8; // see \ref cy_en_erase_blocking_t 557 uint32_t interruptMask : 8; // see \ref cy_en_erase_intrmask_t 558 uint32_t opcode : 8; // Opcode = 0x14 559 } cy_stc_erase_sector_arg0_t; 560 561 typedef struct 562 { 563 uint32_t address : 32; 564 } cy_stc_erase_sector_arg1_t; 565 566 typedef struct 567 { 568 cy_stc_erase_sector_arg0_t arg0; 569 cy_stc_erase_sector_arg1_t arg1; 570 uint32_t resv[2]; 571 } cy_stc_erase_sector_args_t; 572 573 /* Response Message */ 574 typedef struct 575 { 576 uint32_t indication : 28; // indication 577 uint32_t statusCode : 4; // status code 578 } cy_stc_erase_sector_resp0_t; 579 580 typedef struct 581 { 582 cy_stc_erase_sector_resp0_t resp0; 583 uint32_t resv[3]; 584 } cy_stc_erase_sector_resps_t; 585 586 /**********************************/ 587 /*** Flash Erase All Structures ***/ 588 /**********************************/ 589 /* Request Message */ 590 typedef struct 591 { 592 uint32_t rev0 : 24; 593 uint32_t opcode : 8; 594 } cy_stc_erase_all_arg0_t; 595 596 typedef struct 597 { 598 cy_stc_erase_all_arg0_t arg0; 599 uint32_t resv[3]; 600 } cy_stc_erase_all_args_t; 601 602 /* Response Message */ 603 typedef struct 604 { 605 uint32_t indication : 28; // indication 606 uint32_t statusCode : 4; // status code 607 } cy_stc_erase_all_resp0_t; 608 609 typedef struct 610 { 611 cy_stc_erase_sector_resp0_t resp0; 612 uint32_t resv[3]; 613 } cy_stc_erase_all_resps_t; 614 615 /****************************************/ 616 /*** Flash Check FM Status Structures ***/ 617 /****************************************/ 618 /* Request Message */ 619 typedef struct 620 { 621 uint32_t rev0 : 24; 622 uint32_t opcode : 8; // Opcode = 0x07 623 } cy_stc_check_fm_status_arg0_t; 624 625 typedef struct 626 { 627 cy_stc_check_fm_status_arg0_t arg0; 628 uint32_t resv[3]; 629 } cy_stc_check_fm_status_args_t; 630 631 /* Response Message */ 632 typedef struct 633 { 634 uint16_t pgm_code : 1; // Indicates if active PGM operation to the Code flash is taking place 635 uint16_t pgm_work : 1; // Indicates if active PGM operation to the Work flash is taking place 636 uint16_t erase_code : 1; // Indicates if active Erase operation to the Code flash is taking place 637 uint16_t erase_work : 1; // Indicates if active Erase operation to the Work flash is taking place 638 uint16_t ers_suspend : 1; // Indicates if Erase operation (Code/Work) is currently being suspended 639 uint16_t blank_check_work : 1; // Indicates if Blank Check mode is currently running on the work flash 640 uint16_t blank_check_pass : 1; // Indicates the Blank check command result is Blank 641 uint16_t hang : 1; // After embedded operation (pgm/erase) this flag will tell if it was successful or failed 642 uint16_t busy : 1; // Whenever the device is in embedded mode the RDY goes 643 uint16_t : 7; // reserved 644 } cy_stc_fm_status_t; 645 646 typedef union 647 { 648 uint16_t u16; 649 cy_stc_fm_status_t bf; // see \n cy_stc_fm_status_t 650 } cy_un_fm_status_t ; 651 652 typedef struct 653 { 654 uint32_t status : 9; // FM status 655 uint32_t :19; // reserved 656 uint32_t statusCode : 4; // status code 657 } cy_stc_check_fm_status_resp0_t; 658 659 typedef struct 660 { 661 cy_stc_check_fm_status_resp0_t resp0; 662 uint32_t resv[3]; 663 } cy_stc_check_fm_status_resps_t; 664 665 666 /***********************************************/ 667 /*** Flash Configure FM Interrupt Structures ***/ 668 /***********************************************/ 669 typedef enum 670 { 671 CY_SROM_FM_INTR_OPT_CLEAR_INTR_MASK = (0x00UL), 672 CY_SROM_FM_INTR_OPT_SET_INTR_MASK = (0x01UL), 673 CY_SROM_FM_INTR_OPT_CLEAR_INTR = (0x02UL) 674 } cy_en_conf_fm_intr_option_t; 675 676 /* Request Message */ 677 typedef struct 678 { 679 uint32_t : 8; 680 uint32_t option : 8; // options, see \ref cy_en_conf_fm_intr_option_t 681 uint32_t : 8; 682 uint32_t opcode : 8; // Opcode = 0x08 683 } cy_stc_conf_fm_intr_arg0_t; 684 685 typedef struct 686 { 687 cy_stc_conf_fm_intr_arg0_t arg0; 688 uint32_t resv[3]; 689 } cy_stc_conf_fm_intr_args_t; 690 691 /* Response Message */ 692 typedef struct 693 { 694 uint32_t status : 28; // status 695 uint32_t statusCode : 4; // status code 696 } cy_stc_conf_fm_intr_resp0_t; 697 698 typedef struct 699 { 700 cy_stc_conf_fm_intr_resp0_t resp0; 701 uint32_t resv[3]; 702 } cy_stc_conf_fm_intr_resps_t; 703 704 /*********************************/ 705 /*** Flash Checksum Structures ***/ 706 /*********************************/ 707 typedef enum 708 { 709 CY_SROM_CHECKSUM_BANK0 = (0x00UL), 710 CY_SROM_CHECKSUM_BANK1 = (0x01UL) 711 } cy_en_checksum_bank_t; 712 713 typedef enum 714 { 715 CY_SROM_CHECKSUM_PAGE = (0x00UL), 716 CY_SROM_CHECKSUM_WHOLE = (0x01UL) 717 } cy_en_checksum_scope_t; 718 719 typedef enum 720 { 721 CY_SROM_CHECKSUM_MAIN = (0x00UL), 722 CY_SROM_CHECKSUM_WOEK = (0x01UL), 723 CY_SROM_CHECKSUM_SUPERVISORY = (0x02UL) 724 } cy_en_checksum_region_t; 725 726 /* Request Message */ 727 typedef struct 728 { 729 uint32_t : 7; 730 uint32_t bank : 1; // see \ref cy_en_checksum_bank_t 731 uint32_t row_id : 13; // Row id 732 uint32_t whole : 1; // see \ref cy_en_checksum_scope_t 733 uint32_t region : 2; // see \ref cy_en_checksum_region_t 734 uint32_t opcode : 8; // Opcode = 0x0B 735 } stc_checksum_less_than_4M_arg0_t; 736 737 typedef struct 738 { 739 uint32_t : 1; 740 uint32_t bank : 1; // see \ref cy_en_checksum_bank_t 741 uint32_t : 2; 742 uint32_t row_id : 17; // Row id 743 uint32_t whole : 1; // see \ref cy_en_checksum_scope_t 744 uint32_t region : 2; // see \ref cy_en_checksum_region_t 745 uint32_t opcode : 8; // Opcode = 0x0B 746 } stc_checksum_arg0_t; 747 748 typedef struct 749 { 750 stc_checksum_less_than_4M_arg0_t arg0; 751 uint32_t resv[3]; 752 } stc_checksum_less_than_4M_args_t; 753 754 typedef struct 755 { 756 stc_checksum_arg0_t arg0; 757 uint32_t resv[3]; 758 } stc_checksum_args_t; 759 760 /* Response Message */ 761 typedef struct 762 { 763 uint32_t : 28; // Nothing 764 uint32_t statusCode : 4; // status code 765 } stc_checksum_resp0_t; 766 767 typedef struct 768 { 769 stc_checksum_resp0_t resp0; 770 uint32_t resv[3]; 771 } cy_stc_checksum_resps_t; 772 773 /*******************************************/ 774 /*** Flash Compute Basic Hash Structures ***/ 775 /*******************************************/ 776 typedef enum 777 { 778 CY_SROM_COMPUTE_HASH_BASIC = (0x00UL), 779 CY_SROM_COMPUTE_HASH_CRC8 = (0x01UL) 780 } cy_en_computehash_type_t; 781 782 /* Request Message */ 783 typedef struct 784 { 785 uint32_t : 8; 786 uint32_t type : 8; // see \ref cy_en_computehash_type_t 787 uint32_t : 8; 788 uint32_t opcode : 8; // Opecde = 0x0D 789 } cy_stc_compute_hash_arg0_t; 790 791 typedef struct 792 { 793 uint32_t start_addr : 32; 794 } cy_stc_compute_hash_arg1_t; 795 796 typedef struct 797 { 798 uint32_t number_byte : 24; // Number of bytes (0: 1 byte,1: 2 bytes etc.) 799 uint32_t : 8; 800 } cy_stc_compute_hash_arg2_t; 801 802 typedef struct 803 { 804 cy_stc_compute_hash_arg0_t arg0; 805 cy_stc_compute_hash_arg1_t arg1; 806 cy_stc_compute_hash_arg2_t arg2; 807 uint32_t resv; 808 } cy_stc_compute_hash_args_t; 809 810 /* Response Message */ 811 typedef struct 812 { 813 uint32_t hash_crc : 28; // Hash/CRC of the data 814 uint32_t statusCode : 4; // status code 815 } cy_stc_compute_hash_resp0_t; 816 817 typedef struct 818 { 819 cy_stc_compute_hash_resp0_t resp0; 820 uint32_t resv[3]; 821 } cy_stc_compute_hash_resps_t; 822 823 /**************************************/ 824 /*** Flash Erase Suspend Structures ***/ 825 /**************************************/ 826 /* Request Message */ 827 typedef struct 828 { 829 uint32_t rev0 : 24; 830 uint32_t opcode : 8; // Opcode = 0x22 831 } cy_stc_erase_suspend_arg0_t; 832 833 typedef struct 834 { 835 cy_stc_erase_suspend_arg0_t arg0; 836 uint32_t resv[3]; 837 } cy_stc_erase_suspend_args_t; 838 839 /* Response Message */ 840 typedef struct 841 { 842 uint32_t errorCode : 28; // error code 843 uint32_t statusCode : 4; // status code 844 } cy_stc_erase_suspend_resp0_t; 845 846 typedef struct 847 { 848 cy_stc_erase_suspend_resp0_t resp0; 849 uint32_t resv[3]; 850 } cy_stc_erase_suspend_resps_t; 851 852 /*************************************/ 853 /*** Flash Erase Resume Structures ***/ 854 /*************************************/ 855 /* Request Message */ 856 typedef struct 857 { 858 uint32_t rev0 : 8; 859 uint32_t blocking : 8; // see \ref cy_en_erase_blocking_t 860 uint32_t intrmask : 1; // see \ref cy_en_erase_intrmask_t 861 uint32_t : 7; 862 uint32_t opcode : 8; // Opcode = 0x23 863 } cy_stc_erase_resume_arg0_t; 864 865 typedef struct 866 { 867 cy_stc_erase_resume_arg0_t arg0; 868 uint32_t resv[3]; 869 } cy_stc_erase_resume_args_t; 870 871 /* Response Message */ 872 typedef struct 873 { 874 uint32_t errorCode : 28; // error code 875 uint32_t statusCode : 4; // status code 876 } cy_stc_erase_resume_resp0_t; 877 878 typedef struct 879 { 880 cy_stc_erase_resume_resp0_t resp0; 881 uint32_t resv[3]; 882 } cy_stc_erase_resume_resps_t; 883 884 /************************************/ 885 /*** Flash Blank Check Structures ***/ 886 /************************************/ 887 /* Request Message */ 888 typedef struct 889 { 890 uint32_t : 24; 891 uint32_t opcode : 8; // Opcode = 0x2A 892 } cy_stc_blank_check_arg0_t; 893 894 typedef struct 895 { 896 uint32_t addrToBeChecked : 32; 897 } cy_stc_blank_check_arg1_t; 898 899 typedef struct 900 { 901 uint32_t numOfWordsToBeChecked : 16; // 0: 1 word, 1: 2 words etc. 902 uint32_t : 16; 903 } cy_stc_blank_check_arg2_t; 904 905 typedef struct 906 { 907 cy_stc_blank_check_arg0_t arg0; 908 cy_stc_blank_check_arg1_t arg1; 909 cy_stc_blank_check_arg2_t arg2; 910 uint32_t resv; 911 } cy_stc_blank_check_args_t; 912 913 /* Response Message */ 914 typedef struct 915 { 916 uint32_t errorCode : 8; // error code 917 uint32_t failedWordId : 16; // first failed word number 918 uint32_t : 4; 919 uint32_t statusCode : 4; // status code 920 } cy_stc_blank_check_resp0_t; 921 922 typedef struct 923 { 924 cy_stc_blank_check_resp0_t resp0; 925 uint32_t resv[3]; 926 } cy_stc_blank_check_resps_t; 927 928 /*************************/ 929 /*** Generic Structure ***/ 930 /*************************/ 931 /* SROM API argument union 1 */ 932 typedef union 933 { 934 uint32_t arg[4]; 935 cy_stc_silicon_id_args_t SiId; 936 cy_stc_rd_unique_id_args_t RdUnId; 937 cy_stc_rd_efuse_byte_args_t RdFuse; 938 cy_stc_switch_regulator_args_t SwitchRegulator; 939 cy_stc_configure_regulator_args_t ConfigureRegulator; 940 cy_stc_configure_regulator2_args_t ConfigureRegulator2; 941 cy_stc_program_row_args_t ProgramRow; 942 cy_stc_erase_sector_args_t EraseSector; 943 cy_stc_erase_all_args_t EraseAll; 944 cy_stc_check_fm_status_args_t CheckFmStatus; 945 cy_stc_conf_fm_intr_args_t ConfigFmIntr; 946 stc_checksum_less_than_4M_args_t CheckSumLessThan4M; 947 stc_checksum_args_t CheckSum; 948 cy_stc_compute_hash_args_t ComputeHash; 949 cy_stc_erase_suspend_args_t EraseSuspend; 950 cy_stc_erase_resume_args_t EraseResume; 951 cy_stc_blank_check_args_t BlankCheck; 952 } un_srom_api_args_t; 953 954 /* SROM API argument union 2 */ 955 typedef union 956 { 957 uint32_t arg[4]; 958 cy_stc_configure_regulator2_args_2_t ConfigureRegulator2; 959 } un_srom_api_args_2_t; 960 961 /* SROM API response union */ 962 typedef union 963 { 964 uint32_t resp[4]; 965 cy_stc_slicon_id_resps_t SiId; 966 cy_stc_rd_unique_id_resps_t RdUnId; 967 cy_stc_rd_efuse_byte_resps_t RdFuse; 968 cy_stc_program_row_resps_t ProgramRow; 969 cy_stc_erase_sector_resps_t EraseSector; 970 cy_stc_erase_all_resps_t EraseAll; 971 cy_stc_check_fm_status_resps_t CheckFmStatus; 972 cy_stc_conf_fm_intr_resps_t ConfigFmIntr; 973 cy_stc_checksum_resps_t CheckSum; 974 cy_stc_compute_hash_resps_t ComputeHash; 975 cy_stc_erase_suspend_resps_t EraseSuspend; 976 cy_stc_erase_resume_resps_t EraseResume; 977 cy_stc_blank_check_resps_t BlankCheck; 978 } un_srom_api_resps_t; 979 980 typedef union 981 { 982 uint32_t u32[4]; 983 un_srom_api_args_t args; 984 un_srom_api_resps_t resps; 985 } un_srom_api_scrach_sram_t; 986 987 988 /****************************/ 989 /*** Function Declaration ***/ 990 /****************************/ 991 extern cy_en_srom_driver_status_t Cy_Srom_CallApi(const un_srom_api_args_t* params, un_srom_api_resps_t* resp); 992 extern cy_en_srom_driver_status_t Cy_Srom_CallApi_NonBlock(const un_srom_api_args_t* params); 993 extern cy_en_srom_driver_status_t Cy_Srom_CallApi_2(const un_srom_api_args_t* params, const un_srom_api_args_2_t* params2, un_srom_api_resps_t* resp); 994 extern cy_en_srom_driver_status_t Cy_Srom_CallApi_NonBlock_2(const un_srom_api_args_t* params, const un_srom_api_args_2_t* params2); 995 extern cy_en_srom_response_type_t Cy_Srom_GetResponseType(void); 996 extern cy_en_srom_api_status_t Cy_Srom_GetApiResponse(un_srom_api_resps_t* resp); 997 extern cy_en_srom_api_status_t Cy_Srom_ConvertRespToStatus(uint32_t resp0); 998 extern void Cy_Srom_SetResponseHandler(cy_srom_handler handler); 999 1000 #endif 1001 /** \endcond */ 1002 1003 #endif /* CY_IP_M4CPUSS CY_IP_M7CPUSS*/ 1004
