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Searched refs:CY_PRA_REG32_SET (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c147 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), tempReg2); in Cy_GPIO_Pin_Init()
197 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), tempReg2); in Cy_GPIO_Pin_Init()
311 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG), config->cfg); in Cy_GPIO_Port_Init()
312 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_IN), config->cfgIn); in Cy_GPIO_Port_Init()
313 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_OUT), config->cfgOut); in Cy_GPIO_Port_Init()
314 …CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_CFG), config->intrCfg); in Cy_GPIO_Port_Init()
315 …CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_INTR_MASK), config->intrMas… in Cy_GPIO_Port_Init()
316 … CY_PRA_REG32_SET(CY_PRA_GET_PORT_REG_INDEX(base, CY_PRA_SUB_INDEX_PORT_CFG_SIO), config->cfgSIO); in Cy_GPIO_Port_Init()
317 …CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0), config->sel0Activ… in Cy_GPIO_Port_Init()
318 …CY_PRA_REG32_SET(CY_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1), config->sel1Activ… in Cy_GPIO_Port_Init()
[all …]
Dcy_wdt.c230 CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR, _VAL2FLD(SRSS_SRSS_INTR_WDT_MATCH, 1U)); in Cy_WDT_ClearInterrupt()
Dcy_syslib.c191 CY_PRA_REG32_SET(CY_PRA_INDX_FLASHC_FLASH_CMD, FLASHC_FLASH_CMD_INV_Msk); in Cy_SysLib_ClearFlashCacheAndBuffer()
Dcy_syspm.c1061 …CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, (SRSS_PWR_HIBERNATE & (uint32_t) ~polarityMask) |… in Cy_SysPm_SetHibernateWakeupSource()
1102 …CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, (SRSS_PWR_HIBERNATE & (uint32_t) ~clearWakeupSour… in Cy_SysPm_ClearHibernateWakeupSource()
Dcy_flash.c1375 CY_PRA_REG32_SET(CY_PRA_INDX_FLASHC_FLASH_CMD, FLASHC_FLASH_CMD_INV_Msk); in Cy_Flash_OperationStatus()
Dcy_sysclk.c730 …CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_CLK_MFO_CONFIG, (SRSS_CLK_MFO_CONFIG_ENABLE_Msk | (deepSleepEnab… in Cy_SysClk_MfoEnable()
749 CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_CLK_MFO_CONFIG, 0UL); in Cy_SysClk_MfoDisable()
/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/
Dcy_lvd.h505 CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR, CY_LVD_SRSS_INTR_HVLVD1_MASK); in Cy_LVD_ClearInterrupt()
531 CY_PRA_REG32_SET(CY_PRA_INDX_SRSS_SRSS_INTR_SET, CY_LVD_SRSS_INTR_SET_HVLVD1_MASK); in Cy_LVD_SetInterrupt()
Dcy_pra.h835 #define CY_PRA_REG32_SET(regIndex, value) \ macro