Searched refs:CY_PRA_REG32_CLR_SET (Results 1 – 5 of 5) sorted by relevance
| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_lvd.h | 397 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EN, 1U); in Cy_LVD_Enable()
414 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_EN, 0U); in Cy_LVD_Disable()
440 … CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_LVD_CTL, SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL, threshold); in Cy_LVD_SetThreshold()
571 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_HVLVD1, 1U); in Cy_LVD_SetInterruptMask()
591 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_HVLVD1, 0U); in Cy_LVD_ClearInterruptMask()
637 …CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_CFG, SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL, lvdInterr… in Cy_LVD_SetInterruptConfig()
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| D | cy_wdt.h | 736 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 0U); in Cy_WDT_MaskInterrupt()
758 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_SRSS_INTR_MASK, SRSS_SRSS_INTR_MASK_WDT_MATCH, 1U); in Cy_WDT_UnmaskInterrupt()
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| D | cy_pra.h | 815 #define CY_PRA_REG32_CLR_SET(regIndex, field, value) \ macro
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| /hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_syslib.c | 241 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_PWR_HIBERNATE, SRSS_PWR_HIBERNATE_TOKEN, 0UL); in Cy_SysLib_ClearResetReason()
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| D | cy_sysclk.c | 762 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 1U); in Cy_SysClk_ClkMfEnable()
781 CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_ENABLE, 0U); in Cy_SysClk_ClkMfDisable()
796 … CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); in Cy_SysClk_ClkMfSetDivider()
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