CY_BLE_PORT4_HSIOM_SEL1 (reference) in projects: hal_infineon-3.5.0

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Searched refs:CY_BLE_PORT4_HSIOM_SEL1 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-3.5.0/mtb-pdl-cat1/drivers/source/
D	cy_ble_clk.c	`77 #define CY_BLE_PORT4_HSIOM_SEL1 (0x00000000u) macro 572 CY_BLE_PORT4_HSIOM_SEL1 /* sel1Active */ in Cy_BLE_HAL_Init()`
/hal_infineon-3.5.0/bless/
D	cy_ble_clk.c	`77 #define CY_BLE_PORT4_HSIOM_SEL1 (0x00000000u) macro 572 CY_BLE_PORT4_HSIOM_SEL1 /* sel1Active */ in Cy_BLE_HAL_Init()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
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babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
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