1 /***************************************************************************//** 2 * \file cy_ble_cfg_common.h 3 * \version 3.60 4 * 5 * \brief 6 * This file contains the source code for the API of the PSoC 6 BLE Middleware. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2017-2021, Cypress Semiconductor Corporation. All rights reserved. 11 * You may use this file only in accordance with the license, terms, conditions, 12 * disclaimers, and limitations in the end user license agreement accompanying 13 * the software package with which this file was provided. 14 *******************************************************************************/ 15 16 #if !defined(CY_BLE_CFG_COMMON_H) 17 #define CY_BLE_CFG_COMMON_H 18 19 #include "cy_syslib.h" 20 #include "cy_ble_defines.h" 21 22 23 24 25 /******************************************************************************* 26 * Set default configurations 27 *******************************************************************************/ 28 29 #if defined(COMPONENT_BLESS_CONTROLLER_IPC) || defined(COMPONENT_BLESS_HOST_IPC) 30 #define CY_BLE_CONFIG_MODE (CY_BLE_PROFILE) 31 #define CY_BLE_CONFIG_STACK_MODE (CY_BLE_STACK_MODE_DUAL_IPC) 32 33 #elif defined(COMPONENT_BLESS_CONTROLLER) && defined(COMPONENT_BLESS_HOST) 34 #define CY_BLE_CONFIG_MODE (CY_BLE_PROFILE) 35 #define CY_BLE_CONFIG_STACK_MODE (CY_BLE_STACK_MODE_SINGLE_SOC) 36 #define CY_BLE_CONFIG_HOST_CORE (__CORTEX_M) 37 38 #elif defined(CY_BLE_STACK_LIB_SINGLE_SOC_CM0P) 39 #define CY_BLE_CONFIG_MODE (CY_BLE_PROFILE) 40 #define CY_BLE_CONFIG_STACK_MODE (CY_BLE_STACK_MODE_SINGLE_SOC) 41 #define CY_BLE_CONFIG_HOST_CORE (CY_BLE_CORE_CORTEX_M0P) 42 43 #elif defined(COMPONENT_BLESS_CONTROLLER) && !defined(COMPONENT_BLESS_HOST) 44 #define CY_BLE_CONFIG_MODE (CY_BLE_HCI) 45 #define CY_BLE_CONFIG_STACK_MODE (CY_BLE_STACK_MODE_SINGLE_SOC) 46 47 #else 48 #define CY_BLE_CONFIG_MODE (CY_BLE_PROFILE) 49 #define CY_BLE_CONFIG_STACK_MODE (CY_BLE_STACK_MODE_SINGLE_SOC) 50 #define CY_BLE_CONFIG_HOST_CORE (CY_BLE_CORE_CORTEX_M4) 51 #endif 52 53 54 /******************************************************************************* 55 * Macros determines BLE cores and mode 56 *******************************************************************************/ 57 58 /* The BLE operation mode */ 59 #define CY_BLE_MODE (CY_BLE_CONFIG_MODE) 60 61 /* The BLE Stack core mode */ 62 #define CY_BLE_STACK_MODE (CY_BLE_CONFIG_STACK_MODE) 63 64 /* Default host core in CM4 */ 65 #if !defined(CY_BLE_CONFIG_HOST_CORE) 66 #define CY_BLE_CONFIG_HOST_CORE (CY_BLE_CORE_CORTEX_M4) 67 #endif /* (!CY_BLE_CORE_CORTEX_M4) */ 68 69 /* BLE core definitions */ 70 #define CY_BLE_HOST_CORE ((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M4) ? \ 71 CY_CPU_CORTEX_M4 : CY_CPU_CORTEX_M0P) 72 73 #define CY_BLE_CONTR_CORE ((CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_SINGLE_SOC) ? CY_BLE_HOST_CORE : \ 74 ((CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M0P) ? \ 75 CY_CPU_CORTEX_M4 : CY_CPU_CORTEX_M0P)) 76 77 /* BLE modes definitions */ 78 #define CY_BLE_MODE_PROFILE ((CY_BLE_CONFIG_MODE == CY_BLE_PROFILE) && (CY_BLE_HOST_CORE)) 79 #define CY_BLE_MODE_HCI (CY_BLE_CONFIG_MODE == CY_BLE_HCI) 80 81 82 /* Controller/host cores */ 83 #define CY_BLE_STACK_CONTR_CORE ((CY_BLE_MODE_HCI) || \ 84 ((CY_BLE_MODE == CY_BLE_PROFILE) && \ 85 ((CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_SINGLE_SOC) && (CY_BLE_HOST_CORE)) || \ 86 ((CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_DUAL_IPC) && (CY_BLE_CONTR_CORE)))) 87 88 #define CY_BLE_HOST_CONTR_CORE (CY_BLE_MODE_PROFILE || CY_BLE_STACK_CONTR_CORE) 89 90 #define CY_BLE_STACK_IPC_CONTR_CORE ((CY_BLE_MODE == CY_BLE_PROFILE) && \ 91 (CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_DUAL_IPC) && \ 92 (CY_BLE_CONTR_CORE)) 93 94 #define CY_BLE_STACK_IPC_HOST_CORE ((CY_BLE_MODE == CY_BLE_PROFILE) && \ 95 (CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_DUAL_IPC) && \ 96 (CY_BLE_HOST_CORE)) 97 /* Stack mode */ 98 #define CY_BLE_STACK_MODE_IPC (CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_DUAL_IPC) 99 #define CY_BLE_STACK_MODE_SOC (CY_BLE_STACK_MODE == CY_BLE_STACK_MODE_SINGLE_SOC) 100 101 102 /******************************************************************************* 103 * Macros 104 *******************************************************************************/ 105 106 /* Sharing mode defines */ 107 #define CY_BLE_SHARING_MODE_EXPORT (CY_BLE_SHARING_MODE == CY_BLE_SHARING_EXPORT) 108 #define CY_BLE_SHARING_MODE_IMPORT (CY_BLE_SHARING_MODE == CY_BLE_SHARING_IMPORT) 109 110 /* Align the buffer size value to 4 */ 111 #define CY_BLE_ALIGN_TO_4(x) ((((x) & 3u) == 0u) ? (x) : (((x) - ((x) & 3u)) + 4u)) 112 113 #define CY_BLE_GAPP_CONF_COUNT (CY_BLE_GAP_PERIPHERAL_COUNT + CY_BLE_GAP_BROADCASTER_COUNT) 114 #define CY_BLE_GAPC_CONF_COUNT (CY_BLE_GAP_CENTRAL_COUNT + CY_BLE_GAP_OBSERVER_COUNT) 115 116 /** The GAP Role defines */ 117 #define CY_BLE_GAP_ROLE_PERIPHERAL (0u != (CY_BLE_GAP_ROLE & CY_BLE_GAP_PERIPHERAL)) 118 #define CY_BLE_GAP_ROLE_CENTRAL (0u != (CY_BLE_GAP_ROLE & CY_BLE_GAP_CENTRAL)) 119 #define CY_BLE_GAP_ROLE_OBSERVER (0u != (CY_BLE_GAP_ROLE & CY_BLE_GAP_OBSERVER)) 120 #define CY_BLE_GAP_ROLE_BROADCASTER (0u != (CY_BLE_GAP_ROLE & CY_BLE_GAP_BROADCASTER)) 121 122 123 #if !defined(CY_BLE_CONN_COUNT) 124 #define CY_BLE_CONN_COUNT (1u) 125 #endif /* (!CY_BLE_CONN_COUNT) */ 126 127 /** 128 * The parameter to enable configuration of the L2CAP logical channels 129 */ 130 #if !defined(CY_BLE_L2CAP_ENABLE) 131 #define CY_BLE_L2CAP_ENABLE (0u) 132 #endif /* (!CY_BLE_L2CAP_ENABLE) */ 133 #if(CY_BLE_L2CAP_ENABLE != 0u) 134 135 /* L2CAP MTU Size */ 136 #define CY_BLE_L2CAP_MTU (CY_BLE_CONFIG_L2CAP_MTU) 137 138 /** L2CAP MPS Size */ 139 #if defined (CY_BLE_CONFIG_L2CAP_MPS) 140 #define CY_BLE_L2CAP_MPS (CY_BLE_CONFIG_L2CAP_MPS) 141 #else 142 #define CY_BLE_L2CAP_MPS (23u) 143 #endif /* defined (CY_BLE_CONFIG_L2CAP_MPS) */ 144 145 #define CY_BLE_L2CAP_MTU_MPS (CY_BLE_L2CAP_MTU / CY_BLE_L2CAP_MPS) 146 147 /* Number of L2CAP Logical channels */ 148 #define CY_BLE_L2CAP_LOGICAL_CHANNEL_COUNT (CY_BLE_CONFIG_L2CAP_LOGICAL_CHANNEL_COUNT) 149 150 /* Number of L2CAP PSMs */ 151 #define CY_BLE_L2CAP_PSM_COUNT (CY_BLE_CONFIG_L2CAP_PSM_COUNT) 152 153 #else 154 #define CY_BLE_L2CAP_MTU (0u) 155 #define CY_BLE_L2CAP_MPS (0u) 156 #define CY_BLE_L2CAP_MTU_MPS (0u) 157 #define CY_BLE_L2CAP_LOGICAL_CHANNEL_COUNT (0u) 158 #define CY_BLE_L2CAP_PSM_COUNT (0u) 159 #endif /* CY_BLE_L2CAP_ENABLE != 0u */ 160 161 #if (CY_BLE_MODE == CY_BLE_PROFILE) 162 163 /** LL Privacy 1.2 feature */ 164 #if !defined(CY_BLE_CONFIG_ENABLE_LL_PRIVACY) 165 #define CY_BLE_ENABLE_LL_PRIVACY (0u) 166 #else 167 #define CY_BLE_ENABLE_LL_PRIVACY (CY_BLE_CONFIG_ENABLE_LL_PRIVACY) 168 #endif /* !defined(CY_BLE_CONFIG_ENABLE_LL_PRIVACY) */ 169 170 /** The maximum number of peer devices whose addresses should be resolved by this device. */ 171 #if (CY_BLE_ENABLE_LL_PRIVACY != 0u) 172 #define CY_BLE_MAX_RESOLVABLE_DEVICES (CY_BLE_CONFIG_MAX_RESOLVABLE_DEVICES) 173 #else 174 #define CY_BLE_MAX_RESOLVABLE_DEVICES (0u) 175 #endif /* (CY_BLE_ENABLE_LL_PRIVACY == 0u) */ 176 177 /** The maximum number of devices that can be added to the white list. */ 178 #if defined (CY_BLE_CONFIG_MAX_WHITE_LIST_SIZE) 179 #define CY_BLE_MAX_WHITE_LIST_SIZE (CY_BLE_CONFIG_MAX_WHITE_LIST_SIZE) 180 #endif /* defined (CY_BLE_CONFIG_MAX_WHITE_LIST_SIZE) */ 181 182 /** The maximum number of bonded devices to be supported by this device. */ 183 #if defined (CY_BLE_CONFIG_MAX_BONDED_DEVICES) 184 #define CY_BLE_MAX_BONDED_DEVICES (CY_BLE_CONFIG_MAX_BONDED_DEVICES) 185 #endif /* defined (CY_BLE_CONFIG_MAX_BONDED_DEVICES) */ 186 187 /* The GAP security level */ 188 #if defined (CY_BLE_CONFIG_GAP_SECURITY_LEVEL) 189 #define CY_BLE_GAP_SECURITY_LEVEL (CY_BLE_CONFIG_GAP_SECURITY_LEVEL) 190 #endif /* defined (CY_BLE_CONFIG_GAP_SECURITY_LEVEL) */ 191 192 /** Additional queue depth provided from the customizer */ 193 #if defined (CY_BLE_CONFIG_ADD_Q_DEPTH_PER_CONN) 194 #define CY_BLE_ADD_Q_DEPTH_PER_CONN (CY_BLE_CONFIG_ADD_Q_DEPTH_PER_CONN) 195 #else 196 #define CY_BLE_ADD_Q_DEPTH_PER_CONN (0u) 197 #endif /* defined (CY_BLE_CONFIG_ADD_Q_DEPTH_PER_CONN) */ 198 199 /** 200 * Minimum stack queue depth requirement per connection 201 * The application can choose to give higher queue depth for better throughput. 202 */ 203 #define CY_BLE_L2CAP_Q_DEPTH_PER_CONN (CY_BLE_L2CAP_STACK_Q_DEPTH_PER_CONN + CY_BLE_ADD_Q_DEPTH_PER_CONN) 204 #define CY_BLE_L2CAP_Q_HEAP (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_Q_DEPTH_PER_CONN * \ 205 CY_BLE_L2CAP_QUEUE_ELEMENT_SIZE * CY_BLE_CONN_COUNT)) 206 207 /* If mtu > 23 stack queue depth = (stack queue depth per connection - 1) * maxBleConnection */ 208 #define CY_BLE_GATT_MTU_BUFF_COUNT (CY_BLE_CONN_COUNT * ((CY_BLE_GATT_MTU > CY_BLE_MTU_MIN_VALUE) ? \ 209 (CY_BLE_L2CAP_Q_DEPTH_PER_CONN - 1u) : (CY_BLE_MTU_MIN_BUFF_NUM)) ) 210 211 #define CY_BLE_GATT_MTU_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_GATT_MTU + CY_BLE_MEM_EXT_SZ + \ 212 CY_BLE_L2CAP_HDR_SZ)) 213 214 /* GATT Maximum attribute length */ 215 #define CY_BLE_GATT_MAX_ATTR_LEN ((CY_BLE_GATT_DB_MAX_VALUE_LEN == 0u) ? (1u) : \ 216 (CY_BLE_GATT_DB_MAX_VALUE_LEN)) 217 218 #define CY_BLE_GATT_MAX_ATTR_LEN_PLUS_L2CAP_MEM_EXT \ 219 (CY_BLE_ALIGN_TO_4(CY_BLE_GATT_MAX_ATTR_LEN + CY_BLE_MEM_EXT_SZ + \ 220 CY_BLE_L2CAP_HDR_SZ)) 221 222 /* The header length for Prepare Write Request */ 223 #define CY_BLE_GATT_PREPARE_WRITE_HEADER_LEN (5u) 224 225 /* The header length for Write Request */ 226 #define CY_BLE_GATT_WRITE_HEADER_LEN (3u) 227 228 #define CY_BLE_GATT_PREPARE_LENGTH ((CY_BLE_GATT_RELIABLE_CHAR_LENGTH > CY_BLE_GATT_MAX_ATTR_LEN) ? \ 229 CY_BLE_GATT_RELIABLE_CHAR_LENGTH : CY_BLE_GATT_MAX_ATTR_LEN) 230 231 /* The number of buffers required for Prepare Write Request based on assumption that the negotiated MTU 232 * size is equal to the CY_BLE_GATT_DEFAULT_MTU and all the Characteristics supporting a Reliable Write 233 * property must be written, in order, in a single operation. 234 * The buffer count is 0 when the maximum attribute size is less than the minimum MTU - 3. 235 */ 236 #define CY_BLE_GATT_MAX_PREPARE_BUFF_COUNT \ 237 (((CY_BLE_GATT_MAX_ATTR_LEN <= (CY_BLE_GATT_DEFAULT_MTU - CY_BLE_GATT_WRITE_HEADER_LEN)) && \ 238 (CY_BLE_GATT_RELIABLE_CHAR_COUNT == 0u)) ? 0u : \ 239 ((CY_BLE_GATT_PREPARE_LENGTH / (CY_BLE_GATT_DEFAULT_MTU - CY_BLE_GATT_PREPARE_WRITE_HEADER_LEN)) + \ 240 (((CY_BLE_GATT_PREPARE_LENGTH % (CY_BLE_GATT_DEFAULT_MTU - CY_BLE_GATT_PREPARE_WRITE_HEADER_LEN)) > 0u) ? \ 241 1u : 0u))) 242 243 #define CY_BLE_GATT_PREPARE_LENGTH_ALIGN ((CY_BLE_GATT_MAX_PREPARE_BUFF_COUNT == 0u) ? 0u : \ 244 CY_BLE_ALIGN_TO_4(CY_BLE_GATT_PREPARE_LENGTH)) 245 246 /* The parameter to enable the application to provide a dynamically allocated buffer for Prepare Write Request */ 247 #if defined (CY_BLE_CONFIG_GATT_ENABLE_EXTERNAL_PREP_WRITE_BUFF) 248 #define CY_BLE_GATT_EN_EXT_PREP_WRITE_BUFF \ 249 (CY_BLE_CONFIG_GATT_ENABLE_EXTERNAL_PREP_WRITE_BUFF) 250 #else 251 #define CY_BLE_GATT_EN_EXT_PREP_WRITE_BUFF (0u) 252 #endif /* defined (CY_BLE_CONFIG_GATT_ENABLE_EXTERNAL_PREP_WRITE_BUFF) */ 253 254 255 /* Buffer length for the data received during Prepare Write Requests 256 * For dynamic memory allocation by the application level, set the EnableExternalPrepWriteBuff parameter 257 * in the Expression view of the Advanced tab to true. 258 */ 259 260 #define CY_BLE_GATT_PREPARE_WRITE_BUFF_LEN ((CY_BLE_GATT_EN_EXT_PREP_WRITE_BUFF != 0u) ? 0u : \ 261 (CY_BLE_GATT_PREPARE_LENGTH_ALIGN + \ 262 (CY_BLE_GATT_MAX_PREPARE_BUFF_COUNT * \ 263 sizeof(cy_stc_ble_gatt_handle_value_offset_param_t)))) 264 265 266 /* L2CAP RAM buffer sizes */ 267 #define CY_BLE_L2CAP_MTU_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_MTU + \ 268 CY_BLE_MEM_EXT_SZ + CY_BLE_L2CAP_HDR_SZ)) 269 #define CY_BLE_L2CAP_MPS_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_MPS + CY_BLE_MEM_EXT_SZ + \ 270 CY_BLE_L2CAP_HDR_SZ)) 271 #define CY_BLE_L2CAP_PSM_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4((CY_BLE_L2CAP_PSM_SIZE + CY_BLE_MEM_EXT_SZ) * \ 272 CY_BLE_L2CAP_PSM_COUNT)) 273 #define CY_BLE_L2CAP_CBFC_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4((CY_BLE_L2CAP_CBFC_CHANNEL_SIZE + \ 274 CY_BLE_MEM_EXT_SZ) * CY_BLE_L2CAP_LOGICAL_CHANNEL_COUNT)) 275 #else /* CY_BLE_MODE == CY_BLE_HCI */ 276 #define CY_BLE_MAX_BONDED_DEVICES (CY_BLE_DEFAULT_BONDED_DEVICE_LIST_SZ) 277 #define CY_BLE_MAX_RESOLVABLE_DEVICES (CY_BLE_DEFAULT_RPA_LIST_SZ) 278 #define CY_BLE_MAX_WHITE_LIST_SIZE (CY_BLE_MAX_WHITELIST_LIST_SZ) 279 #define CY_BLE_ENABLE_LL_PRIVACY (1u) 280 #define CY_BLE_GAP_SECURITY_LEVEL (0x0u) 281 #define CY_BLE_L2CAP_Q_DEPTH_PER_CONN (0x0u) 282 #define CY_BLE_GATT_PREPARE_WRITE_BUFF_LEN (0x0u) 283 #endif /* CY_BLE_MODE_PROFILE */ 284 285 /* LL max data length */ 286 #define CY_BLE_LL_MAX_SUPPORTED_TX_PAYLOAD_SIZE (251u) 287 #define CY_BLE_LL_MAX_SUPPORTED_RX_PAYLOAD_SIZE (251u) 288 #define CY_BLE_LL_MIN_SUPPORTED_TX_PAYLOAD_SIZE (27u) 289 #define CY_BLE_LL_MIN_SUPPORTED_RX_PAYLOAD_SIZE (27u) 290 #define CY_BLE_LL_MAX_TX_TIME (0x0848u) 291 292 /* Use maximum payload size (LL max data length) */ 293 #if (CY_BLE_MODE == CY_BLE_PROFILE) 294 /** Max Tx payload size. */ 295 #if !defined(CY_BLE_CONFIG_LL_MAX_TX_PAYLOAD_SIZE) 296 #define CY_BLE_CONFIG_LL_MAX_TX_PAYLOAD_SIZE (0u) 297 #endif /* (!CY_BLE_CONFIG_LL_MAX_TX_PAYLOAD_SIZE) */ 298 #define CY_BLE_LL_MAX_TX_PAYLOAD_SIZE (CY_BLE_CONFIG_LL_MAX_TX_PAYLOAD_SIZE) 299 300 /** Max Rx payload size. */ 301 #if !defined(CY_BLE_CONFIG_LL_MAX_RX_PAYLOAD_SIZE) 302 #define CY_BLE_CONFIG_LL_MAX_RX_PAYLOAD_SIZE (0u) 303 #endif /* (!CY_BLE_CONFIG_LL_MAX_RX_PAYLOAD_SIZE) */ 304 #define CY_BLE_LL_MAX_RX_PAYLOAD_SIZE (CY_BLE_CONFIG_LL_MAX_RX_PAYLOAD_SIZE) 305 306 #else /* Use maximum payload size for HCI mode */ 307 #define CY_BLE_LL_MAX_TX_PAYLOAD_SIZE (CY_BLE_LL_MAX_SUPPORTED_TX_PAYLOAD_SIZE) 308 #define CY_BLE_LL_MAX_RX_PAYLOAD_SIZE (CY_BLE_LL_MAX_SUPPORTED_RX_PAYLOAD_SIZE) 309 #endif /* CY_BLE_MODE_PROFILE */ 310 311 #define CY_BLE_LL_MAX_TX_PAYLOAD_BUFFER_SZ CY_BLE_ALIGN_TO_4(CY_BLE_LL_MAX_TX_PAYLOAD_SIZE) 312 #define CY_BLE_LL_MAX_RX_PAYLOAD_BUFFER_SZ CY_BLE_ALIGN_TO_4(CY_BLE_LL_MAX_RX_PAYLOAD_SIZE) 313 314 #if ((CY_BLE_LL_MAX_TX_PAYLOAD_SIZE > CY_BLE_LL_MIN_SUPPORTED_TX_PAYLOAD_SIZE) || \ 315 (CY_BLE_LL_MAX_RX_PAYLOAD_SIZE > CY_BLE_LL_MIN_SUPPORTED_RX_PAYLOAD_SIZE)) 316 #define CY_BLE_DLE_FEATURE (CY_BLE_DLE_FEATURE_MASK) 317 #define CY_BLE_LL_DLE_HEAP_SZ (CY_BLE_LL_DLE_HEAP_REQ) 318 #else 319 #define CY_BLE_DLE_FEATURE (0u) 320 #define CY_BLE_LL_DLE_HEAP_SZ (0u) 321 #endif /* DLE enabled */ 322 323 #if (CY_BLE_ENABLE_LL_PRIVACY > 0u) 324 #define CY_BLE_LL_PRIVACY_FEATURE (CY_BLE_PRIVACY_1_2_FEATURE_MASK) 325 #define CY_BLE_LL_PRIVACY_HEAP_SZ (CY_BLE_LL_PRIVACY_HEAP_REQ) 326 #define CY_BLE_STORE_RESOLVING_LIST_FEATURE (CY_BLE_PERSISTENT_STORE_RESOLVING_LIST) 327 328 /* Resolving list memory computation */ 329 #define CY_BLE_STACK_RESOLVING_LIST_SIZE ((CY_BLE_LL_PRIVACY_HEAP_SZ * CY_BLE_MAX_RESOLVABLE_DEVICES) + \ 330 CY_BLE_LL_PRIVACY_RETENTION_HEAP_REQ) 331 #else 332 #define CY_BLE_LL_PRIVACY_FEATURE (0u) 333 #define CY_BLE_LL_PRIVACY_HEAP_SZ (0u) 334 #define CY_BLE_STORE_RESOLVING_LIST_FEATURE (0u) 335 #define CY_BLE_STACK_RESOLVING_LIST_SIZE (0u) 336 #endif /* CY_BLE_MAX_RESOLVABLE_DEVICES != 0u */ 337 338 /** Secure Connection feature */ 339 #if !defined(CY_BLE_GAP_SECURITY_LEVEL) 340 #define CY_BLE_GAP_SECURITY_LEVEL (0u) 341 #endif /* !defined(CY_BLE_GAP_SECURITY_LEVEL) */ 342 #if (CY_BLE_GAP_SECURITY_LEVEL == 0x03) 343 #define CY_BLE_SECURE_CONN_FEATURE (CY_BLE_SECURE_CONN_FEATURE_MASK) 344 #define CY_BLE_RAM_SECURE_CONNECTIONS_SIZE (CY_BLE_RAM_SIZE_SECURE_CONNECTIONS) 345 #else 346 #define CY_BLE_SECURE_CONN_FEATURE (0u) 347 #define CY_BLE_RAM_SECURE_CONNECTIONS_SIZE (0u) 348 #endif /* CY_BLE_GAP_SECURITY_LEVEL == 0x03 */ 349 350 /** PHY update enable */ 351 #if !defined (CY_BLE_CONFIG_ENABLE_PHY_UPDATE) 352 #define CY_BLE_ENABLE_PHY_UPDATE (0u) 353 #else 354 #define CY_BLE_ENABLE_PHY_UPDATE (CY_BLE_CONFIG_ENABLE_PHY_UPDATE) 355 #endif /* defined(CY_BLE_CONFIG_ENABLE_PHY_UPDATE) */ 356 357 #if ((CY_BLE_ENABLE_PHY_UPDATE != 0u) || (CY_BLE_MODE_HCI)) 358 #define CY_BLE_PHY_UPDATE_FEATURE (CY_BLE_PHY_UPDATE_FEATURE_MASK) 359 #else 360 #define CY_BLE_PHY_UPDATE_FEATURE (0u) 361 #endif /* (CY_BLE_ENABLE_PHY_UPDATE != 0u) || (CY_BLE_MODE_HCI) */ 362 363 /** Tx 5dbm mode enable */ 364 #if defined (CY_BLE_CONFIG_ENABLE_TX_5DBM) 365 #define CY_BLE_ENABLE_TX_5DBM (1u) 366 #else 367 #define CY_BLE_ENABLE_TX_5DBM (0u) 368 #endif /* defined (CY_BLE_CONFIG_ADD_Q_DEPTH_PER_CONN) */ 369 370 /* Bonded device list auxiliary flash memory computation */ 371 #if !defined (CY_BLE_BONDING_REQUIREMENT) 372 #define CY_BLE_BONDING_REQUIREMENT (CY_BLE_BONDING_NO) 373 #endif /* !defined (CY_BLE_BONDING_REQUIREMENT) */ 374 #if ((CY_BLE_MODE_PROFILE) && (CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES)) 375 376 #define CY_BLE_STORE_BONDLIST_FEATURE (CY_BLE_PERSISTENT_STORE_BONDLIST) 377 378 /* Bonded device list auxiliary flash memory computation. Cypress ID #309591 */ 379 #define CY_BLE_STACK_BOND_FLASH_SIZE ((CY_BLE_STACK_ONE_BONDED_DEVICE_SIZE * CY_BLE_MAX_BONDED_DEVICES) + \ 380 (CY_BLE_STACK_ONE_DEVICE_Q_ENTITY_SIZE * \ 381 (CY_BLE_MAX_CONNECTION_INSTANCES + CY_BLE_MAX_BONDED_DEVICES))) 382 383 /* Bonded device list RAM memory computation */ 384 #define CY_BLE_STACK_BOND_RAM_SIZE ((CY_BLE_STACK_ONE_BONDED_DEVICE_SIZE + \ 385 CY_BLE_STACK_ONE_DEVICE_Q_ENTITY_SIZE) * \ 386 (CY_BLE_CONN_COUNT + CY_BLE_MAX_BONDED_DEVICES)) 387 #else 388 #define CY_BLE_STORE_BONDLIST_FEATURE (0u) 389 #define CY_BLE_STACK_BOND_FLASH_SIZE (0u) 390 #define CY_BLE_STACK_BOND_RAM_SIZE (0u) 391 #endif /* (CY_BLE_MODE_PROFILE) && (CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) */ 392 393 #define CY_BLE_STORE_WHITELIST_FEATURE (CY_BLE_PERSISTENT_STORE_WHITELIST) 394 395 /* White list memory computation */ 396 #define CY_BLE_STACK_WHITELIST_SIZE ((CY_BLE_LL_ONE_WHITELIST_HEAP_REQ * CY_BLE_MAX_WHITE_LIST_SIZE) + \ 397 CY_BLE_LL_WHITELIST_RETENTION_HEAP_REQ) 398 399 #if defined(CY_BLE_CONFIG_TX_POWER_CALIBRATION_ENABLE) && (CY_BLE_CONFIG_TX_POWER_CALIBRATION_ENABLE != 0u) 400 #define CY_BLE_TX_POWER_CALIBRATION_FEATURE (CY_BLE_PERSISTENT_RADIO_CALIBRATION_MASK) 401 #else 402 #define CY_BLE_TX_POWER_CALIBRATION_FEATURE (0u) 403 #endif /* CY_BLE_TX_POWER_CALIBRATION_ENABLE CALIBRATION != 0u */ 404 405 /* BLE Features */ 406 #define CY_BLE_DLE_FEATURE_ENABLED (CY_BLE_DLE_FEATURE != 0u) 407 #define CY_BLE_LL_PRIVACY_FEATURE_ENABLED (CY_BLE_LL_PRIVACY_FEATURE != 0u) 408 #define CY_BLE_SECURE_CONN_FEATURE_ENABLED (CY_BLE_SECURE_CONN_FEATURE != 0u) 409 #define CY_BLE_PHY_UPDATE_FEATURE_ENABLED (CY_BLE_PHY_UPDATE_FEATURE != 0u) 410 411 #define CY_BLE_TX_POWER_CALIBRATION_FEATURE_ENABLED (CY_BLE_TX_POWER_CALIBRATION_FEATURE != 0u) 412 #define CY_BLE_INTR_NOTIFY_FEATURE_ENABLED (CY_BLE_INTR_NOTIFY_FEATURE_ENABLE != 0u) 413 414 415 #define CY_BLE_LL_ACL_TX_HEAP_SZ (CY_BLE_LL_DEFAULT_NUM_ACL_TX_PACKETS * \ 416 (CY_BLE_LL_MAX_TX_PAYLOAD_BUFFER_SZ + \ 417 CY_BLE_LL_ACL_DATA_PACKET_OVERHEAD_SZ + \ 418 CY_BLE_MEM_EXT_SZ)) 419 420 #define CY_BLE_LL_ACL_RX_HEAP_SZ (CY_BLE_LL_DEFAULT_NUM_ACL_RX_PACKETS * \ 421 (CY_BLE_LL_MAX_RX_PAYLOAD_BUFFER_SZ + \ 422 CY_BLE_LL_ACL_DATA_PACKET_OVERHEAD_SZ + \ 423 CY_BLE_MEM_EXT_SZ)) 424 425 426 #define CY_BLE_LL_CONTROLLER_HEAP_REQ ((CY_BLE_DLE_DEVICE_PARAM_SZ) + \ 427 (CY_BLE_LL_DLE_HEAP_REQ * CY_BLE_CONN_COUNT) + \ 428 ((CY_BLE_CONTROLLER_CONN_SPECIFIC_HEAP_REQ + \ 429 CY_BLE_LL_ACL_TX_HEAP_SZ) * CY_BLE_CONN_COUNT) + \ 430 CY_BLE_CONTROLLER_DEVICE_SPECIFIC_HEAP_REQ + \ 431 CY_BLE_LL_ACL_RX_HEAP_SZ + \ 432 CY_BLE_STACK_RESOLVING_LIST_SIZE + \ 433 CY_BLE_STACK_WHITELIST_SIZE) 434 435 /** CRC size for stack flash */ 436 #define CY_BLE_STACK_FLASH_CRC_SIZE (2u) 437 438 /** 439 * \addtogroup group_ble_common_api_macros 440 * \{ 441 */ 442 #if ((CY_BLE_MODE == CY_BLE_PROFILE) && (CY_BLE_HOST_CORE)) 443 444 /* Define controller heap for single CPU mode. For dual CPU mode it will defined as CY_BLE_STACK_CONTROLLER_RAM_SIZE */ 445 #if CY_BLE_STACK_MODE_SOC 446 /** The size of RAM memory required for the Stack controller */ 447 #define CY_BLE_LL_CONTROLLER_HEAP_REQ_SOC (CY_BLE_LL_CONTROLLER_HEAP_REQ) 448 #else 449 /** The size of RAM memory required for the Stack controller */ 450 #define CY_BLE_LL_CONTROLLER_HEAP_REQ_SOC (0u) 451 #endif /* CY_BLE_STACK_MODE_SOC */ 452 453 /** The size of RAM memory required for store attribute handle state (Enable/Disable) */ 454 #if defined(CY_BLE_STACK_APP_POOL_5_SZ) 455 #define CY_BLE_GATT_DB_ATTR_BUFF_SIZE (CY_BLE_ALIGN_TO_4( (CY_BLE_GATT_DB_INDEX_COUNT / 8u) + CY_BLE_MEM_EXT_SZ + \ 456 ((CY_BLE_GATT_DB_INDEX_COUNT % 8u) ? 1u : 0u) )) 457 #else 458 #define CY_BLE_GATT_DB_ATTR_BUFF_SIZE (0u) 459 #endif /*(CY_BLE_STACK_APP_POOL_5_SZ) */ 460 461 /** The size of RAM memory required for the Stack host */ 462 #define CY_BLE_STACK_RAM_SIZE (CY_BLE_ALIGN_TO_4(CY_BLE_DEFAULT_HOST_RAM_SIZE + CY_BLE_LL_CONTROLLER_HEAP_REQ_SOC +\ 463 CY_BLE_RAM_SECURE_CONNECTIONS_SIZE + CY_BLE_L2CAP_Q_HEAP + \ 464 CY_BLE_STACK_BOND_RAM_SIZE + \ 465 (CY_BLE_GATT_MTU_PLUS_L2CAP_MEM_EXT * CY_BLE_GATT_MTU_BUFF_COUNT) + \ 466 (CY_BLE_L2CAP_PSM_PLUS_L2CAP_MEM_EXT * CY_BLE_L2CAP_PSM_COUNT) + \ 467 (CY_BLE_L2CAP_CBFC_PLUS_L2CAP_MEM_EXT * 2u * \ 468 CY_BLE_L2CAP_LOGICAL_CHANNEL_COUNT) + \ 469 (CY_BLE_L2CAP_MTU_PLUS_L2CAP_MEM_EXT * 2u * \ 470 CY_BLE_L2CAP_LOGICAL_CHANNEL_COUNT) + \ 471 (CY_BLE_STACK_BUFFER_MGR_UTIL_RAM_SZ * CY_BLE_STACK_APP_MIN_POOL) + \ 472 (CY_BLE_RAM_SIZE_HOST_SINGLE_CONN * CY_BLE_CONN_COUNT) + \ 473 CY_BLE_GATT_DB_ATTR_BUFF_SIZE + \ 474 (CY_BLE_GATT_PREPARE_WRITE_BUFF_LEN))) /* This buffer must always be the latest */ 475 #else 476 /** The size of RAM memory required for the Stack Controller */ 477 #define CY_BLE_STACK_RAM_SIZE (CY_BLE_LL_CONTROLLER_HEAP_REQ) 478 #endif /* CY_BLE_MODE == CY_BLE_PROFILE) && (CY_BLE_HOST_CORE) */ 479 480 481 482 /** The size of RAM memory required for the Stack Controller */ 483 #define CY_BLE_STACK_CONTROLLER_RAM_SIZE (CY_BLE_LL_CONTROLLER_HEAP_REQ) 484 485 /** The size of flash memory required for the bonding data */ 486 #define CY_BLE_STACK_FLASH_SIZE (CY_BLE_STACK_BOND_FLASH_SIZE + CY_BLE_STACK_RESOLVING_LIST_SIZE + \ 487 CY_BLE_STACK_WHITELIST_SIZE + CY_BLE_STACK_FLASH_CRC_SIZE ) 488 489 /** \} group_ble_common_api_macros */ 490 491 #endif /* CY_BLE_CFG_COMMON_H */ 492 493 /* [] END OF FILE */ 494
